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EE 227

Mixed Signal Circuit Design


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Introduction
Instructor Morris Jones
Intel Corporation
PMorris.jones@intel.com
Web site
Phttp://www.engr.sjsu.edu/mjones
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Class Content
Quick review of CMOS design
PEquations
PCell Design
PModels -- More about BSIM
PMixed Signal
Building blocks
PFunctions
A/D D/A PLL
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You get a Project !! (15%of Grade)
Design, Layout and simulate a CMOS
mixed-signal section!!!
Work in teams
Project ideas
PD/A
PA/D
PHigh speed I/O
PNon Linear circuits
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You get Homework!!! (10%of grade)
Larger problems
PSome will take several weeks
Less crank and grind, more design
PLayout and PC tool use
PSimulations
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You get Exams!!!
Midterm (30% of Grade)
PNormal very long exam
Final (45% of Grade)
PNormal very long exam
PComprehensive
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Adds
Talk to me about it next week
I normally fill the room
PMany Students this year
PPriority
Full time Students with Microelectronics focus
Full time Students who graduate next quarter
Full time Students
Open University will probably not get in L
Some may drop out
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Howto make a MOS Transistor
MOS = Metal Oxide Semiconductor
PIn the early days, it was made of metal!
PPoly-silicon was easier and cheaper to build
PWe are too lazy to change the name to POS
Many Fabrication steps
PKeeps the Chemical and manufacturing
engineers up late at night!
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Add Metal and cover with Glass
N- Substrate
N Well P Well
P+ P+ N+ N+
Gn Poly Gp Poly
SiO
2
SiO
2
Metal (Al)
Glass
Note: Implants not shown
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As Viewed FromAbove
P Well
poly
Metal
Metal
Contacts
Implant Implant
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L and W
P Well
poly
L
W
Implant Implant
Well Removed for clarity
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So Which is the Source and Drain?
In MOS circuits with rectangular gates
PThere is no difference
PIn NMOS,
The most positive is the Drain
The other is the Source
The Body is almost ALWAYS Ground
Life is real fun if it isnt
Not for this class
PIn PMOS Just reverse the signs
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As Viewed FromAbove
P Well
poly
Metal
Metal
Contacts
Implant Implant
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L and W
P Well
poly
L
W
Implant Implant
Well Removed for clarity
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Lamda
Designs are normally performed in
Grid units.
PMakes software easier
Technologies are often scaled
PJust made smaller
Carver-Mead came up with the concept
of using .
PJust state one process in Lambda
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LamdaConcept
Example
PL=2* is the rule
P=1u results in L=2u
PW is then stated in also
PDo entire design in , and translate at the
spice simulation run.
Why
PMove the design from process to process
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So Which is the Source and Drain?
In MOS circuits with rectangular gates
PThere is no difference
PIn NMOS,
The most positive is the Drain
The other is the Source
The Body is almost ALWAYS Ground
Life is real fun if it isnt
Not for this class
PIn PMOS Just reverse the signs
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Current Voltage Curves
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( )
OX
OX
OX
A Si
OX
F SB F T T
OX
B B
OX
OX
OX
B
F GC
OX
OX
OX
B
F GC T
t
C
N q
C
V V V
C
Q Q
C
Q
C
Q
C
Q
C
Q
V





=
=
+ + =

=
=
2
1
2 2
2
2
0
0 0
Threshold Voltage Equation
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This is a simple threshold model!!!
They get much more complex
Not calculated much by hand
The BSIM model will be more fun
Remember that VT varies with V
SB
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[ ]
[ ]
T GS DS
T GS
DS DS T GS
DS DS T GS D
V V V
V V
V V V V
k
V V V V
L
W
k I

=
=
,
2
2
) ( 2
2
) ( 2
2
'
Current in the linear region
Once there are free electrons, they can
conduct current.
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This is only a model
Derived from physics
Only used for design
All simulators use more complex
models
Good enough for design
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When VDS > VGS- VT
Pinch-off occurs
PChannel changes little after this
PCurrent stays about the same
Wait for effective L later
2
) (
2
T GS D
V V
k
I =
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) 1 ( ) (
2
2
DS T GS D
V V V
k
I + =
Only partly good
This equation shows a perfect current
source
PNever happens
PAdd an Effective Length factor
Just a first order correction
Magic
correction
term
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This adds some slope to curves
The (1+V
DS
) term must be placed on
the linear equation also
PThere will be a discontinuity between the
two
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Modeling Problems
Spice iterates to solve the voltage and
current equations of the circuit
Transistors have different slopes from
linear to saturated modes
Curve fitting doesnt always work
Model may not Converge to a solution
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Temperature Effects
Many items change with Temperature
PNi
P
( )
a
T
T
300 /
) 300 (
) (

=
Where a is the mobility exponent with temperature (Between 1 and 1.5)
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Notation Issues
Some use k some
This book uses
PThey are the same thing!!!
PNewer books use k since was already
taken by Bi-Polar
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Designing Analog
These equations get real ugly in a hurry
PDo not come to closed solutions
Most Analog centered around small
signals
Make a simplification
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g
m
( )
D sat m
ds linear m
ds
gs
ds
m
I Vt Vgs g
V g
C V
dV
dI
g

2
) (
) (
= =
=
= =
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Homework
Will use TSMC 0.25u rules
BSIM3 Model
PGet used to it now
Look on Sheets for k and terms
Last Semester focused on project
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Challenge Problem
Vo
Vi
R
R
W/L
What is the equation for Vo in terms
of Vi, R, and W/L?

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