Professional Documents
Culture Documents
ISSN: 2278-0181
Vol. 3 Issue 5, May - 2014
I.
Introduction
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II.
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875
Constant
Freq_6Axles
Rectifer DC volts
controlsignal_6Axles
6 step0_PWM_6 Axles
dc bus volts
Freq
Vabc_ph
controlSignalAmp
vabc_ph
is_abc_Amps
Currents
inverterModeSelect
SIX INVERTERS
Stator_ave_degC
ir_abc_Amps
Stator_ave_degC
Rotor_cond_degC
Rotor_cond_degC
motorSpeedRPM
PfricWind_W
Pelec_losses
w_RPM
PfricWind
Te_Nm
Torques
III.
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1.
2.
3.
4.
5.
IV.
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+0.5Vdc and 0 are the upper and lower signal inputs for the
three top level switches whereas the other three bottom level
switches have -0.5Vdc and 0 as the upper and lower signal
inputs. Thus according to the gating pulses various switch
outputs are obtained. These outputs are then appropriately
calculated to generate phase or line voltages. The fig shows
the schematic diagram of the inverter model.
1
Vs1_1
1
Constant1
g1_1
Comparator, #1
Carrier
1
g1_1
Constant3
0
Constant13
g4_1
Vs2_1
g4_1
Constant11
V.
OPERATION OF INVERTER
1
Constant5
g3_1
0
Comparator, #2
3
g3_1
Constant15
0
Constant12
Vs3_1
g6_1
1
Constant18
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Constant7
g5_1
0
Comparator, #3
g6_1
g5_1
Constant22
0
Constant20
g2_1
g2_1
Constant19
Vpulse
3
A0
In1
1
Vabc_ph
g3
Demux
Van
g4
2
Van
B0
In2
g5
Vbn
3
Vbn
g6
+0.5Vdc
1
2
-0.5Vdc
+0.5Vdc
C0
In3
Vcn
4
Vcn
-0.5Vdc
Subsystem
Subsystem1
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Fig 16. Relation between torque and time for single device fault
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