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Code No: 57039 Set No. 1
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.Tech. I Sem., II Mid-Term Examinations, October 2013
DSP PROCESSORS AND ARCHITECTURE
Objective Exam
Name: ______________________________ Hall Ticket No.

Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.

I. Choose the correct alternative:

1. __________filter is represented by a transfer function, which is a ratio of two polynomials in z. [ ]
A) FIR B) Low pass C) IIR D) High pass

2. The Q-notation specifies ___________ [ ]
A) Number of valid bits B) Number of filter coefficients
C) Number of guard bits D) Number of fractional bits

3. HPI unit allows the DSP to interface to an ________ host device [ ]
A) 8 Bit or 16 Bit B) 2 Bit or 4 Bit C) 16 Bit or 32 Bit D) None

4. The internal clock source option of clock generator uses an [ ]
A) Internal clock generator B) Phase locked loop circuit C) Both A & B D) none

5. The Multiplier of CPU in TMS320C54xx Processor is _____ bit. [ ]
A) 16x16 B) 17x17 C) 20x20 D) 40x40

6. Hardware timer is an onchip _________ counter that can be used to generate a signal to
down initiate an interrupt or to initiate any other process. [ ]
A) Up-Down B) Down C) Up D) None

7. The Decimation filter is used to ____ sampling rate. [ ]
A) Double B) Increase C) Decrease D) Half

8. A _______ filter is a filter whose coefficients can be updated on-line to counter varying signal
distortions. [ ]
A) IIR Filter B) Adaptive Filter C) FIR Filter D) Interpolation filter

9. ____________ Ports are used for interfacing external devices such as A/D and D/A Converters to DSP
Processors. [ ]
A) Serial I/O B) Sequential I/O C) Parallel I/O D) All

10. The CPU of TMS320C54xx Processor consists of _____ accumulators. [ ]
A) 2 B) 3 C) 4 D) 5


Cont..2




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Code No: 57039 :2: Set No. 1


II Fill in the Blanks

11. The TMS320C54xx devices consists of 64K words of__________________

12. Function of RPT #k Instruction executes ____________ times.

13. In ______________ addressing, any location in the data space can be accessed by means of an address
contained in an auxiliary register.

14. If the naturally occurring input time-sequence sample indices are bit reversed and processed by the
algorithm, the frequency domain output is in the natural order, such a computation is called a
________________

15. CSSU stands for _______________________________

16. Barrel shifter in TMS Processor produces ____________ bits of left shift and _________ bits of right
shift.

17. The length of guard bits of the accumulator of TMS320C54xx Processor is ___________.

18. _____________ Processors have one program & three data memory spaces with separate buses.

19. In Bit-Reversed Addressing mode, ________________ register specifies one half of the size of the FFT.


20. The 2- point DIT requires only _____________ and __________operations to implement
butterfly.






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Code No: 57039 Set No. 2
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.Tech. I Sem., II Mid-Term Examinations, October 2013
DSP PROCESSORS AND ARCHITECTURE
Objective Exam
Name: ______________________________ Hall Ticket No.

Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.

I. Choose the correct alternative:

1. The internal clock source option of clock generator uses an [ ]
A) Internal clock generator B) Phase locked loop circuit C) Both A & B D) none

2. The Multiplier of CPU in TMS320C54xx Processor is _____ bit. [ ]
A) 16x16 B) 17x17 C) 20x20 D) 40x40

3. Hardware timer is an onchip _________ counter that can be used to generate a signal to
down initiate an interrupt or to initiate any other process. [ ]
A) Up-Down B) Down C) Up D) None

4. The Decimation filter is used to ____ sampling rate. [ ]
A) Double B) Increase C) Decrease D) Half

5. A _______ filter is a filter whose coefficients can be updated on-line to counter varying signal
distortions. [ ]
A) IIR Filter B) Adaptive Filter C) FIR Filter D) Interpolation filter

6. ____________ Ports are used for interfacing external devices such as A/D and D/A Converters to DSP
Processors. [ ]
A) Serial I/O B) Sequential I/O C) Parallel I/O D) All

7. The CPU of TMS320C54xx Processor consists of _____ accumulators. [ ]
A) 2 B) 3 C) 4 D) 5

8. __________filter is represented by a transfer function, which is a ratio of two polynomials in z. [ ]
A) FIR B) Low pass C) IIR D) High pass

9. The Q-notation specifies ___________ [ ]
A) Number of valid bits B) Number of filter coefficients
C) Number of guard bits D) Number of fractional bits

10. HPI unit allows the DSP to interface to an ________ host device [ ]
A) 8 Bit or 16 Bit B) 2 Bit or 4 Bit C) 16 Bit or 32 Bit D) None



Cont..2



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Code No: 57039 :2: Set No. 2


II Fill in the Blanks

11. If the naturally occurring input time-sequence sample indices are bit reversed and processed by the
algorithm, the frequency domain output is in the natural order, such a computation is called a
________________

12. CSSU stands for _______________________________

13. Barrel shifter in TMS Processor produces ____________ bits of left shift and _________ bits of right
shift.

14. The length of guard bits of the accumulator of TMS320C54xx Processor is ___________.

15. _____________ Processors have one program & three data memory spaces with separate buses.

16. In Bit-Reversed Addressing mode, ________________ register specifies one half of the size of the FFT.


17. The 2- point DIT requires only _____________ and __________operations to implement
butterfly.

18. The TMS320C54xx devices consists of 64K words of__________________

19. Function of RPT #k Instruction executes ____________ times.

20. In ______________ addressing, any location in the data space can be accessed by means of an address
contained in an auxiliary register.







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Code No: 57039 Set No. 3
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.Tech. I Sem., II Mid-Term Examinations, October 2013
DSP PROCESSORS AND ARCHITECTURE
Objective Exam
Name: ______________________________ Hall Ticket No.

Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.

I. Choose the correct alternative:

1. Hardware timer is an onchip _________ counter that can be used to generate a signal to
down initiate an interrupt or to initiate any other process. [ ]
A) Up-Down B) Down C) Up D) None

2. The Decimation filter is used to ____ sampling rate. [ ]
A) Double B) Increase C) Decrease D) Half

3. A _______ filter is a filter whose coefficients can be updated on-line to counter varying signal
distortions. [ ]
A) IIR Filter B) Adaptive Filter C) FIR Filter D) Interpolation filter

4. ____________ Ports are used for interfacing external devices such as A/D and D/A Converters to DSP
Processors. [ ]
A) Serial I/O B) Sequential I/O C) Parallel I/O D) All

5. The CPU of TMS320C54xx Processor consists of _____ accumulators. [ ]
A) 2 B) 3 C) 4 D) 5

6. __________filter is represented by a transfer function, which is a ratio of two polynomials in z. [ ]
A) FIR B) Low pass C) IIR D) High pass

7. The Q-notation specifies ___________ [ ]
A) Number of valid bits B) Number of filter coefficients
C) Number of guard bits D) Number of fractional bits

8. HPI unit allows the DSP to interface to an ________ host device [ ]
A) 8 Bit or 16 Bit B) 2 Bit or 4 Bit C) 16 Bit or 32 Bit D) None

9. The internal clock source option of clock generator uses an [ ]
A) Internal clock generator B) Phase locked loop circuit C) Both A & B D) none

10. The Multiplier of CPU in TMS320C54xx Processor is _____ bit. [ ]
A) 16x16 B) 17x17 C) 20x20 D) 40x40



Cont..2



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Code No: 57039 :2: Set No. 3


II Fill in the Blanks

11. Barrel shifter in TMS Processor produces ____________ bits of left shift and _________ bits of right
shift.

12. The length of guard bits of the accumulator of TMS320C54xx Processor is ___________.

13. _____________ Processors have one program & three data memory spaces with separate buses.

14. In Bit-Reversed Addressing mode, ________________ register specifies one half of the size of the FFT.


15. The 2- point DIT requires only _____________ and __________operations to implement
butterfly.

16. The TMS320C54xx devices consists of 64K words of__________________

17. Function of RPT #k Instruction executes ____________ times.

18. In ______________ addressing, any location in the data space can be accessed by means of an address
contained in an auxiliary register.

19. If the naturally occurring input time-sequence sample indices are bit reversed and processed by the
algorithm, the frequency domain output is in the natural order, such a computation is called a
________________

20. CSSU stands for _______________________________







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Code No: 57039 Set No. 4
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY HYDERABAD
IV B.Tech. I Sem., II Mid-Term Examinations, October 2013
DSP PROCESSORS AND ARCHITECTURE
Objective Exam
Name: ______________________________ Hall Ticket No.

Answer All Questions. All Questions Carry Equal Marks. Time: 20 Min. Marks: 10.

I. Choose the correct alternative:

1. A _______ filter is a filter whose coefficients can be updated on-line to counter varying signal
distortions. [ ]
A) IIR Filter B) Adaptive Filter C) FIR Filter D) Interpolation filter

2. ____________ Ports are used for interfacing external devices such as A/D and D/A Converters to DSP
Processors. [ ]
A) Serial I/O B) Sequential I/O C) Parallel I/O D) All

3. The CPU of TMS320C54xx Processor consists of _____ accumulators. [ ]
A) 2 B) 3 C) 4 D) 5

4. __________filter is represented by a transfer function, which is a ratio of two polynomials in z. [ ]
A) FIR B) Low pass C) IIR D) High pass

5. The Q-notation specifies ___________ [ ]
A) Number of valid bits B) Number of filter coefficients
C) Number of guard bits D) Number of fractional bits

6. HPI unit allows the DSP to interface to an ________ host device [ ]
A) 8 Bit or 16 Bit B) 2 Bit or 4 Bit C) 16 Bit or 32 Bit D) None

7. The internal clock source option of clock generator uses an [ ]
A) Internal clock generator B) Phase locked loop circuit C) Both A & B D) none

8. The Multiplier of CPU in TMS320C54xx Processor is _____ bit. [ ]
A) 16x16 B) 17x17 C) 20x20 D) 40x40

9. Hardware timer is an onchip _________ counter that can be used to generate a signal to
down initiate an interrupt or to initiate any other process. [ ]
A) Up-Down B) Down C) Up D) None

10. The Decimation filter is used to ____ sampling rate. [ ]
A) Double B) Increase C) Decrease D) Half



Cont..2



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Code No: 57039 :2: Set No. 4


II Fill in the Blanks

11. _____________ Processors have one program & three data memory spaces with separate buses.

12. In Bit-Reversed Addressing mode, ________________ register specifies one half of the size of the FFT.


13. The 2- point DIT requires only _____________ and __________operations to implement
butterfly.

14. The TMS320C54xx devices consists of 64K words of__________________

15. Function of RPT #k Instruction executes ____________ times.

16. In ______________ addressing, any location in the data space can be accessed by means of an address
contained in an auxiliary register.

17. If the naturally occurring input time-sequence sample indices are bit reversed and processed by the
algorithm, the frequency domain output is in the natural order, such a computation is called a
________________

18. CSSU stands for _______________________________

19. Barrel shifter in TMS Processor produces ____________ bits of left shift and _________ bits of right
shift.
20. The length of guard bits of the accumulator of TMS320C54xx Processor is ___________.







-oOo-

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