A Broadband CMOS Multiplier-Based Correlator for IR-UWB

Transceiver SoC
Haolu Xie
1
, Xin Wang
1
, Albert Wang
1
, Bin Zhao
2
, Lee Yang
3
, and Yumei Zhou
4

1
3301 S. Dearborn St., Chicago, IL, USA Dept. of Electrical & Computer Engineering, Illinois
Institute of Technology, awang@ece.iit.edu,
2
Freescale Semiconductor, USA,
3
Semiconductor
Manufacturing International Corporation, China, and
4
Institute of Microelectronics Chinese Academy
of Sciences, China

Abstract a multiplier-based correlator is an important
component for impulse radio ultra-wideband (IR-UWB)
receiver. Classified as correlation-type demodulator, this
type of correlator uses correlation-type demodulation. This
paper reports design and implementation of a fully
integrated low-power broadband multiplier-based
correlator for a 3.1-10.6GHz full-band UWB receiver in
0.18m CMOS that consists of an UWB multiplier and a
first-order RC integrator with a 200MHz bandwidth.
Measurement results confirm the correlation-type
demodulation function and achieve a conversion gain of
0dB, noise figure of 8.2dB and power consumption 52mW
for the UWB multiplier.
Index Terms UWB, multiplier, correlator, noise figure,
demodulation, conversion gain.
I. INTRODUCTION
UWB radio development is gaining momentum
since the FCC opened the door for commercial
development in 2002 [1]. The FCC allocated frequency
spectrum for UWB is the unlicensed 3.1-10.6GHz band.
Currently, there are two major IEEE UWB radio
schemes, i.e., multi-band (MB) OFDM and direct
sequence (DS) [2, 3], both dividing the 7.5GHz UWB
bandwidth into multiple sub-bands and use carrier in
radio transmission. An alternative UWB radio solution is
a fully pulse-based, non-carrier, single-band (7.5GHz),
most-digital, all-CMOS UWB transceiver that can take
the full advantages of the original impulse UWB radio
technology to achieve the required multi-Gbps
throughput. Recently, research on developing such full-
band impulse radio UWB transceiver IC has attracted
significant attentions [4-6]. A correlator is critical and
indispensable circuit block in the receiving channel of
any IR-UWB transceiver IC chips. Fig.1 shows a typical
pulse-based UWB transceiver architecture where the
correlator block is marked with the dashed line [6]. The
typical correlator works as a correlation-type
demodulator. The core of the UWB correlator is an ultra
wideband multiplier circuit. Papers [7, 8] discussed
simulation results of CMOS multipliers without
measurements.
In traditional RF switched-mixer type UWB
multipliers [4-6], the LO signal must be optimized strong
enough to ensure the switching function of LO stage
transistors and the key concern in design is the linearity
of RF signal only.

Fig.1 A pulse-based UWB transceiver architecture contains a
correlator block marked in dashed line.

However, a RF multiplier is different from the RF
switched-mixer because both the linearity of RF and LO
signals must be enforced in a multiplier. Hence, a
multiplier circuit is a bilinear circuit. Also, in a multiplier
circuit, all transistors operate in a single mode, not a
switching mode, and the input power of the LO signal
cannot be too strong in order to achieve good LO linearity
at the output port. Therefore, a traditional switched-mixer
does not work as a good multiplier because switching
behavior degrades the LO signal linearity of the
multiplier and results in poor signal noise ratio (SNR) of
a correlator circuit [9]. This argument can be theoretically
understood using the correlation-type demodulation
scheme shown in Fig. 2. Assume there are N users
communicating at the same time and each user signal is
pre-signed uniquely by ) (t
n
. The )} ( { t
n
consists of a
series of orthogonal pulse signals, ) (t with the
following features:
m n nt consta dt t t
m
T
n
= =

, ) ( ) (
0
(1)
1-4244-0530-0/1-4244-0531-9/07/$20.00 2007 IEEE 2007 IEEE Radio Frequency Integrated Circuits Symposium 493
m n dt t t
m
T
n
=

, 0 ) ( ) (
0
(2)


Fig.2 Correlation-type demodulation.

The received signals can be expressed as
) ( ) ( ) ( t n t t r
m m
+ = , where m=1,2,N and n(t) is the
channel additive noise. Hence, we have
m n t N nt consta dt t t r
m m
T
n
= + =

, ) ( ) ( ) (
0
(3)
m n t N dt t t r
m m
T
n
=

), ( ) ( ) (
0
(4)
Where )} ( { t N
m
are random variables coming from the
presence of the channel additive noise.
According to (3) and (4), if an ideal multiplier, which
is bilinear with both RF and LO signals, is used for a
correlator circuit, after the demodulation, the correlator
output will only contain the desired user signal plus
channel noise, while the undesirable user interfering
signals can be 100% attenuated to 0. This ensures the
maximum SNR at the output [9]. However, if a traditional
switched-mixer is used as the correlator core, its output
will contain both the desired signals and the unwanted
interferers, resulting in poor SNR.
In this paper, we report a fully integrated low power
3.1-10.6GHz UWB correlator designed and fabricated in
a commercial 0.18m CMOS.

II. UWB CORRELATOR CIRCUIT DESIGN
The full-band 3.1-10.6GHz UWB correlator circuit
was designed and implemented in a 0.18m CMOS
technology. Fig. 3 shows the schematic of the UWB
correlator core circuit. The UWB correlator consists of a
multiplier and a RC integrator. The multiplier features a
double-balanced topology that is followed by a first-order
RC integrator with a 200MHz bandwidth. A source
follower buffer is used to drive the 50 ohms testing port.
For this CMOS multiplier circuit, if the transistors are
biased in saturation region, the drain current
D
I is
expressed by,

) 1 ( ) (
2
1
2
DS TH GS D
V V V K I + =
(5)
where L W c k
ox
/
0
= is transconductance,
TH
V is the
threshold voltage and represents the channel-length
modulation effect. Clearly, low power consumption
requires a low
D
I , hence a small
GS
V , which will lead to
a reduced input linear range, resulting in a degraded
linearity. This is highly undesirable for a correlation-type
demodulator. On the other hand, if the transistors are
biased into triode region where the drain current is given
by,
]
2
1
) [(
2
DS DS TH GS D
V V V V K I =
, (6)
the drain current can be obtained while keeping a
relatively large input range. Since
DS TH GS
V V V > in
triode region, a large overdrive voltage can be used to
increase the input range. The drain current can remain to a
proper value by reducing
DS
V to keep the power
dissipation low. Considering the fact that PMOS
transistors need less drain current for larger overdrive
voltage
TH GS
V V compared with NMOS transistors,
PMOS transistors are preferred in the pulse template input
terminals at l(t) in Fig. 1, while NMOS transistors should
be used in the RF input signal terminal for r(t) in Fig. 1,
because mostly the power level of local pulse template
signal l(t) is higher than that of the received signal r(t)
though r(t) is amplified by a low noise amplifier. Hence,
l(t) requires a larger dynamic range. In this paper, the
upper case letters, R(t) and L(t), represent common-mode
(DC bias) components, while the lower case letters, r(t)
and l(t), represent small (input AC) signals. Based upon
the above analysis, to achieve low-power multiplier
design, we bias most transistors (N1-N4 and M1-M4) into
triode region while set PMOS devices (P1-P4) operate in
saturation region. With all transistors in Fig.3 biased into
the proper operating region, we can get,

)] ( 1 [ |) | ) ( ) ( (
2
1
1
2
1 P DD THP DD P P
V V V t l t L V K i + =
(7)
and the same for
2 P
i ,
3 P
i and
4 P
i , while,

) )( ) ( ) ( [(
1 1 1 1 P O THN P N
V V V V t r t R K i + =
] ) (
2
1
2
1 1 P O
V V
(8)
494
( ) ( ) L t l t + ( ) ( ) R t r t + ( ) ( ) R t r t
( ) ( ) L t l t
( ) ( ) L t l t +
( ) ( ) L t l t
( ) ( ) R t r t + ( ) ( ) R t r t
1 p
i
2 p
i
3 p
i
4 p
i
4 M
i
3 M
i
2 M
i
1 M
i
1
i
2
i
3
i
4
i

Fig. 3 Schematic for the UWB correlator core circuit in this work.

and the same for
2
i ,
3
i and
4
i . In addition, we have,
1 1 1 M P
i i i = + ,
2 2 2 M P
i i i = ,
3 3 3 M P
i i i = + , and
4 4 4 M P
i i i = . The transistors M1-M4 can be considered
as the resistors with resistance approximately equal to
) (
1
THN DD M
ON
V V K
R

. Solving the above equations

with
2 1
i i = and
4 3
i i = gives the following approximated
result,

) ( ) (
2 1
t l t r
K
K K
V V
P
M N
O O

(9)

which is a multiplication of two input signals, r(t) and l(t).
Transfer function of the first-order RC integrator in
Fig.3 can be derived as,

Cs R
R
R
s H
2
2
1
) 1 (
1
) (
+ +
=
(10)
A bandwidth of 200MHz for the integrator is designed
by properly selecting the
1
R ,
2
R and C values. From (9)
and (10), a correlation-type demodulator can be
constructed as a correlator circuit for IR-UWB receiver.
III. SIMULATION AND MEASUREMENT
This fully-integrated 7.5GHz UWB correlator circuit is
designed and fabricated in a commercial 0.18m CMOS.
Fig. 4 shows the die photo for this correlator. Parasitic
effects of the bonding pads are considered in the correlator
design and measurements. Figs. 5 & 6 show that the
multiplier achieves a conversion gain of 0dB and NF of
8.2dB over the full 7.5GHz UWB bandwidth. Fig. 7
shows the transient results of the multiplier, which clearly
shows that the multiplier output equals to the product of
r(t) and l(t). The correlator output is that of the multiplier
filtered by the following integrator. Fig. 8 compares the
correlator output results from simulation and measurement,
which shows good agreement. The demodulated 1
signals in Fig. 8 have a time width of 6ns and an
amplitude of 70mV, adequate for driving the following
ADC stage of the UWB SoC in this work. The 0 signals
have a time width of 6ns and an amplitude of -70mV. The
correlator circuit consumes a low 52mW at 1.8V
excluding the buffer.


Fig. 4 Die photo of the UWB correlator circuit.

495

Fig. 5 UWB multiplier conversion gain.


Fig. 6 UWB multiplier noise figure.

Fig. 7 UWB multiplier transient results
IV. CONCLUSION
This paper reports a fully-integrated low-power 3.1-
10.6GHz UWB correlator circuit designed and fabricated
in a 0.18m CMOS for a full-band non-carrier impulse
UWB receiver. The correlator circuit uses double-balance
multiplier followed by an RC integrator to achieve the
desired UWB multiplication, conversion gain, noise
performance, and the overall correlation-type
demodulation. Measurement over the full 7.5GHz UWB
spectrum confirms the correlation-type demodulation
function and show a conversion gain of 0dB, a minimum
NF of 8.2dB and a low power of 52mW at 1.8V.







0.0 10.0n 20.0n 30.0n 40.0n 50.0n 60.0n
0.25
0.30
0.35
0.40
0.45 Correlator Transient Output
A
m
p
l
i
t
u
d
e

(
V
)
Time (S)
Measurment
Simulation
Fig. 8 Comparison transient output signals of UWB correlator
from simulation & measurement.
REFERENCES
[1] FCC First Report and Order, FCC 02-48, Feb 14, 2002.
[2] IEEE 03268r3P802-15 TG3a Multiband CFP.
[3] IEEE 15-04-0137-03-003 a merger2 proposal DS-UWB-
update.
[4] T. Terada, S. Yoshizumi, Y. Sanada and T. Kuroda,
Transceiver circuits for pulse-based ultra-wideband
Circuits and Systems, IEEE ISCAS Symp, Vol.4, pp 349-
52, 2004.
[5] Y. Zheng, Y. Tong, J. Yan, Y. Xu, W. Yeoh and F. Lin, A
low power noncoherent CMOS UWB transceiver ICs
IEEE RFIC Symp, pp. 347-350, 2005.
[6] H. Xie, S. Fan, X. Wang, A. Wang, Z. Wang and H. Chen;
A pulse-based full-band UWB transceiver SoC in 0.18m
SiGe BiCMOS, IEEE SoC Conf, pp.73-76, 2006.
[7] G. Han and E. Sanchez-Sinencio, CMOS transconductance
multipliers: A tutorial, IEEE TCAS-II, Vol. 45, No. 12, pp.
1550-1563, Dec. 1998.
[8] L. Zhou, Y. Xu and F. Lin; A gigahertz wideband CMOS
multiplier for UWB transceiver, IEEE ISCAS, Symp, Vol.
5, pp 5087 5090, 2005.
[9] J. Proakis, Communication Systems Engineering,
Prentice Hall, ISBN-0130617938, 2001.
496