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DEVICE MODELLING MINI-PROJECT

FREQUENCY DIVIDERS













Joshua David Serrao BT08ECE059






Department of Electronics and Communication
Visvesvaraya National Institute of technology
Nagpur -440 010 India
October 2011


ABSTRACT

This project shows how to divide a clock frequency by odd and non-integer numbers to obtain 50%
duty cycle. Dividing an incoming clock by an integer number is trivial. And dividing by an even
number always generates a 50% duty cycle. But sometimes it is necessary to generate. Clock pulses at
50% duty cycle that is not an integer sub-multiple of the input clock. This device is cheaper and faster
than a phase locked loop.


INTRODUCTION

Each circuit assumes a 50% duty cycle of the input clock signal, otherwise the fractional divider output
will jitter. And the integer divider will have non 50% duty cycle. The circuits are combinatorial circuits,
some with feedback around a look up table (k map). It works perfectly to prevent glitch free output,
but may cause the simulator to fail. The circuit consist of D flip flops and gates all made from MOS
transistors. The clock is given to all the clock inputs of the D flip-flops the inputs of the D flip-flops are
obtained from the excitation table of a D flip-flop feed-backing the outputs and using K map method.
The outputs obtained are the out puts of a counter. Thus the circuit is a counter. It will count states.
These outputs are fed to combinatorial circuits to obtain the desired outputs of clock frequency. These
outputs are feed backed into the circuit to give glitch free output.
Thus in a clock divider by 3 circuit. If the input frequency is 90 kHz then a clock output of 30 kHz can
be obtained.


LITERATURE SURVEY

Conventional frequency synthesis techniques in used today may be classified as following 3 types.
a) Phase locked loop PLL based or 'indirect'
b) Mixer /filter/ divide or 'indirect analog'
c) Direct digital synthesis

Each of these has some advantages and disadvantages. Direct analog synthesis uses the functional
elements of multiplication, division or other mathematical technique to produce the desired frequency
but this method is very expensive. DDs uses logic and memory to digitally construct the desired output
signal on the output a digital to analog converter is used to convert it from digital to analog domain.
PLL is widely used, but it has one major drawback is that PLL with a wide frequency range cannot be
achieved easily.

Frequency divider can be made using injection locked oscillator. It usually exhibits poor phase noise
performance but with proper modifications good results can be achieved.









DESCRIPTION

X.cir

Clk A B Vout Vout2
L 0 0 0 1
H 0 0 0 0
L 1 0 1 1
H 1 0 1 1
L 0 1 1 0
H 0 1 0 1







Truth table for D flip flop

D Q
0 0
1 1

Excitation table for D flip flop

Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1

X.cir

Vout = F (clk,A,B)
The circuit works as a counter that counts states. Thus two flip-flops are used to generate three states in
a clock divide by 3 and 1.5 circuit. Similarly three flip-flops are used which can generate up-to eight
states.

For generation of five states required for getting an output of clock divide by 5 and 2.5, a common
clock is given to all the 2/3 flip-flops. The outputs of these flip-flops are used to get the required clock
output.

D

Let us consider the example of clock divide by 3 and 1.5 circuit


The above circuit is a circuit which divides the clock frequency by 3 and by 1.5

As it can be seen the circuit contains 2 flip-flops the output of the first flip flop A given as an input to
the second flip-flops Db. While the input to the first flip flop Da is the logical AND of the outputs of
the flip flop A' and B' giving clock to this circuit generates the following counter

Clk A B Vout Vout2
L 0 0 0 1
H 0 0 0 0
L 1 0 1 1
H 1 0 1 1
L 0 1 1 0
H 0 1 0 1

The first column is the clock pulse applied to the clock input. The clock is negative edge triggered the
outputs A and B are the second and third columns of the table thus it can be seen that the circuit acts as
a mod 3 counter having states 00 10 01 and back. This counter is used to generate a clock frequency
1/3rd and 1/1.5 of the original clock input with 50% duty cycle to get the desired out puts we create a
combinatorial circuit of the input clock (CLK) and the outputs of the flip-flops A and B
We have assumed a particular set of outputs that could be obtained through a particular combination of
CLK, A, B this assumption is as shown in the truth table above. Assumptions for clock divide by 3 i.e.
Vout and clock divide by 1.5 i.e. Vout2 are made.


Using the basic concepts of K map solving
Vout =F (CLK, A, B)
Similarly
Vout2 =F (CLK, A, B)

solving this K map

Vout A'B' A'B AB AB'
CLK' 0 1 X 1
CLK 0 0 X 1

The solution to this K map is Vout = CLK ' B +A
Similarly solving the Kmap for Vout2

Vout 2 A'B' A'B AB AB'
CLK' 1 0 X 1
CLK 0 1 X 1


The solution to this is Vout2 = ClK^B + A
It should be noted that the connections of Da and Db could be obtained from the truth table of the
divide by three circuit and using the excitation table of the D flip-flops used.

Like in the following manner

Clk A B Anext Bnext
L 0 0 1 0
H 0 0 1 0
L 1 0 0 1
H 1 0 0 1
L 0 1 0 0
H 0 1 0 0


Da = F( A, B)
Db = F(A, B)

Da B' B
A' 1 0
A 0 X

Da = A'.B'

Similarly we can obtain for Db

Db B' B
A' 0 0
A 1 X

Therefore Db= A

Gates used

GATE No of transistors used in the gate
Not 2
2ip AND 6
2ip OR 6
3ip AND 8
3ip OR 8
2 ip NAND 6
2ip NOR 6
D flip flop 40


The AND, OR, NAND, NOR are created using MOS transistors and are used as block in the simulation.
A D flip-flop has been created with the name D_ff . It is used as an IC as shown in the above circuit
figure.

Thus the following table shows the total requirement of transistor for the above divide by 3, 1.5 circuit

GATE/ IC / BLOCK Number Total transistor
D flip-flop 2 40
NOT 1 2
2 ip AND 3 18
2 ip OR 4 24
Total 124

Thus a total of 124 transistors are required to make a clock divide by 3, 1.5 circuit




Following is the NGSPICE PROGRAM

* X.cir clock divide by 3 and 1.5
XX12 Vdd CLK _CLK not
V1 CLK 0 PULSE(0 5 5 1u 1u 5 10)
Vdd Vdd 0 5
XX1 CLK N001 Vdd _A A D_ff
XX2 CLK A Vdd _B B D_ff
XX3 _A _B Vdd N001 and
XX5 B CLK Vdd N003 and
XX7 _B _CLK Vdd N002 and
XX4 N002 N003 Vdd C or
XX6 C A Vdd Vout2 or
XX8 Vout A Vdd N004 or
XX9 _CLK _B Vdd N005 or
XX10 N004 N005 Vdd Vout and

* block symbol definitions
.subckt not Vdd Vin Vout
M1 Vout Vin Vdd Vdd PMOS
M2 Vout Vin 0 0 NMOS
.ends not

.subckt D_ff CP D Vdd _Q Q
M1 F1 _Q Vdd Vdd PMOS
M2 F1 D Vdd Vdd PMOS
M3 F1 CP Vdd Vdd PMOS
M4 F1 _Q P001 P001 NMOS
M5 P001 D P002 P002 NMOS
M6 P002 CP 0 0 NMOS
M7 _Y F2 P003 P003 NMOS
M8 P003 Y 0 0 NMOS
M9 _Y F2 Vdd Vdd PMOS
M10 _Y Y Vdd Vdd PMOS
M11 _CP CP Vdd Vdd PMOS
M12 _CP CP 0 0 NMOS
M13 F2 CP Vdd Vdd PMOS
M14 F2 _D Vdd Vdd PMOS
M15 F2 Q Vdd Vdd PMOS
M16 F2 CP P004 P004 NMOS
M17 P004 _D P005 P005 NMOS
M18 P005 Q 0 0 NMOS
M19 Y F1 P006 P006 NMOS
M20 P006 _Y 0 0 NMOS
M21 Y F1 Vdd Vdd PMOS
M22 Y _Y Vdd Vdd PMOS
M23 F4 _CP P007 P007 NMOS
M24 P007 _Y 0 0 NMOS
M25 F4 _CP Vdd Vdd PMOS
M26 F4 _Y Vdd Vdd PMOS
M27 F3 Y P008 P008 NMOS
M28 P008 _CP 0 0 NMOS
M29 F3 _CP Vdd Vdd PMOS
M30 F3 Y Vdd Vdd PMOS
M31 _Q F4 P009 P009 NMOS
M32 P009 Q 0 0 NMOS
M33 _Q F4 Vdd Vdd PMOS
M34 _Q Q Vdd Vdd PMOS
M35 Q F3 P010 P010 NMOS
M36 P010 _Q 0 0 NMOS
M37 Q F3 Vdd Vdd PMOS
M38 Q _Q Vdd Vdd PMOS
M39 _D D Vdd Vdd PMOS
M40 _D D 0 0 NMOS
.ends D_ff

.subckt and Va Vb Vdd Vout
M1 N001 Va Vdd Vdd PMOS
M2 N001 Vb Vdd Vdd PMOS
M3 N001 Va P001 P001 NMOS
M4 P001 Vb 0 0 NMOS
M5 Vout N001 0 0 NMOS
M6 Vout N001 Vdd Vdd PMOS
.ends and

.subckt or Va Vb Vdd Vout
M3 N001 Va 0 0 NMOS
M4 N001 Vb 0 0 NMOS
M5 P001 Va Vdd Vdd PMOS
M6 N001 Vb P001 P001 PMOS
M1 Vout N001 0 0 NMOS
M2 Vout N001 Vdd Vdd PMOS
.ends or

.model NMOS NMOS
.model PMOS PMOS
.tran .1 150
*.backanno
.end
Given below are the Waveforms simulated in NGSPICE of the various outputs

ie A , B , Vout , Vout2
simulating time from t =30s to t=120s
input clock provided during simulation =PULSE(0 5 0 1u 1u 5 10)
Vdd = 5V











Thus it can be seen from the output waveforms that the clock frequency is divided by 3 at Vout and by
1.5 at Vout2 thus it behaves as a MOD 3 counter and MOD 1.5 counter.



Next here is a brief analysis of a clock divide by 5 and 2.5 circuit

Circuit diagram



Y.cir

Clk A B C Vout5 Vout7
L 0 0 1 0 0
H 0 0 1 0 0
L 1 0 0 1 1
H 1 0 0 1 1
L 0 0 0 1 0
H 0 0 0 1 0
L 0 1 0 1 0
H 0 1 0 0 1
L 0 1 1 0 1
H 0 1 1 0 0



Total number of MOS transistors used in this circuit is 176.
Following are the waveforms of the clock(CLK) 0.05 Hz and the corresponding clock divide by 5 op
Vout5 and divide by 2.5 Vout7









It can also be possible to create divider circuits by using configurations of such circuits.
Even normal divide by 2n frequency divider could be used.


Following shows the block circuit diagram of a cicuit that can generate divide by 15 and 7.5
Similarly in this way we can create frequency dividers of 2.25 ,4.5 ,9 ,6.25 ,12.5 ,25 etc
.





















Implementation in Electric

The Electric VLSI Design System free and powerful CAD system for chip design (schematics,
layout, DRC, LVS, ERC, etc.) that runs on any platform (Unix, Linux, Mac, Windows).

The Electric VLSI Design System is an EDA tool written in the early 1980s by Steven M. Rubin.
Electric is used to draw schematics and to do integrated circuit layout. It can also handle hardware
description languages such as VHDL and Verilog. Electric was built as an alternative to traditional
VLSI design systems that did not combine graphics, connectivity, and accurate geometry to implement
connectivity, the Electric design system has an extendible database, built on a network structure.
Electric has been distributed as free software, and is currently part of the GNU project. It is written in
the Java language and released under the GNU GPL.

Electric has a powerful way of doing integrated circuit (IC) layout the system considers integrated
circuits to be composed of nodes and arcs. Nodes are circuit elements such as transistors and contacts.
Arcs connect the nodes. This style of design is quite different from typical IC layout systems, such as
Magic and Cadence, which do IC layout by manipulating polygons on different layers of the wafer.
This powerful design style makes it possible for the designer to run Layout Versus Schematic (LVS)
on layouts which are not yet Design Rule Check (DRC) clean. This is extremely useful during the
design process. It also makes it possible for the design tool to back-annotate wire-lengths from a layout
to a schematic even if the layout is not yet DRC clean. Finally, because layouts are stored internally as
a graph (rather than "paint"), the LVS check is exceptionally fast, often running in under a second on
full-chip designs.

One added advantage of the nodes-and-arcs view of a circuit is that it is possible to add layout
constraints to the arcs. With careful placement, the circuit can be programmed to stay properly
connected when physical changes are made.

Electric incorporates many synthesis and analysis tools:
Design rule checking two built-in checkers and two interfaces to industry tools.
Electrical Rule Checking a Well/Substrate checker and an Antenna rule checker.
Simulation two built-in simulators and interfaces to over a dozen industry tools (Spice, Verilog,
etc.)
Routing five different routers for various special purposes.
Generators a PLA generator, a cell generator, a pad frame generator, and a ROM generator.
Logical Effort a tool for analyzing the Logical Effort of a circuit and resizing gates.
LVS (layout vs. schematic) a tool which compares any two representations of a circuit.
I/O the capability to read and write circuit descriptions in many formats, including CIF, GDS,
EDIF, DXF, and VHDL. It can also interface with other systems, such as EAGLE, Pads, ECAD.

Electric supports many different design technologies, for example:
CMOS
NMOS
Bipolar
Schematics
Artwork

There are geometric data associated with every component and wire so that correct layout can be
represented. Since the database is extendible, additional structures can be stored to describe behavior,
power consumption, design rules, etc.
To represent the geometry of a layout, Electric stores actual coordinates on each node and arc,
expressed in half-mill microns. Organization of this information is done with an R-tree that locates
every node and arc in a balanced geometric space Thus there are two ways to access objects in the
database: by topology and by geometry.
The most interesting aspect of Electric is its powerful facility for programming designs. Besides
providing built-in interpreters for LISP, TCL, and Mathematica, Electric has a few constraint systems
available in the database.

What is MOSIS
MOSIS Scalable CMOS (SCMOS) is a set of logical layers together with their design rules, which
provide a nearly process- and metric-independent interface to many CMOS fabrication processes
available through MOSIS. The designer works in the abstract SCMOS layers and metric unit
("lambda"). He then specifies which process and feature size he wants the design to be fabricated in.
MOSIS maps the SCMOS design onto that process, generating the true logical layers and absolute
dimensions required by the process vendor. The designer can often submit exactly the same design, but
to a different fabrication process or feature size. MOSIS alone handles the new mapping. Vendor rules
may be more appropriate when seeking maximal use of silicon area, more direct control over analog
circuit parameters, or for very large production runs, where the added investment in development time
and loss of design portability is clearly justified. However the advantages of using SCMOS rules may
far outweigh such concerns, and should be considered.

SCMOS design rules
The unit of measurement, lambda, can easily be scaled to different fabrication processes as
semiconductor technology advances. Each design has a technology-code associated with the layout file.
Each technology-code may have one or more associated options added for the purpose of specifying
either (a) special features for the target process or (b) the presence of novel devices in the design.

Standard SCMOS
The standard CMOS technology accessed by MOSIS is a single polysilicon, double metal, bulk CMOS
process with enhancement-mode n-MOSFET and p-MOSFET devices.

Well Type
The Scalable CMOS (SC) rules support both n-well and p-well processes. SCN specifies an n-well
process, SCP specifies a p-well process, and SCE indicates that the designer is willing to utilize a
process of either n-well or p-well.

SCMOS Options
SCMOS options are used to designate projects that use additional layers beyond the standard single-
poly, double metal CMOS. Each option is called out with a designator that is appended to the basic
technology-code.

SCMOS_SUBM and SCMOS_DEEP Rules
The SCMOS layout rules were historically developed for 1.0 to 3.0 micron processes. To take full
advantage of sub-micron processes, the SCMOS rules were revised to create SCMOS_SUBM. The
SCMOS_SUBM rules were revised again at the 0.25 micron regime to better fit the typical deep
submicron processes, creating the SCMOS_DEEP variant.
CIF and GDS Layer Specification
A user design submitted to MOSIS using the SCMOS rules can be in either Calma GDSII format or
Caltech Intermediate Form (CIF version 2.0). The two are completely interchangeable. Note that all
submitted CIF and GDS files have already been scaled before submission, and are always in absolute
metric units -- never in lambda units. GDSII is a binary format, while CIF is a plain ASCII text.

Minimum Density Rule
Many fine-featured processes utilize CMP (Chemical-Mechanical Polishing) to achieve planarity.
Currently, for MOSIS, the ON Semi 0.50 micron and all the 0.35 micron (and smaller) processes are in
this category.

Process-Induced Damage Rules ("Antenna Rules")
General Requirements the "Antenna Rules" deal with process induced gate oxide damage caused when
exposed polysilicon and metal structures, connected to a thin oxide transistor, collect charge from the
processing environment and develop potentials sufficiently large to cause Fowler Nordheim current to
flow through the thin oxide. Failure to consider antenna rules in a design may lead to either reduced
performance in transistors exposed to process induced damage, or may lead to total failure if the
antenna rules are seriously violated.

Support for Arbitrary Via Placement by Process and Technology Codes
Some processes have restrictions on the placement of vias relative to contacts and/or relative to poly
and active edges. Other processes allow arbitrary placement of vias over these lower features. The
placement of vias directly over contacts or other, lower vias is known as "stacked vias."

Half-lambda grid submissions
MOSIS Scalable design rules require that layout is on a 12 lambda grid. MOSIS accepts and process a
design regardless of its actual grid using the standard "recipe" for that design rule set.

PADS Layer
MOSIS has defined an optional PADS layer to help users tell MOSIS which glass openings are to be
bonded and which are not. This optional layer lets you call out only those glass



















Steps in creation of the Layout in Electric:
1. Create a library in Electric with C5 process and fabrication through MOSIS with Scale (lambda) of
300 nm
2. Create a new cell NMOS in schematic and in layout with width of 10 and length 2. Similarly create a
PMOS cell. Add the corresponding Spice model to the transistors
3. Create basic CMOS logic gates cells of Inverter, 2 input AND, OR, NAND, NOR and 3 input NAND
gates using created transistor and use those to create a D-Flipflop. Export the I/O nodes, gnd and vcc,
and Check the DRC, LVS and ERC
4. Create an Icon View of the above gates
5. A tiny chip fabricated in this process via the MOSIS Educational Program (MEP) measures 1.5 mm
by 1.5 mm: 40 pin DIP package
6Create the layout and Schematic of a pad cell, Create its icon view, and utilize it to make a pad frame.
7. Create a new Cell final_chip schematic, dragging the icon view of the corresponding logic gate
according to the frequency divider circuit .connect a bus to the pad frame icon.
8.Export the input clock as pin[6], the output frequency signals CP/3 as pin[11] and CP/1.5 as pin[12]
the power source(vcc) to pin[40] and gnd to pin[40].Add spice code to the circuit, Check DRC
9. Create the Layout View of the final_chip using the same circuit but using the layout view of the
gates. Export the nodes as done above. Check DRC, ERC, LVS
10. Run the Spice code to obtain the output Waveforms in LTSPICE.
11. The GDS (stream) file for this chip can be generated using the menu commands, With the GDS file
it can be sent to MOSIS for Fabrication

Following are Images of the Process:

D Flip flop Layoutjj3D layout of D Flip flop










3D layout of D Flip flop


Divide by 3 layout














CONCLUSION

Thus a cheap reliable circuit has been created using around 200 MOS transistors.
A cheaper way to implement frequency division with 50% duty cycle



REFERENCES

1.Unusual Clock Dividers by Peter Alfke Xilinx Applications
2. EDN ACCESS VHDL code implements 50% duty cycle divider by Brain Boorman,Harris RF
Communications, Rochester, NY
3. CMOS Circuit Design, Layout, and Simulation, Third Edition by Jacob baker
4. Computer Aids for VLSI Design by: Steven M. Rubin
5. http://www.rulabinsky.com/cavd/
6. http://www.mosis.com
7. http://cmosedu.com
8. http://www.staticfreesoft.com/

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