Data Sheet

ADS8864
REF
VINP
VIN
M
4:2
HV MUX
+
+
+ Anti-Aliasing
Filter
Gain Network
High Voltage Level Translation
VCM
High Voltage Multiplexed Input
Reference Driver
REF3240 RC Filter OPA192 RC Filter
Analog Inputs
LED
Photo
Detect
Bridge Sensor
Thermocouple
Current Sensing
Optical Sensor
OPA192
OPA192
OPA192
Gain Network
Gain Network
G
a
i
n

N
e
t
w
o
r
k
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
www.ti.com SBOS620A DECEMBER 2013 REVISED J ANUARY 2014
H ig h V ol ta g e , R a il - to- R a il I n p u t/ O u tp u t,
P r e cis ion O p e r a tion a l A mp l if ie r s , e - tr im S e r ie s
Ch e ck f or S a mp l e s : O P A 1 9 2 , O P A 2 1 9 2 , O P A 4 1 9 2
1 FEA TUR ES A P P LI CA TI O NS
High-Resolution ADC Driver Amplifiers
2 34 56 Low O f f s e t V ol ta g e : 5 V
Multiplexed Data-Acquisition Systems
Low O f f s e t V ol ta g e Dr if t: 0.2 V / C
SAR ADC Reference Buffers
Low Nois e : 5.5 n V / H z a t 1 kH z
Programmable Logic Controllers
Wide Ba n dwidth : 1 0 MH z GBW (G = 1 00)
Test and Measurement Equipment
H ig h S l e w R a te : 2 0 V / s
High-Side and Low-Side Current Sensing
Low Qu ie s ce n t Cu r r e n t: 1 mA p e r A mp l if ie r
High Precision Comparator
R a il - to- R a il I n p u t a n d O u tp u t
Wide S u p p l y: 2 .2 5 V to 1 8 V , +4 .5 V to +36 V DES CR I P TI O N
The OPA192 family
(1)
(OPA192, OPA2192, and EMI / R FI Fil te r e d I n p u ts
OPA4192) is a new generation of 36-V, e-trim
H ig h Common - Mode R e je ction : 1 4 0 dB
operational amplifiers. These devices offer
Low Bia s Cu r r e n t: 5 p A
outstanding dc precision and ac performance,
Dif f e r e n tia l I n p u t V ol ta g e R a n g e to S u p p l y R a il including rail-to-rail input/output, low offset (5 V,
typ), low offset drift (0.2 V/C, typ), and 10MHz
H ig h Ca p a citive Loa d Dr ive Ca p a bil ity: 1 n F
bandwidth. Unique features such as differential input-
I n du s tr y s ta n da r d p a cka g e s :
voltage range to the supply rail, high output current
S in g l e in S O - 8, MS O P - 8 a n d S O T2 3- 5
and high capacitive load drive of up to 1 nF, and high
slew rate make the OPA192 a robust, high-
Du a l in S O - 8 a n d MS O P - 8
performance operational amplifier for high-voltage
Qu a d in S O - 1 4 a n d TS S O P - 1 4
industrial applications. The OPA192 family of op
amps is available in standard packages and is
specified from40C to +125C.
(1) OPA192 SO-8 package is production data. All other devices
are product preview.
O P A 1 9 2 I N A H I GH - V O LTA GE, MULTI P LEXED, DA TA - A CQUI S I TI O N S YS TEM
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2e-trimis a trademark of Texas Instruments.
3TINA-TI is a trademark of Texas Instruments, Inc and DesignSoft, Inc.
4Bluetooth is a registered trademark of Bluetooth SIG, Inc.
5TINA, DesignSoft are trademarks of DesignSoft, Inc.
6All other trademarks are the property of their respective owners.
UNLESS OTHERWISE NOTED this document contains
Copyright 20132014, Texas Instruments Incorporated
PRODUCTION DATA information current as of publication date.
Products conform to specifications per the terms of Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
SBOS620A DECEMBER 2013 REVISED J ANUARY 2014 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range fromsubtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
P A CKA GE A ND O R DER I NG I NFO R MA TI O N
(1 )
(1) For the most current package and ordering information, see the Package Option Addendumat the end of this document, or visit the
device product folder at www.ti.com.
A BS O LUTE MA XI MUM R A TI NGS
(1 )
Over operating free-air temperature range, unless otherwise noted.
V A LUE UNI T
Supply voltage 20 (+40, single supply) V
Common-mode (V) 0.5 to (V+) +0.5 V
Voltage
Signal input
Differential (V+) - (V-) +0.2 V
terminals
Current 10 mA
Output short circuit
(2)
Continuous
Operating temperature 55 to +150 C
Storage temperature 65 to +150 C
J unction temperature +150 C
Electrostatic Human body model (HBM) 4 kV
discharge (ESD)
Charged device model (CDM) 1 kV
ratings
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximumconditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
(2) Short-circuit to ground, one amplifier per package.
ELECTR I CA L CH A R A CTER I S TI CS : V
S
= 4 V to 1 8 V (V
S
= +8 V to +36 V )
At T
A
=+25C, V
CM
=V
OUT
=V
S
/ 2, and R
LOAD
=10 k connected to V
S
/ 2, unless otherwise noted.
O P A 1 9 2
P A R A METER TES T CO NDI TI O NS MI N TYP MA X UNI T
O FFS ET V O LTA GE
5 25 V
V
OS
Input offset voltage
T
A
=40C to +125C 75 V
dV
OS
/dT Input offset voltage drift T
A
=40C to +125C (V) 0.1 V <V
CM
<(V+) 3 V 0.2 0.5 V/C
Power-supply rejection
PSRR T
A
=40C to +125C 0.3 1.0 V/V
ratio
I NP UT BI A S CUR R ENT
5 20 pA
I
B
Input bias current
T
A
=40C to +125C 5 nA
2 20 pA
I
OS
Input offset current
T
A
=40C to +125C 2 nA
NO I S E
(V) 0.1 V <V
CM
<(V+) 3V f =0.1 Hz to 10 Hz 1.30 V
PP
E
n
Input voltage noise
(V+) 1.5 V <V
CM
<(V+) +0.1
f =0.1 Hz to 10 Hz 4 V
PP
V
f =100 Hz 10.5 nV/Hz
(V) 0.1 V <V
CM
<(V+) 3 V
f =1 kHz 5.5 nV/Hz
Input voltage noise
e
n
density
f =100 Hz 32 nV/Hz
(V+) 1.5 V <V
CM
<(V+) +0.1
V
f =1 kHz 12.5 nV/Hz
Input current noise
i
n
f =1kHz 1.5 fA/Hz
density
2 Submit Documentation Feedback Copyright 20132014, Texas Instruments Incorporated
Product Folder Links: OPA192 OPA2192 OPA4192
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
S
= 4 V to 1 8 V (V
S
= +8 V to +36 V ) (con tin u e d)
At T
A
=+25C, V
CM
=V
OUT
=V
S
/ 2, and R
LOAD
S
O P A 1 9 2
I NP UT V O LTA GE
Common-mode voltage (V+) +
V
CM
(V) 0.1 V
range 0.1
(V) 0.1 V <V
CM
<(V+) 3 V 120 140 dB
(V+) 3 V <V
CM
<(V+) - 1.5 V See Typical Characteristics
(V+) 1.5 V <V
CM
<(V+) +0.1
Common-mode 100 120 dB
CMRR V
rejection ratio
(V) 0.1 V <V
CM
<(V+) 3 V 114 126 dB
T
A
=40C to +125C
(V+) 1.5 V <V
CM
<(V+) +0.1
86 100 dB
V
I NP UT I MP EDA NCE
Z
ID
Differential 100 || 1.6 M || pF
Z
IC
Common-mode 1 || 6.4 10
13
|| pF
O P EN- LO O P GA I N
(V) +0.6 V <V
O
<(V+) 0.6 V R
LOAD
=2 k 120 134 dB
(V) +0.6 V <V
O
<(V+) 0.6 V
R
LOAD
=2 k 114 126 dB
T
A
=40C to +125C
A
OL
Open-loop voltage gain
(V) +0.3 V <V
O
<(V+) 0.3 V R
LOAD
=10 k 126 140 dB
(V) +0.3 V <V
O
<(V+) 0.3 V
R
LOAD
=10 k 120 134 dB
T
A
=40C to +125C
FR EQUENCY R ES P O NS E
GBW Unity gain bandwidth 10 MHz
SR Slewrate G =1, 10-V step 20 V/s
V
S
=18 V, G =1, 10-V step 1.4 s
To 0.01%
V
S
=18 V, G =1, 5-V step 0.9 s
t
s
Settling time
V
S
=18 V, G =1, 10-V step 2.1 s
To 0.001%
V
S
=18 V, G =1, 5-V step 1.8 s
t
OR
Overload recovery time V
IN
G =V
S
200 ns
Total harmonic
THD+N G =1, f =1 kHz, V
O
=3.5 V
RMS
0.00008 %
distortion +noise
O UTP UT
No load 5 10 mV
Positive rail R
LOAD
=10 k 95 110 mV
R
LOAD
=2 k 430 500 mV
Voltage output swing
V
O
fromrail
No load 5 10 mV
Negative rail R
LOAD
=10 k 95 110 mV
R
LOAD
=2 k 430 500 mV
I
SC
Short-circuit current 65 mA
C
LOAD
Capacitive load drive See Typical Characteristics pF
Open-loop output
Z
O
f =1 MHz, I
O
=0 A, See Figure 23 375
impedance
Copyright 20132014, Texas Instruments Incorporated Submit Documentation Feedback 3
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
S
= 2 .2 5 V to 4 V (V
S
= +4 .5 V to +8 V )
At T
A
=+25C, V
CM
=V
OUT
=V
S
/ 2, and R
LOAD
S
O P A 1 9 2
O FFS ET V O LTA GE
V
CM
=(V+) 3 V 5 25 V
See Common-Mode Voltage Range
V
CM
=V
S
/ 2 V
section
V
OS
Input offset voltage
V
CM
=(V+) 1.5 V 10 25 V
T
A
=40C to +125C, V
CM
=(V+) 3 V 75 V
(V) 0.1 V <V
CM
<
0.2 0.5 V/C
(V+) 1.5 V
dV
OS
/dT Input offset voltage drift T
A
=40C to +125C
(V+) 1.5 V <V
CM
<(V+)
0.5 3 V/C
+0.1 V
V
CM
=(V-) 0.5 V/V
PSRR Power-supply rejection ratio
T
A
=40C to +125C 1 V/V
I NP UT BI A S CUR R ENT
5 20 pA
I
B
Input bias current
T
A
=40C to +125C 5 nA
2 20 pA
I
OS
Input offset current
T
A
=40C to +125C 2 nA
NO I S E
(V) 0.1 V <V
CM
<(V+) 3 V, f =0.1 Hz to 10 Hz 1.30 V
PP
E
n
Input voltage noise
(V+) 1.5 V <V
CM
<(V+) +0.1 V, f =0.1 Hz to 10 Hz 4 V
PP
f =100 Hz 10.5 nV/Hz
(V) 0.1 V <V
CM
<(V+) 3 V
f =1 kHz 5.5 nV/Hz
e
n
Input voltage noise density
f =100 Hz 32 nV/Hz
(V+) 1.5 V <V
CM
<(V+) +0.1 V
f =1 kHz 12.5 nV/Hz
i
n
Input current noise density f =1kHz 1.5 fA/Hz
I NP UT V O LTA GE
V
CM
Common-mode voltage range (V) 0.1 (V+) +0.1 V
(V) 0.1 V <V
CM
<
94 110 dB
(V+) 3 V
(V+) 3 V <V
CM
<
See Typical Characteristics dB
(V+) 1.5 V
CMRR Common-mode rejection ratio
(V+) 1.5V <V
CM
<(V+)
100 120 dB
+0.1 V
(V) 0.1 V <V
CM
<
T
A
=40C to +125C 90 104 dB
(V+) 3 V
I NP UT I MP EDA NCE
Z
ID
Differential 100 || 1.6 M || pF
Z
IC
Common-mode 1 || 6.4 10
13
|| pF
O P EN- LO O P GA I N
(V) +0.6 V <V
O
<(V+) 0.6 V R
LOAD
=2 k 110 120 dB
(V) +0.6 V <V
O
<(V+) 0.6 V
R
LOAD
=2 k 100 114 dB
T
A
=40 C to +125 C
A
OL
Open-loop voltage gain
(V) +0.3 V <V
O
<(V+) 0.3 V R
LOAD
=10 k 110 126 dB
(V) +0.3 V <V
O
<(V+) 0.3 V
R
LOAD
=10 k 110 120 dB
T
A
=40C to +125C
FR EQUENCY R ES P O NS E
GBW Unity gain bandwidth 10 MHz
SR Slewrate G =1, 10-V step 20 V/s
V
S
=3 V, G =1, 5-V
t
s
Settling time To 0.01% 1 s
step
t
OR
Overload recovery time V
IN
G =V
S
200 ns
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
ELECTR I CA L CH A R A CTER I S TI CS
At T
A
=+25C, V
CM
=V
OUT
=V
S
/ 2, and R
LOAD
S
P O WER S UP P LY
V
S
Specified voltage range +4.5 +36 V
I
O
=0 A 1 1.2 mA
I
Q
Quiescent current per amplifier
T
A
=40C to +125C, I
O
=0 A 1.5 mA
TEMP ER A TUR E
Specified range 40 +125 C
Operating range 55 +150 C
Thermal protection +140 C
TH ER MA L I NFO R MA TI O N: O P A 1 9 2
O P A 1 9 2
TH ER MA L METR I C
(1 )
D (S O ) DBV (S O T2 3) DGK (MS O P ) UNI TS
8 P I NS 5 P I NS 8 P I NS
J A
J unction-to-ambient thermal resistance 115.8 TBD TBD
J C(top)
J unction-to-case(top) thermal resistance 60.1 TBD TBD
J B
J unction-to-board thermal resistance 56.4 TBD TBD
C/W
J T
J unction-to-top characterization parameter 12.8 TBD TBD
J B
J unction-to-board characterization parameter 55.9 TBD TBD
J C(bottom)
J unction-to-case(bottom) thermal resistance N/A TBD TBD
(1) For more information about traditional and newthermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
1
2
3
4
8
7
6
5
NC
(1)
V+
OUT
NC
(1)
NC
(1)
-IN
+IN
V-
1
2
3
4
14
13
12
11
OUT D
-IN D
+IN D
V-
OUT A
-IN A
+IN A
V+
5
6
7
10
9
8
+IN C
-IN C
OUT C
+IN B
-IN B
OUT B
1
2
3
5
4
V+
OUT
IN+
V-
IN-
1
2
3
4
8
7
6
5
V+
OUT B
-IN B
+IN B
OUT A
-IN A
+IN A
V-
1
2
3
5
4
V+
-IN
OUT
V-
+IN
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
P I N CO NFI GUR A TI O NS
DBV P A CKA GE: O P A 1 9 2
D A ND DGK P A CKA GES : O P A 2 1 9 2
S O T2 3- 5
S O - 8 A ND MS O P - 8
(TO P V I EW)
(TO P V I EW)
DCK P A CKA GE: O P A 1 9 2
S C- 70
(TO P V I EW)
D A ND P W P A CKA GES : O P A 4 1 9 2
S O - 1 4 A ND TS S O P - 1 4
(TO P V I EW)
D A ND DGK P A CKA GES : O P A 1 9 2
S O - 8 A ND MS O P - 8
(TO P V I EW)
(1) NC =No internal connection.
NOTE: OPA192 SO-8 package is production data. All other packages are product preview.
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
TYP I CA L CH A R A CTER I S TI CS : Ta bl e of Gr a p h s
Ta bl e 1 . Ch a r a cte r is tic P e r f or ma n ce Me a s u r e me n ts
DES CR I P TI O N FI GUR E
Offset Voltage Production Distribution Figure 1
Offset Voltage Drift Distribution Figure 2
Offset Voltage vs Temperature Figure 3
Offset Voltage vs Common-Mode Voltage Figure 4, Figure 5, Figure 6
Offset Voltage vs Power Supply Figure 7
Open-Loop Gain and Phase vs Frequency Figure 8
Closed-Loop Gain and Phase vs Frequency Figure 9
Input Bias Current vs Common-Mode Voltage Figure 10
Input Bias Current vs Temperature Figure 11
Output Voltage Swing vs Output Current (maximumsupply) Figure 12
CMRR and PSRR vs Frequency Figure 13
CMRR vs Temperature Figure 14
PSRR vs Temperature Figure 15
0.1-Hz to 10-Hz Noise Figure 16
Input Voltage Noise Spectral Density vs Frequency Figure 17
THD+N Ratio vs Frequency Figure 18
THD+N vs Output Amplitude Figure 19
Quiescent Current vs Supply Voltage Figure 20
Quiescent Current vs Temperature Figure 21
Open Loop Gain vs Temperature Figure 22
Open Loop Output Impedance vs Frequency Figure 23
Small Signal Overshoot vs Capacitive Load (100-mV output step) Figure 24, Figure 25
No Phase Reversal Figure 26
Positive Overload Recovery Figure 27
Negative Overload Recovery Figure 28
Small-Signal Step Response (100 mV) Figure 29, Figure 30
Large-Signal Step Response Figure 31
Settling Time Figure 32, Figure 33, Figure 34, Figure 35
Short-Circuit Current vs Temperature Figure 36
MaximumOutput Voltage vs Frequency Figure 37
Propagation Delay Rising Edge Figure 38
Propagation Delay Falling Edge Figure 39
200
150
100
50
0
50
100
150
200
2.5 2.0 1.5 1.0 0.5 0.0 0.5 1.0 1.5 2.0 2.5
V
O
S

(
V
)

V
CM
(V)
C001
5 Typical Units Shown
V
S
= 2.25 V
V
CM
=+2.35V V
CM
= -2.35 V
P-Channel Transition N-Channel
100
75
50
25
0
25
50
75
100
12.5 13.5 14.5 15.5 16.5 17.5 18.5
V
O
S

(
V
)

V
CM
(V)
C001
V
CM
= +18.1V
N-Channel P-Channel
Transition
V
CM
= -18.1V
50
25
0
25
50
20 15 10 5 0 5 10 15 20
V
O
S

(
V
)

V
CM
(V)
C001
V
CM
= -18.1V
100
75
50
25
0
25
50
75
100
75 50 25 0 25 50 75 100 125 150
V
O
S

(
V
)

Temperature (SC)
C001
0
2
4
6
8
10
12
14
16
18
20
22
-
1
0

-
9

-
8

-
7

-
6

-
5

-
4

-
3

-
2

-
1

0

1

2

3

4

5

6

7

8

9

1
0

P
e
r
c
e
n
t
a
g
e

o
f

A
m
p
l
i
f
i
e
r
s

(
%
)

Offset Voltage (V)
C032
Distribution Taken From 4715 Amplifiers
0
5
10
15
20
25
30
35
0
.
0
0

0
.
1
0

0
.
2
0

0
.
3
0

0
.
4
0

0
.
5
0

0
.
6
5

0
.
7
5

0
.
8
5

0
.
9
5

P
e
r
c
e
n
t
a
g
e

o
f

A
m
p
l
i
f
i
e
r
s

(
%
)

Offset Voltage Drift (V/SC)
C013
Distribution Taken From 66 Amplifiers
Temperature = -40SC to 125SC
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
TYP I CA L CH A R A CTER I S TI CS
V
S
=18 V, V
CM
=V
S
/ 2, R
LOAD
S
/ 2, and C
L
=100 pF, unless otherwise noted.
Fig u r e 1 . O FFS ET V O LTA GE P R O DUCTI O N DI S TR I BUTI O N Fig u r e 2 . O FFS ET V O LTA GE DR I FT DI S TR I BUTI O N
Fig u r e 3. O FFS ET V O LTA GE vs TEMP ER A TUR E Fig u r e 4 . O FFS ET V O LTA GE vs CO MMO N- MO DE V O LTA GE
Fig u r e 5. O FFS ET V O LTA GE vs CO MMO N- MO DE V O LTA GE Fig u r e 6. O FFS ET V O LTA GE vs CO MMO N- MO DE V O LTA GE
1000
0
1000
2000
3000
4000
5000
6000
75 50 25 0 25 50 75 100 125 150 175
I
n
p
u
t

B
i
a
s

C
u
r
r
e
n
t

(
p
A
)

Temperature (SC)
C001
I
B+
I
B -
I
os
I
os
(V+) +1
(V+)
(V+) -1
(V+) -2
(V+) -3
(V+) -4
(V+) -5
(V-) +5
(V-) +4
(V-) +3
(V-) +2
(V-) +1
(V-)
(V-) -1

0 10 20 30 40 50 60 70 80
O
u
t
p
u
t

V
o
l
t
a
g
e

(
V
)

Output Current (mA) C018
40SC
25SC
125SC
25SC
40SC
125SC
85SC
85SC
20.0
0.0
20.0
40.0
60.0
1000 10k 100k 1M 10M
G
a
i
n

(
d
B
)

Frequency (Hz)
G = -100
G = +1
G = -1
G = -10
C003
20
15
10
5
0
5
10
15
20
18.0 9.0 0.0 9.0 18.0
I
n
p
u
t

B
i
a
s

C
u
r
r
e
n
t

(
p
A
)

V
CM
(V)
C001
I
B+
I
B-
0
45
90
135
180
20.0
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
1 10 100 1k 10k 100k 1M 10M 100M
P
h
a
s
e

(
S
)
G
a
i
n

(
d
B
)

Frequency (Hz)
C004
Phase
Open-loop Gain
C
LOAD
= 15 pF
50
40
30
20
10
0
10
20
30
40
50
0.0 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0 20.0
V
O
S

(
V
)

V
SUPPLY
(V)
C001
V
S
= 2.25V to ]18V
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
TYP I CA L CH A R A CTER I S TI CS (con tin u e d)
V
S
=18 V, V
CM
=V
S
/ 2, R
LOAD
S
/ 2, and C
L
Fig u r e 7. O FFS ET V O LTA GE vs P O WER S UP P LY Fig u r e 8. O P EN- LO O P GA I N A ND P H A S E vs FR EQUENCY
Fig u r e 9 . CLO S ED- LO O P GA I N A ND P H A S E vs Fig u r e 1 0. I NP UT BI A S CUR R ENT vs CO MMO N- MO DE
FR EQUENCY V O LTA GE
Fig u r e 1 1 . I NP UT BI A S CUR R ENT vs TEMP ER A TUR E Fig u r e 1 2 . O UTP UT V O LTA GE S WI NG vs O UTP UT
CUR R ENT (Ma ximu m S u p p l y)
1
10
100
1000
0.1 1 10 100 1k 10k 100k
V
o
l
t
a
g
e

N
o
i
s
e

D
e
n
s
i
t
y

(
n
V
/
\
H
z
)

Frequency (Hz) C002
V
CM
= V
+
- 100 mV
N-Channel Input
V
CM
= 0 V
P-Channel Input
-140
-120
-100
-80
-60
0.00001
0.0001
0.001
0.01
0.1
10 100 1k 10k
T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

(
d
B
)

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

(
%
)

Frequency (Hz)
G = +1 V/V, RL = 10 k
G = +1 V/V, RL = 2 k
G = -1 V/V, RL = 10 k
G = -1 V/V, RL = 2 k
C007
V
OUT
= 3.5 V
RMS
BW = 80 kHz
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
75 50 25 0 25 50 75 100 125 150
P
o
w
e
r
-
S
u
p
p
l
y

R
e
j
e
c
t
i
o
n

R
a
t
i
o

(
V
/
V
)

Temperature (SC)
C001
4
0
0

n
V
/
d
i
v

Time (1 s/div)
C001
Peak-to-Peak Noise = V
RMS
6.6 = 1.30 V
pp
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
160.0
1 10 100 1k 10k 100k 1M
C
o
m
m
o
n
-
M
o
d
e

R
e
j
e
c
t
i
o
n

R
a
t
i
o

(
d
B
)
,

P
o
w
e
r
-
S
u
p
p
l
y

R
e
j
e
c
t
i
o
n

R
a
t
i
o

(
d
B
)

Frequency (Hz)
+PSRR
CMRR
-PSRR
C012
10
8
6
4
2
0
2
4
6
8
10
75 50 25 0 25 50 75 100 125 150
C
o
m
m
o
n
-
M
o
d
e

R
e
j
e
c
t
i
o
n

R
a
t
i
o

(
V
/
V
)

Temperature (SC)
C001
V
S
= 18 V, V
CM
= 0 V
V
S
= 2.25 V, V
CM
= V
+
- 3V
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
V
S
=18 V, V
CM
=V
S
/ 2, R
LOAD
S
/ 2, and C
L
Fig u r e 1 3. CMR R A ND P S R R vs FR EQUENCY Fig u r e 1 4 . CMR R vs TEMP ER A TUR E
Fig u r e 1 5. P S R R vs TEMP ER A TUR E Fig u r e 1 6. 0.1 - H z to 1 0- H z NO I S E
Fig u r e 1 7. I NP UT V O LTA GE NO I S E S P ECTR A L DENS I TY vs Fig u r e 1 8. TH D+N R A TI O vs FR EQUENCY
FR EQUENCY
10
100
1k
10k
0 1 10 100 1k 10k 100k 1M 10M
O
u
t
p
u
t

I
m
p
e
d
a
n
c
e

(
)

Frequency (Hz)
C016
0
5
10
15
20
25
30
35
40
45
50
10p 100p 1n
O
v
e
r
s
h
o
o
t

(
%
)

Capacitive Load (F)
0
25
50
+
RI = 1 kO
VIN
+ 18 V
18 V
CL
OPA192 +
RF = 1 kO
RISO
G = -1
C013
R
ISO
= 0
R
ISO
= 25
R
ISO
= 50
RI RF
0.8
0.9
1
1.1
1.2
75 50 25 0 25 50 75 100 125 150
I
Q

(
m
A
)

Temperature (SC)
C001
V
s
= 18V

V
s
= 2.25V

3.0
2.0
1.0
0.0
1.0
2.0
3.0
75 50 25 0 25 50 75 100 125 150
A
O
L

(
V
/
V
)

Temperature (SC)
C001
V
s
= 4.5V
V
s
= 36V
R
L
= 10k

0.8
0.9
1.0
1.1
1.2
0 4 8 12 16 20 24 28 32 36
I
Q

(
m
A
)

Supply Voltage (V)
C001
-140
-120
-100
-80
-60
0.00001
0.0001
0.001
0.01
0.1
0.01 0.1 1 10
T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

(
d
B
)

T
o
t
a
l

H
a
r
m
o
n
i
c

D
i
s
t
o
r
t
i
o
n

+

N
o
i
s
e

(
%
)

Output Amplitude (VRMS)
G = +1 V/V, RL = 10 k
G = +1 V/V, RL = 2 k
G = -1 V/V, RL = 10 k
G = -1 V/V, RL = 2 k
C008
f = 1 kHz
BW = 80 kHz
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
V
S
=18 V, V
CM
=V
S
/ 2, R
LOAD
S
/ 2, and C
L
Fig u r e 1 9 . TH D+N vs O UTP UT A MP LI TUDE Fig u r e 2 0. QUI ES CENT CUR R ENT vs S UP P LY V O LTA GE
Fig u r e 2 1 . QUI ES CENT CUR R ENT vs TEMP ER A TUR E Fig u r e 2 2 . O P EN- LO O P GA I N vs TEMP ER A TUR E
Fig u r e 2 3. O P EN- LO O P O UTP UT I MP EDA NCE vs Fig u r e 2 4 . S MA LL- S I GNA L O V ER S H O O T vs CA P A CI TI V E
FR EQUENCY LO A D (1 00- mV O u tp u t S te p )
2
0

m
V
/
d
i
v

Time (100 ns/div)
C015
CL RL
+
VIN
+ 18 V
18 V
OPA192
+
G = +1
C
L
= 10 pF
2
0

m
V
/
d
i
v

Time (120 ns/div)
C006
RL
C
L
= 10 pF
+
RI = 1 kO
VIN
+ 18 V
18 V
CL
OPA192 +
RF = 1 kO
G = -1
RI RF
5

V
/
d
i
v

Time (200 ns/div)
C009
VOUT
VIN
+
RF = 10 kO RI = 1 kO
VOUT
VIN
+ 18 V
18 V
OPA192 +
G = -10
RI RF
5

V
/
d
i
v

Time (200 ns/div)
C010
VOUT
VIN
+
RF = 10 kO RI = 1 kO
VOUT
VIN
+ 18 V
18 V
OPA192 +
G = -10
RI RF
0
5
10
15
20
25
30
35
40
45
50
10p 100p 1n
O
v
e
r
s
h
o
o
t

(
%
)

Capacitive Load (F)
0
25
50
C013
R
ISO
= 0
R
ISO
= 25
R
ISO
= 50
CL RL
+
VIN
+ 18 V
18 V
OPA192
+
RISO
G = +1
5

V
/
d
i
v

Time (200 s/div)
C011
V
IN
V
OUT
37 VPP
Sine Wave
(18.5V)
+
VOUT
+ 18 V
18 V
OPA192
+
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
V
S
=18 V, V
CM
=V
S
/ 2, R
LOAD
S
/ 2, and C
L
Fig u r e 2 5. S MA LL- S I GNA L O V ER S H O O T vs CA P A CI TI V E Fig u r e 2 6. NO P H A S E R EV ER S A L
LO A D (1 00- mV O u tp u t S te p )
Fig u r e 2 7. P O S I TI V E O V ER LO A D R ECO V ER Y Fig u r e 2 8. NEGA TI V E O V ER LO A D R ECO V ER Y
Fig u r e 2 9 . S MA LL- S I GNA L S TEP R ES P O NS E (1 00 mV ) Fig u r e 30. S MA LL- S I GNA L S TEP R ES P O NS E (1 00 mV )
-4
-3
-2
-1
0
1
2
3
4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
O
u
t
p
u
t

D
e
l
t
a

f
r
o
m

F
i
n
a
l

V
a
l
u
e

(
m
V
)

Time (s)
C034
0.01% Settling = 500 V
G = +1
Step Applied at t = 0
0
20
40
60
80
75 50 25 0 25 50 75 100 125 150
I
S
C

(
m
A
)

Temperature (SC)
C001
I
SC
, Source
I
SC
, Sink

-4
-3
-2
-1
0
1
2
3
4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
O
u
t
p
u
t

D
e
l
t
a

f
r
o
m

F
i
n
a
l

V
a
l
u
e

(
m
V
)

Time (s)
C034
0.01% Settling = 500 V
G = +1
-4
-3
-2
-1
0
1
2
3
4
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
O
u
t
p
u
t

D
e
l
t
a

f
r
o
m

F
i
n
a
l

V
a
l
u
e

(
m
V
)

Time (s)
C034
0.01% Settling = 1 mV
G = +1
2

V
/
d
i
v

Time (300 ns/div)
C005
RL
C
L
= 10 pF
+
RI = 1 kO
VIN
+ 18 V
18 V
CL
OPA192 +
RF = 1 kO
G = -1
RI RF
-4
-3
-2
-1
0
1
2
3
4
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
O
u
t
p
u
t

D
e
l
t
a

f
r
o
m

F
i
n
a
l

V
a
l
u
e

(
m
V
)

Time (s)
C034
G = +1
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
V
S
=18 V, V
CM
=V
S
/ 2, R
LOAD
S
/ 2, and C
L
Fig u r e 31 . LA R GE- S I GNA L S TEP R ES P O NS E Fig u r e 32 . S ETTLI NG TI ME (1 0- V P os itive S te p )
Fig u r e 33. S ETTLI NG TI ME (5- V P os itive S te p ) Fig u r e 34 . S ETTLI NG TI ME (1 0- V Ne g a tive S te p )
Fig u r e 35. S ETTLI NG TI ME (5- V Ne g a tive S te p ) Fig u r e 36. S H O R T- CI R CUI T CUR R ENT vs TEMP ER A TUR E
O
u
t
p
u
t

V
o
l
t
a
g
e

(
1

V
/
d
i
v
)

Time (200 ns/div)
C026
V
OUT
Voltage
Overdrive = 100 mV
t
pLH
= 1.1 s
0
5
10
15
20
25
30
10k 100k 1M 10M
O
u
t
p
u
t

V
o
l
t
a
g
e

(
V
P
P
)

Frequency (Hz)
C033
V
S
= 2.25 V
V
S
= 5 V
V
S
= 15 V
Maximum output voltage without
slew-rate induced distortion.
O
u
t
p
u
t

V
o
l
t
a
g
e

(
5

V
/
d
i
v
)

Time (200 ns/div)
C025
V
OUT
Voltage
Overdrive = 100 mV
t
pLH
= 0.97 s
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
V
S
=18 V, V
CM
=V
S
/ 2, R
LOAD
S
/ 2, and C
L
Fig u r e 37. MA XI MUM O UTP UT V O LTA GE vs FR EQUENCY Fig u r e 38. P R O P A GA TI O N DELA Y R I S I NG EDGE
Fig u r e 39 . P R O P A GA TI O N DELA Y FA LLI NG EDGE
36-V
Differential
Front End
Slew
Boost
High
Capacitive Load
Compensation
e-Trim
Package Level Trim
IN+
IN
VOUT
OPA192
NCH Input
Stage
PCH Input
Stage
Output
Stage
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
DETA I LED DES CR I P TI O N
O V ER V I EW
The OPA192 family of operational amplifiers use e-trim, a method of package-level trim for offset and offset
temperature drift implemented during the final steps of manufacturing after the plastic molding process. This
method minimizes the influence of inherent input transistor mismatch, as well as errors induced during package
molding. The trimcommunication occurs on the output pin of the standard pinout, and after the trimpoints are
set, further communication to the trimstructure is permanently disabled. Figure 40 shows the simplified diagram
of OPA192 with e-trim.
Fig u r e 4 0. S imp l if ie d S ch e ma tic
Unlike previous e-trimop amps, the OPA192 uses a patented two-temperature trimarchitecture to achieve a very
low offset voltage of 25 V (max) and low voltage offset drift of 0.5 V/C (max) over the full specified
temperature range. This level of precision performance at wide supply voltages makes these amplifiers useful for
high-impedance industrial sensors, filters, and high-voltage data acquisition.
As with all amplifiers, applications with noisy or high-impedance power supplies require decoupling capacitors
close to the device pins. In most cases, 0.1-F capacitors are adequate.
O P ER A TI NG V O LTA GE
The OPA192 is specified for operation from 4.5 V to 36 V (2.25 V to 18 V). Many specifications apply from
40C to +125C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics.
CA UTI O N
Supply voltages larger than 40 V can permanently damage the device; see the
Absolute MaximumRatings.
In addition, key parameters are assured over the specified temperature of T
A
=40C to +125C. Parameters
that vary significantly with operating voltage or temperature are shown in the Typical Characteristics.
0.0
20.0
40.0
60.0
80.0
100.0
120.0
140.0
160.0
10M 100M 1G 10G
E
M
I
R
R

I
N
+

(
d
B
)

Frequency (Hz) C017
P
RF
= -10 dBm
V
SUPPLY
= 18 V
V
CM
= 0 V
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
EMI R EJECTI O N
The OPA192 uses integrated electromagnetic interference (EMI) filtering to reduce the effects of EMI from
sources such as wireless communications and densely-populated boards with a mix of analog signal chain and
digital components. EMI immunity can be improved with circuit design techniques; the OPA192 benefits from
these design improvements. Texas Instruments has developed the ability to accurately measure and quantify the
immunity of an operational amplifier over a broad frequency spectrum extending from 10 MHz to 6 GHz.
Figure 41 shows the results of this testing on the OPA192. Table 2 shows the EMIRR IN+values for the OPA192
at particular frequencies commonly encountered in real-world applications. Applications listed in Table 2 may be
centered on or operated near the particular frequency shown. Detailed information can also be found in the
Application Report SBOA128, EMI Rejection Ratio of Operational Amplifiers, available for download from
www.ti.com.
Fig u r e 4 1 . EMI R R Te s tin g
Ta bl e 2 . O P A 1 9 2 EMI R R I N+ f or Fr e qu e n cie s of I n te r e s t
FR EQUENCY A P P LI CA TI O N O R A LLO CA TI O N EMI R R I N+
Mobile radio, mobile satellite, space operation, weather, radar, ultra-high frequency
400 MHz 44.1 dB
(UHF) applications
Global systemfor mobile communications (GSM) applications, radio
900 MHz communication, navigation, GPS (to 1.6 GHz), GSM, aeronautical mobile, UHF 52.8 dB
applications
GSM applications, mobile personal communications, broadband, satellite, L-band
1.8 GHz 61.0 dB
(1 GHz to 2 GHz)
802.11b, 802.11g, 802.11n, Bluetooth
, mobile personal communications,

2.4 GHz industrial, scientific and medical (ISM) radio band, amateur radio and satellite, S- 69.5 dB
band (2 GHz to 4 GHz)
3.6 GHz Radiolocation, aero communication and navigation, satellite, mobile, S-band 88.7 dB
802.11a, 802.11n, aero communication and navigation, mobile communication,
5.0 GHz 105.5 dB
space and satellite operation, C-band (4 GHz to 8 GHz)
Power-Supply
ESD Cell
100
100
VSS
VDD
IN-
IN+
+
+
+
R1
RS
RF
TVS
TVS
RL
VIN
+VS
-VS
OPA192
ID
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
ELECTR I CA L O V ER S TR ES S
Designers often ask questions about the capability of an operational amplifier to withstand electrical overstress
(EOS). These questions tend to focus on the device inputs, but may involve the supply voltage pins or even the
output pin. Each of these different pin functions have electrical stress limits determined by the voltage breakdown
characteristics of the particular semiconductor fabrication process and specific circuits connected to the pin.
Additionally, internal electrostatic discharge (ESD) protection is built into these circuits to protect them from
accidental ESD events both before and during product assembly.
Having a good understanding of this basic ESD circuitry and its relevance to an electrical overstress event is
helpful. See Figure 42 for an illustration of the ESD circuits contained in the OPAx192 (indicated by the dashed
line area). The ESD protection circuitry involves several current-steering diodes connected from the input and
output pins and routed back to the internal power-supply lines, where the diodes meet at an absorption device or
the power-supply ESD cell, internal to the operational amplifier. This protection circuitry is intended to remain
inactive during normal circuit operation.
Fig u r e 4 2 . Equ iva l e n t I n te r n a l ES D Cir cu itr y R e l a tive to a Typ ica l Cir cu it A p p l ica tion
An ESD event is very short in duration and very high voltage (for example, 1 kV, 100 ns), whereas an EOS event
is long duration and lower voltage (for example, 50 V, 100 ms). The ESD diodes are designed for out-of-circuit
ESD protection (that is, during assembly, test, and storage of the device before it is soldered to the PCB). During
an ESD event, the ESD signal is passed through the ESD steering diodes to an absorption circuit (labeled ESD
power-supply circuit). The ESD absorption circuit clamps the supplies to a safe level.
While this behavior is necessary for out-of-circuit protection, it causes excessive current and damage if activated
in-circuit. A transient voltage suppressors (TVS) can be used to prevent against damage caused by turning on
the ESD absorption circuit during an in-circuit ESD event. Using the appropriate current limiting resistors and
TVS diodes allows for the use of device ESD diodes to protect against EOS events.
-15.0 -14.0 ; 11.0 12.0 13.0 14.0 15.0
Common Mode Voltage
I
n
p
u
t

O
f
f
s
e
t

V
o
l
t
a
g
e

(
u
V
)
200
100
0
-100
-200
-300
Input Offset Voltage vs Vcm
without e-Trim Input
Transition
Region
P-Channel
Region
N-Channel
Region
-15.0 -14.0 ; 11.0 12.0 13.0 14.0 15.0
Common Mode Voltage
I
n
p
u
t

O
f
f
s
e
t

V
o
l
t
a
g
e

(
u
V
)
200
100
0
-100
-200
-300
Transition
Region
P-Channel
Region
N-Channel
Region
OPA192 e-Trim
Input Offset Voltage vs Vcm
NCH3
PCH2
PCH1
IS1
NCH4
-Vsupply
+Vsupply
VIN+
VIN-
FUSE BANK
VOS TRIM VOS DRIFT TRIM
e-Trim
TM
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
CO MMO N- MO DE V O LTA GE R A NGE
The OPA192 is a 36-V, true rail-to-rail input operational amplifier with an input common-mode range that extends
100 mV beyond either supply rail. This is achieved with paralleled complementary N-channel and P-channel
differential input pairs, as shown in Figure 43. The N-channel pair is active for input voltages close to the positive
rail, typically (V+) 3 V to 100 mV above the positive supply. The P-channel pair is active for inputs from100 mV
belowthe negative supply to approximately (V+) 1.5 V. There is a small transition region, typically (V+) 3 V to
(V+) 1.5 V) in which both input pairs are on. This transition region can vary modestly with process variation,
and within this region PSRR, CMRR, offset voltage, offset drift, noise and THD performance may be degraded
compared to operation outside this region.
Fig u r e 4 3. R a il - to- R a il I n p u t S ta g e
To achieve the best performance for two-stage rail-to-rail input amplifiers, avoid the transition region when
possible. The OPA192 uses a precision trim for both the N-channel and P-channel regions. This technique
enables significantly lower levels of offset than previous-generation devices, causing variance in the transition
region of the input stages to appear exaggerated relative to offset over the full common-mode range, as shown in
Figure 44.
Fig u r e 4 4 . Common - Mode Tr a n s ition vs S ta n da r d R a il - to- R a il A mp l if ie r s
100
80
60
40
20
0
20
40
60
80
100
0 5 10 15 20 25 30 35 40 45 50 55 60
O
u
t
p
u
t

D
e
l
t
a

F
r
o
m

F
i
n
a
l

V
a
l
u
e

(
m
V
)

Time (s)
C040
Standard Input Diode Structure
Extends Settling Time
OPA192 Input Structure
Offers Fast Settling
Input Low Pass Filter
R
on_mux
C
S
C
S
C
D
S
n
S
n+
1
D
Simplified Mux Model
R
FILT
R
FILT
C
FILT
C
FILT
V
n
=+10V
V
n+1
=-
10V
+10V
-10V
Buffer Amplifier
1
2
I
diode_transient
R
on_mux
+10V ~-9.3V
1
Vin+
Vin-
~0.7V
Vout
2
-10V
VIN+
VIN
OPA192 36 V
~0.7 V
VOUT
V+
V
VOUT
Conventional Input Protection
Limits Differential Input Range
OPA192 Provides Full 36-V
Differential Input Range
VIN+
VIN
V+
V
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
I NP UT P R O TECTI O N CI R CUI TR Y
The OPA192 uses a unique input architecture to eliminate the need for input protection diodes but still provides
robust input protection under transient conditions. Conventional input diode protection schemes shown in
Figure 45 can be activated by fast transient step responses and can introduce signal distortion and settling time
delays due to alternate current paths, as shown in Figure 46. For low-gain circuits, these fast-ramping input
signals forward-bias back-to-back diodes causing an increase in input current and resulting in extended settling
time, as seen in Figure 47.
Fig u r e 4 5. O P A 1 9 2 I n p u t P r ote ction Doe s Not Limit Dif f e r e n tia l I n p u t Ca p a bil ity
Fig u r e 4 6. Ba ck- to- Ba ck Diode s Cr e a te S e ttl in g I s s u e s
Fig u r e 4 7. O P A 1 9 2 P r ote ction Cir cu it Ma in ta in s Fa s t- S e ttl in g Tr a n s ie n t R e s p on s e
V
o
u
t
140 C
3V
0V
T
e
m
p
e
r
a
t
u
r
e
Normal
Operation
Output
High-Z
150 C
+30V
R
L

1
0
0

-
+
Vin
3V dc
+
3V
-
Iout = 30mA
OPA192
Ta= 65C
Pd = 0.81W
ja = 116 C/W
Tj = 116 C/W x 0.81W + 65 C
Tj = 159 C (expected)
+
-
5

V
/
d
i
v

Time (200 s/div)
C011
V
IN
V
OUT
37 VPP
Sine Wave
(18.5V)
+
VOUT
+ 18 V
18 V
OPA192
+
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
The OPA192 family of operational amplifiers provides a true high-impedance differential input capability for high-
voltage applications. This patented input protection architecture does not introduce additional signal distortion or
delayed settling time, making it an optimal op amp for multichannel, high-switched, input applications. The
OPA192 can tolerate a maximum differential swing (voltage between inverting and noninverting terminal of the
op amp) of up to 36 V, making it suitable for use as a comparator or in applications with fast-ramping input
signals, such as multiplexed data-acquisition systems, as shown in Figure 55.
P H A S E R EV ER S A L P R O TECTI O N
The OPA192 family has internal phase-reversal protection. Many op amps exhibit a phase reversal when the
input is driven beyond its linear common-mode range. This condition is most often encountered in noninverting
circuits when the input is driven beyond the specified common-mode voltage range, causing the output to
reverse into the opposite rail. The OPA192 is a rail-to-rail input op amp; therefore, the common-mode range can
extend up to the rails. Input signals beyond the rails do not cause phase reversal; instead, the output limits into
the appropriate rail. This performance is shown in Figure 48.
Fig u r e 4 8. No P h a s e R e ve r s a l
TH ER MA L P R O TECTI O N
The internal power dissipation of any amplifier causes its internal (junction) temperature to rise. This
phenomenon is called self heating. The absolute maximum junction temperature of the OPA192 is +150C.
Exceeding this temperature causes damage to the device. The OPA192 has a thermal protection feature that
prevents damage from self heating. The protection works by monitoring the temperature of the device and
turning off the op amp output drive for temperatures above +140C. Figure 49 shows an application example for
the OPA192 that will have significant self heating (+159C) because of its power dissipation (0.81 W). Thermal
calculations indicate that for an ambient temperature of +65C the device junction temperature should reach
+187C. The actual device, however, turns off the output drive to maintain a safe junction temperature. Figure 49
depicts how the circuit behaves during thermal protection. During normal operation, the device acts as a buffer
so the output is 3 V. When self heating causes the device junction temperature to increase above +140C, the
thermal protection forces the output to a high-impedance state and the output is pulled to ground through resistor
RL.
Fig u r e 4 9 . Th e r ma l P r ote ction
0
5
10
15
20
25
30
35
40
45
50
10p 100p 1n
O
v
e
r
s
h
o
o
t

(
%
)

Capacitive Load (F)
0
25
50
+
RI = 1 kO
VIN
+ 18 V
18 V
CL
OPA192 +
RF = 1 kO
RISO
G = -1
C013
R
ISO
= 0
R
ISO
= 25
R
ISO
= 50
RI RF
0
5
10
15
20
25
30
35
40
45
50
10p 100p 1n
O
v
e
r
s
h
o
o
t

(
%
)

Capacitive Load (F)
0
25
50
C013
R
ISO
= 0
R
ISO
= 25
R
ISO
= 50
CL RL
+
VIN
+ 18 V
18 V
OPA192
+
RISO
G = +1
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
O V ER LO A D R ECO V ER Y
Overload recovery is defined as the time it takes for the op amp output to recover from a saturated state to a
linear state. The output devices of the op amp enter a saturation region when the output voltage exceeds the
rated operating voltage, either due to the high input voltage or the high gain. After the device enters the
saturation region, the charge carriers in the output devices require time to return back to the linear state. After
the charge carriers return back to the linear state, the device begins to slewat the specified slewrate. Thus, the
propagation delay in case of an overload condition is the sumof the overload recovery time and the slew time.
The overload recovery time for the OPAx192 is approximately 200 ns.
GENER A L LA YO UT GUI DELI NES
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
Connect low-ESR, 0.1-F ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+to ground is applicable to single-
supply applications.
In order to reduce parasitic coupling, run the input traces as far away fromthe supply lines as possible.
A ground plane helps distribute heat and reduces EMI noise pickup.
Place the external components as close to the device as possible. This configuration prevents parasitic
errors (such as the Seebeck effect) fromoccurring.
CA P A CI TI V E LO A D A ND S TA BI LI TY
The OPA192 features a patented output stage capable of driving large capacitive loads, and in a unity-gain
configuration, can directly drive up to 1 nF of pure capacitive load. Increasing the gain enhances the ability of the
amplifier to drive greater capacitive loads, as shown in Figure 50 and Figure 51. The particular op amp circuit
configuration, layout, gain, and output loading are some of the factors to consider when establishing whether an
amplifier will be stable in operation.
Fig u r e 50. S ma l l - S ig n a l O ve r s h oot vs Ca p a citive Fig u r e 51 . S ma l l - S ig n a l O ve r s h oot vs Ca p a citive
Loa d (1 00- mV ou tp u t s te p ) Loa d (1 00- mV ou tp u t s te p )
+
C
load +
V
in
V
out
+V
s
R
iso
-V
s
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
For additional drive capability in unity-gain configurations, capacitive load drive can be improved by inserting a
small (10 to 20 ) resistor, R
ISO
, in series with the output, as shown in Figure 52. This resistor significantly
reduces ringing while maintaining dc performance for purely capacitive loads. However, if there is a resistive load
in parallel with the capacitive load, a voltage divider is created, introducing a gain error at the output and slightly
reducing the output swing. The error introduced is proportional to the ratio R
ISO
/ R
L
, and is generally negligible at
lowoutput levels. A high capacitive load drive makes the OPA192 well suited for applications such as reference
buffers, MOSFET gate drives, and cable-shield drives. The circuit shown in Figure 52 uses an isolation resistor
(R
ISO
) to stabilize the output of an op amp. R
ISO
modifies the open-loop gain of the systemfor increased phase
margin, and results using the OPA192 are summarized in Table 3. For additional information on techniques to
optimize and design using this circuit, TI Precision Design TIDU032 details complete design goals, simulation,
and test results.
Fig u r e 52 . Exte n din g Ca p a citive Loa d Dr ive with th e O P A 1 9 2
Ta bl e 3. O P A 1 9 2 Ca p a citive Loa d Dr ive S ol u tion Us in g I s ol a tion R e s is tor Comp a r is on of Ca l cu l a te d a n d
Me a s u r e d R e s u l ts
Ca p a citive Loa d 1 00 p F 1 000 p F 0.01 F 0.1 F 1 F
P h a s e Ma r g in 45 60 45 60 45 60 45 60 45 60
R
I S O
() 47.0 360.0 24.0 100.0 20.0 51.0 6.2 15.8 2.0 4.7
Me a s u r e d
23.2 8.6 10.4 22.5 9.0 22.1 8.7 23.1 8.6 21.0 8.6
O ve r s h oot (%)
Ca l cu l a te d P M 45.1 58.1 45.8 59.7 46.1 60.1 45.2 60.2 47.2 60.2
For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test
results, refer to TI Precision Design TIDU032 - Capacitive Load Drive Solution using an Isolation Resistor
VCC
VEE
R2
1.6 M
VOUT
V+
+
VIN
RL
10 k
R1
1.69 k
C1
470 nF
Op Amp Gain Stage Slew Rate Limiter
OPA192
VCC
VEE
V+
OPA192
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
A P P LI CA TI O N I NFO R MA TI O N
TI P R ECI S I O N DES I GNS
The OPA192 is featured in several TI Precision Designs, available online at
http://www.ti.com/ww/en/analog/precision-designs/. TI Precision Designs are analog solutions created by TIs
precision analog applications experts and offer the theory of operation, component selection, simulation,
complete PCB schematic and layout, bill of materials, and measured performance of many useful circuits.
S LEW R A TE LI MI T FO R I NP UT P R O TECTI O N
In control systems for valves or motors, abrupt changes in voltages or currents can cause mechanical damages.
By controlling the slew rate of the command voltages into the drive circuits, the load voltages can ramp up and
down at a safe rate. For symmetrical slew-rate applications (positive slew rate equals negative slew rate) one
additional op amp provides slew-rate control for a given analog gain stage. The unique input protection and high
output current and slew rate of the OPA192 make it an optimal amplifier to achieve slew rate control for both
dual- and single-supply systems. Figure 53 shows the OPA192 in a slew-rate limit design.
Fig u r e 53. S l e w R a te Limite r Us e s O n e O p A mp
results, refer to TI Precision Design TIDU026 - Slew Rate Limiter Uses One Op Amp
RF
1 k
CL
10 F
RISO
37.4
VREF
2.5 V
RFx
10 k
CF
39 nF
V+
OPA192 VOUT
VCC

O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
P R ECI S I O N R EFER ENCE BUFFER
The OPA192 features high output current drive capability and low input offset voltage, making it an excellent
reference buffer to provide an accurate buffered output with ample drive current for transients. For the 10-F
ceramic capacitor shown in Figure 54, R
ISO
, a 37.4- isolation resistor, provides separation of two feedback
paths for optimal stability. Feedback path number one is through R
F
and is directly at the output, V
OUT
. Feedback
path number two is through R
Fx
and C
F
and is connected at the output of the op amp. The optimized stability
components shown for the 10-F load give a closed-loop signal bandwidth at V
OUT
of 4 kHz, while still providing
a loop gain phase margin of 89. Any other load capacitances require recalculation of the stability components:
R
F
, R
Fx
, C
F
, and R
ISO
.
Fig u r e 54 . P r e cis ion R e f e r e n ce Bu f f e r
SAR
ADC
REFP
VINP
VINM
1
4:2
Mux
+
+
+ Antialiasing
Filter
Gain
Network
Gain
Network
G
a
i
n

N
e
t
w
o
r
k
High-Voltage Level Translation
V
C
M
High-Voltage Multiplexed Input
Reference Driver
2 4
Voltage
Reference
RC Filter Buffer RC Filter
16 Bits
400 kSPS
Delay
Digital Counter For Multiplexer
CONV
5
3
Very Low Output Impedance
Input-Filter Bandwidth
High-Impedance Inputs
No Differential Input Clamps
Fast Settling-Time Requirements
Attenuate High-Voltage Input Signal
Fast-Settling Time Requirements
Stability of the Input Driver
Attenuate ADC Kickback Noise
VREF Output: Value and Accuracy
Low Temp and Long-Term Drift
Fast logic transition
20-V,
10-kHz
Sine Wave
20-V,
10-kHz
Sine Wave
+
+
+
+
Shmidtt
Trigger
Counter
REF3240
Voltage
Divider
OPA350
VCM Generation Circuit
n
n
CH0+
CH0-
CH3+
CH3-
OPA192
OPA192
OPA192
OPA192
OPA140
OPA192
OPA192
Gain
Network
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
1 6- BI T P R ECI S I O N MULTI P LEXED DA TA - A CQUI S I TI O N S YS TEM
Figure 55 shows a 16-bit, differential, 4-channel, multiplexed data-acquisition system. This example is typical in
industrial applications that require low distortion and a high-voltage differential input. The circuit uses the
ADS8864, a 16-bit, 400-kSPS successive-approximation-resistor (SAR) analog-to-digital converter (ADC), along
with a precision, high-voltage, signal-conditioning front end, and a 4-channel differential multiplexer (mux). This
TI Precision Design details the process for optimizing the precision, high-voltage, front-end drive circuit using the
OPA192 and OPA140 to achieve excellent dynamic performance and linearity with the ADS8864.
Fig u r e 55. O P A 1 9 2 in 1 6- Bit, 4 00- kS P S , 4 - Ch a n n e l , Mu l tip l e xe d Da ta A cqu is ition S ys te m
f or H ig h - V ol ta g e I n p u ts with Lowe s t Dis tor tion
results, refer to TI Precision Design TIDU181 - 16-bit, 400-kSPS, 4-Channel, Multiplexed Data Acquisition
System for High Voltage Inputs with Lowest Distortion
TI NA - TI (Fr e e Down l oa d S of twa r e )
TINA is a simple, powerful, and easy-to-use circuit simulation programbased on a SPICE engine. TINA-TI is a
free, fully-functional version of the TINA software, preloaded with a library of macro models in addition to a range
of both passive and active models. TINA-TI provides all the conventional dc, transient, and frequency domain
analysis of SPICE, as well as additional design capabilities.
Available as a free download from the Analog eLab Design Center, TINA-TI offers extensive post-processing
capability that allows users to format results in a variety of ways. Virtual instruments offer the ability to select
input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic quick-start tool.
NO TE
These files require that either the TINA software (fromDesignSoft) or TINA-TI software
be installed. Download the free TINA-TI software fromthe TINA-TI folder.
O P A 1 9 2
O P A 2 1 9 2
O P A 4 1 9 2
R EV I S I O N H I S TO R Y
NOTE: Page numbers for previous revisions may differ frompage numbers in the current version.
Ch a n g e s f r om O r ig in a l (De ce mbe r 2 01 3) to R e vis ion A P a g e
Changed first paragraph of 16-BIT PRECISION MULTIPLEXED DATA-ACQUISITION SYSTEM section ....................... 25
Changed Figure 55 and title ............................................................................................................................................... 25
Changed TIDU181 reference design title ........................................................................................................................... 25
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jan-2014
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing
Pins Package
Qty
Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (C) Device Marking
(4/5)
Samples
OPA192ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA192
OPA192IDBVR PREVIEW SOT-23 DBV 5 3000 TBD Call TI Call TI -40 to 125
OPA192IDBVT PREVIEW SOT-23 DBV 5 250 TBD Call TI Call TI -40 to 125
OPA192IDGKR PREVIEW VSSOP DGK 8 2500 TBD Call TI Call TI -40 to 125
OPA192IDGKT PREVIEW VSSOP DGK 8 80 TBD Call TI Call TI -40 to 125
OPA192IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br)
CU NIPDAU Level-2-260C-1 YEAR -40 to 125 OPA192

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
PACKAGE OPTION ADDENDUM
Addendum-Page 2

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
(mm)
Pin1
Quadrant
OPA192IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA192IDR SOIC D 8 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
Pack Materials-Page 2
IMPORTANT NOTICE
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