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Name Description Status Issue Test

apm_hdlc_init
_ get all HDLC configuration related
parameters from insmod comand.

_ pass these parameters to
apm_hdlc_run function.
apm_hdlc_run
_ call Keelback's low-level intializing
functions with parameters from
apm_hdlc_init function.

_ allocation memory for hdlc net
device.

_ request interrupt for hdlc net device.

_ initializing each members of
apm_hdlc struct.

_ register hdlc net device with Linux
Kernel.
apm_hdlc_exit _ unregiste hdlc net device
apm_hdlc_ioctl
_ issue Keelback's device-specific
commands.
apm_hdlc_xmit
_ called by generic HDLC layer to send
frame
apm_hdlc_attach
_ called by generic HDLC layer when
protocol selected (PPP, frame relay, ..)
set endconding and frame check
sequence (FCS) options.
apm_hdlc_intr
_ Keelback's HDLC interrupr handler.

_ the function is called eachtime there
is an interrupt on the port, it will check if
it is a Tx or Rx interrup and call the
respected interrupt handler.
apm_hdlc_set_carrier
_ Change Link State.

Test Comment Code
apm_hdlc_open
_ called by generic network driver

_ call hdlc_open to open the HDLC
device

_ call apm_hdlc_set_carrier to anounce
link state change to Linux Kernel.

_ call netif_start_queue to start HDLC
interface's transmit queue.
apm_hdlc_close
_ reset HDLC channel.

_ disable HDLC related interrupts.

_ call netif_stop_queue to mark the
device as being unable to transmit any
more packets.

_ call hdlc_close to announce HDLC
device is being closed.
Keelback's low-level initializing functions
TDM Interface
Config
Choosing the order of transmission on
the TDM interface by setting the
BitOrder bit in Configuration Register 2.
By default, data on the TDM interface
is transmitted least significant bit first.
Time Slot Assigner
Config
setting or clearing the TSEnb bit in the
Time Slot Assigner Table for each 128
timeslots.
Ready to Send
Config
RTSEnb = 0: the hdlc_rts_n signal is
always asserted
RTSEnb = 1: the hdlc_rts_n signal is
asserted during the frame transmission
and deassered between frames.
TTdmEdge: indicate which hdlc_txclk
clock edge the hdlc_rts_n signal is
asserted and deasserted.
Keelback's low-level initializing functions
Clear to Send
Config
Clear to Send operation is controlled by
the CTSEnb, and CTSMode bits in
Configuration Register 1.
++ When CTSEnb = 0, the HDLC-AHB
core transmit frames regardless of the
state of hdlc_cts_i.
++ When CTSEnb = 1, the value
assigned to hdlc_cts_i depends on the
value of CTSMode.
++ When CTSMode = 0, hdlc_cts_i is
set to the signal hdlc_cts_n.
++ When CTSMode = 1, hdlc_cts_i is
generated internally.
+ The CTSLMode bit in Configuration
Register 1 controls the operation when
hdlc_cts_i is deasserted.
++ The HDLC-AHB Core waits for
hdlc_cts_i to be asserted to transmit a
frame.
++ If CTSLMode = 0, the transmission
continues even if the hdlc_cts_i is
deasserted.
++ If CTSLMode = 1, the transmisson
stops when hdlc_cts_i is sampled high
and the CTSLost interrupt is asserted.
Carrier Detect
Receiver Config
Its operation is controlled by the
CDEnb, and CDMode bits in
Configuration Register 1.
+ When CDEnb = 0, the HDLC-AHB
Core receives frames regardless of the
state of hdlc_cd_i.
+ When CDEnb = 1, the value
assigned to hdlc_cd_i depends on the
value of CDMode.
+ When CDMode = 0, hdlc_cd_i is set
to the signal hdlc_cd_n.
+ When CDMode = 1, hdlc_cd_i
internally generated.
+ It is asserted when hdlc_cts_i = 0
and hdlc_txd = 1.
+
The HDLC-AHB Core starts receiving
data as soon as hdlc_cd_i is sampled
low on the edge of the hdlc_rxclk
indicated by the RTdmEdge bit in
Configuration Register 1.
+ The CDLMode bit in Configuration
Register
1 controls the operation when
hdlc_cd_i is deasserted. The HDLC-
AHB
Core receives frames while hdlc_cd_i
is asserted.
+ If CDLMode = 0, once a frame
reception starts, it continues even if
hdlc_cd_i is deasserted.
+
If CDLMode = 1, the frame reception is
terminated when hdlc_cd_i is
sampled high and the CDLost bit is set
in the descriptor of the received
frame.
HDLC Receive
Section
_The bit destuffing mode is selected by
setting the CfgRxStuffMode bit to 0

_The byte destuffing mode is selected
by setting the CfgRxStuffMode bit to 1

_ CRC checking is enabled by
asserting the CfgRxCRCEnb
configuration bit. The CRC circuit
(CRC16 or CRC32) is selected via the
CfgRxCRCLength bit.
HDLC Transmit
Section
_ The bit stuffing mode is selected by
setting the CfgTxStuffMode bit to 0.

_ The byte stuffing mode is selected by
setting the CfgTxStuffMode bit to 1.

_ CRC insertion is enabled by
asserting the TxConfig.CRCEnb
configuration bit. The CRC circuit
(CRC16 or CRC32) is seleted via the
TxConfig.CRCLength bit. NOTE: when
CRC insertion is disabled (TxConfig.
CRCEnb = 0), the CRC is provided with
the packet over the FIFO interface.
Address
Comparison
Config
_ The least significant byte of the
HDLC Receive Header Data Registers
is programmed with the first byte of the
expected address (i.e., the byte
following the opening flag). The most
significant byte of the HDLC Receive
Header Data Registers is programmed
with the second byte of the expected
address.
Frame
Retransmission
Config enable by setting RetransEnb bit
Transmit Frame
Operation
_ Host CPU divides frame into
segments with each segment written
into a separate buffer in system RAM.

_ The Host CPU then writes a
descriptor for each segment into the Tx
Dsc FIFO. The descriptor consists of
the address of the buffer in system
RAM, the segment length, and
indications that the segment is the
frame's first or last segment.
Receive Frame
Operation
_ Prior to enabling the receiver, the
host CPU must supply free buffer
pointers by writing them in the Receive
Pointer FIFO

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