Ch.

6 Basic FET Amplifiers

In the last chapter, we described the operation of the FET, in particular the MOSFET, and analyzed and
designed the dc response of circuits containing these devices. In this chapter, we ephasize the use of FETs
in linear aplifier applications. !lthough a a"or use of MOSFETs is in digital applications, they are also
used in linear aplifier circuits.
There are three basic configurations of single#stage or single#transistor FET aplifiers. These are the
coon#source, source#follower, and coon#gate configurations. $e investigate the characteristics of
each configuration and show how these properties are used in various applications. Since MOSFET
integrated circuit aplifiers norally use MOSFETs as load devices instead of resistors because of their
sall size, we introduce the techni%ue of using MOSFET enhanceent or depletion devices as loads. These
three configurations for the building bloc&s for ore cople' aplifiers, so gaining a good understanding
of these three aplifier circuits is an iportant goal of this chapter.
In integrated circuit systes, aplifiers are usually connected in series or cascade, foring a ultistage
configuration, to increase the overall voltage gain, or to provide a particular cobination of voltage gain and
output resistance. $e consider a few of the any possible ultistage configurations, to introduce the
analysis ethods re%uired for such circuits, as well as their properties.
6.1 THE MOSFET AMPLIFIER
In (hapter ), we discussed the reasons linear aplifiers are necessary in analog electronic systes. In this
chapter, we continue the analysis and design of linear aplifiers that use field#effect transistors as the
aplifying device. The ter sall signal eans that we can linearize the ac e%uivalent circuit. $e will
define what is eant by sall signal in the case of MOSFET circuits. The ter linear aplifiers eans that
we can use superposition so that the dc analysis and ac analysis of the circuits can be perfored separately
and the total response is the su of the two individual responses.
The echanis with which MOSFET circuits aplify sall tie#varying signals was introduced in the last
chapter. In this section, we will e'pand that discussion using the graphical techni%ue, dc load line, and ac
load line. In the process, we will develop the various sall#signal paraeters of linear circuits and the
corresponding e%uivalent circuits.
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There are four possible e%uivalent circuits that can he used. These are listed in Table ).* of (hapter ).
The ost coon e%uivalent circuit that is used for the FET aplifiers is the transconductance aplifier, in
which the input signal is a voltage and the output signal is a current.
.
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6.1 .1 Graphical Analsis! L"a# Lines! an# Small$Si%nal Parame&ers
Figure -. / shows an 0MOS coon#source circuit with a tie#varying voltage source in series with the dc
source. $e assue the tie#varying input signal is sinusoidal. Figure -.+ shows the transistor
characteristics, dc load line, and 1#point, where the dc load line and 1#point are functions of v2S, 344, 54
and the transistor paraeters.
For the output voltage to be a linear function of the input voltage, the transistor ust be biased in the
saturation region. 0ote that, although we priarily use n#channel, enhanceent #ode MOSFETs in our
discussions, the sae results apply to the other MOSFETs.
!lso shown in Figure -.+ are the sinusoidal variations in the gate#to#source voltage, drain current, and drain#
to#source voltage, as a result of the sinusoidal source vi. The total gate#to#source voltage is the su of 32S1
and vi. !s vi increases, the instantaneous value of v2S increases, and the bias point oves up the load line.
! larger value of v2S eans a larger drain current and a saller value of v4S. Once the 1#point is established,
we can develop a atheatical odel for the sinusoidal, or sall#signal, variations in the gate#to#source
voltage, drain#to#source voltage, and drain current.
The tie#varying signal source in Figure -./ generates a tie#varying coponent of the gate#to#source
voltage. For the FET to operate as a linear aplifier, the transistor ust be biased in the saturation region,
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and the instantaneous drain current and drain#to#source voltage ust also be confined to the saturation
region.
Transis&"r Parame&ers
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source is assued to be constant, the sinusoidal current produces no sinusoidal voltage coponent across
this eleent. The e%uivalent ac ipedance is therefore zero, or a short circuit. (onse%uently, in the ac
e%uivalent circuit, the dc voltage sources are e%ual to zero. $e say that the node connecting 54 and 344 is at
signal ground.
6.1.' Small$Si%nal E()i*alen& Circ)i&
0ow that we have the ac e%uivalent circuit for the 0MOS aplifier circuit, 8Figure -.)9, we ust develop a
sall#signal e%uivalent circuit for the transistor.
Initially, we assue that the signal fre%uency is sufficiently low so that any capacitance at the gate terinal
can be neglected. The input to the gate thus appears as an open circuit, or an infinite resistance. E%. -./)
relates the sall#signal drain current to the sall#signal input voltage and E%. -.. shows that the
transconductance is a function of the 1#point. The resulting siplified sall#signal e%uivalent circuit for the
0MOS device is shown in Figure -.:. 8The phasor coponents are in parentheses.9
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This sall#signal e%uivalent circuit can also he e'panded to ta&e into account the finite output resistance of a
MOSFET biased in the saturation region. This effect, discussed in the previous chapter, is a result of the
nonzero slope in the i4 versus v4S curve. $e &now that
The e'panded sall#signal e%uivalent circuit of the n#channel MOSFET is shown in Figure -.- in phasor
notation.
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$e note that the sall#signal e%uivalent circuit for the MOSFET circuit is very siilar to that of the ;<T
circuits considered in (hapter ).
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(oent= ;ecause of the relatively low value of transconductance, MOSFET circuits tend to have a lower
sall#signal voltage gain than coparable bipolar circuits. !lso, the sall#signal voltage gain contains a
inus sign, which eans that the sinusoidal output voltage is /67 degrees out of phase with respect to the
input sinusoidal signal
Pr"+lem$S"l*in% Techni()e, MOSFET AC Analsis
Since we are dealing with linear aplifiers, superposition applies, which eans that we can perfor the dc
and ac analyses separately. The analysis of the MOSFET aplifier proceeds as follows=
/. !nalyze the circuit with only the dc sources present. This solution is the dc or %uiescent solution. The
transistor ust he biased in the saturation region in order to produce a linear aplifier.
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+. 5eplace each eleent in the circuit with its sall#signal odel, which eans replacing the transistor by
its sall#signal e%uivalent circuit.
*. !nalyze the sall#signal e%uivalent circuit, setting the dc source coponents e%ual to zero, to produce
the response of the circuit to the tie#varying input signals only.
The previous discussion was for an n#channel MOSFET aplifier. The sae basic analysts and e%uivalent
circuit also applies to the p#channel transistor. Figure -.68a9 shows a circuit containing a p#channel
MOSFET.
0ote that the power supply voltage is connected to the source. 8The subscript 44 can be used to indicate that
the supply is connected to the drain terinal >ere, however, 344, is siply the usual notation for the power
supply voltage in MOSFET circuits.9 !lso note the change in current directions and voltage polarities
copared to the circuit containing the 0MOS transistor. Figure -.68b9 shows the ac e%uivalent circuit, with
the dc voltage sources replaced
The final sall#signal e%uivalent circuit of the p#channel MOSFET aplifier is shown in Figure -./7
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$e also note that the e'pression for the sall#signal voltage gain of the p#channel MOSFET aplifier is
e'actly the sae as that for the n#channel MOSFET aplifier. The negative sign indicates that a /67#degree
phase reversal e'ists between the output and input signals, for both the ?MOS and the 0MOS
circuit.
6.' BASIC TRA-SISTOR AMPLIFIER CO-FIG.RATIO-S
!s we have seen, the MOSFET is a three#terinal device 8actually ) counting the substrate9. Three basic
single#transistor aplifier configurations can be fored, depending on which of the three transistor terinals
is used as signal ground. These three basic configurations are appropriately called coon source, coon
drain 8source follower9, and coon gate. These three circuit configurations correspond to the coon#
eitter, eitter#follower, and coon#base configurations using ;<Ts.
The input and output resistance characteristics of aplifiers are iportant in deterining loading effects.
These paraeters, as well as voltage gain, for the three basic MOSFET circuit configurations will be
deterined in the following sections.
6./ THE COMMO-$SO.RCE AMPLIFIER
in this section, we consider the first of the three basic circuits@ the coon#source aplifier. $e will
analyze several basic coon#source circuits, and will deterine sall#signal voltage gain and input and
output ipedances.
6./.1 A Basic C"mm"n$S")rce C"nfi%)ra&i"n
For the circuit shown in Figure -./*, assue that the transistor is biased in the saturation region by resistors
5/ and 5+, and that the signal fre%uency is sufficiently large for the coupling capacitor to act essentially as a
short circuit. The signal source is represented by a Thevenin e%uivalent circuit, in which the signal voltage
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source vi, is in series with an e%uivalent source resistance 5Si. !s we will see, 5Si should be uch less than
the aplifier input resistance, 5i A 5/ BB 5+ in order to iniize loading effects.
Figure -./) shows the resulting sall#signal e%uivalent circuit. The sall signal variables, such as the input
signal voltage 3i are given in phasor for.
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The output voltage is
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The input and output resistances of the aplifier can be deterined fro Figure -./). The input resistance to
the aplifier is 5is A 5/ BB 5+. Since the low#fre%uency input resistance loo&ing into the gate of the MOSFET
is essentially infinite, the input resistance is only a function of the bias resistors. The output resistance
loo&ing hac& into the output terinals is found by setting the independent input source 3i e%ual to zero,
which eans that 32S A 7. The output resistance is therefore 5o A 54 BB ro.
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6./.' C"mm"n$S")rce Amplifier 0i&h S")rce Resis&"r
! source resistor 5S tends to stabilize the 1#point against variations in transistor paraeters 8Figure -./69.
If, for e'aple, the value of the conduction paraeter varies fro one transistor to another, the 1#point will
not vary as uch if a source resistor is included in the circuit. >owever, as shown in the following e'aple,
a source resistor also reduces the signal gain. This sae effect was observed in ;<T circuits when an eitter
resistor was included.
The circuit in Figure -./6 is an e'aple of a situation in which the body effect 8not discussed9 should be
ta&en into account. The substrate 8not shown9 would norally be connected to the #: 3 supply, so that the
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body and substrate terinals are not at the sae potential. >owever, in the following e'aple, we will
neglect this effect.
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6././ C"mm"n$S")rce Circ)i& 0i&h S")rce Bpass Capaci&"r
! source bypass capacitor added to the coon#source circuit with a source resistor will iniize the loss
in the sall#signal voltage gain, while aintaining 1#point stability. The 1#point stability can be further
increased by replacing the source resistor with a constant#current source. The resulting circuit is shown in
Figure -.++, assuing an ideal signal source. If the signal fre%uency is sufficiently large so that the bypass
capacitor acts essentially as an ac short#circuit, the source will be held at signal ground.
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6.1 THE SO.RCE$FOLLO2ER AMPLIFIER
The second type of MOSFECT aplifier to be considered is the coon#drain circuit. !n e'aple of this
circuit configuration is shown in Figure -.+6.
!s seen in this figure, the output signal is ta&en off the source with respect to ground and the drain is
connected directly to 344. Since 344 becoes signal ground in the ac e%uivalent circuit, we get the nae
coon drain, but the ore coon nae is a source follower. The reason for this nae will becoe
apparent as we proceed through the analysis.
6.1.1 Small$Si%nal 3"l&a%e Gain
The dc analysis of the circuit is e'actly the sae as we have already seen, so we will concentrate on the
sall#signal analysis. The sall#signal e%uivalent circuit, assuing the coupling capacitor acts as a short
circuit, is shown in Figure -.+,8a9. The drain is at signal ground, and the sall#signal resistance ro of the
transistor is in parallel with the dependent current source. Figure -.+,8b9 is the sae e%uivalent circuit, but
with all signal grounds at a coon point. $e are again neglecting the body effect. The output voltage is
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6.1.' Inp)& an# O)&p)& impe#ance
The input resistance 5i, as defined in Figure -.+,Db9, is the Thevenin e%uivalent resistance of the bias
resistors. Even though the input resistance to the gate of the MOSFET is essentially infinite, the input bias
resistances do create a loading effect. This sae effect was seen in the coon#source circuits.
To calculate the output resistance, we set all independent sall#signal sources e%ual to zero, apply a test
voltage to the output terinals, and easure a test current. Figure -.*/ shows the circuit we will use to
deterine the output resistance of the source follower shown in Figure -.+6.
$e set 3i A 7 and apply a test voltage 3'. Since there are no capacitances in the circuit, the output ipedance
is siply an output resistance, which is defined as
5o A 3' E I'
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6.4 THE COMMO-$GATE CO-FIG.RATIO-
The third aplifier configuration is the coon#gate circuit. To deterine the sall#signal voltage and
current gains, and the input and output ipedances, we will use the sae sall#signal e%uivalent circuit for
the transistor that was used previously. The dc analysis of the coon#gate circuit is the sae as that of
previous MOSFET circuits.
5.4.1 Small$Si%nal 3"l&a%e an# C)rren& Gains
In the coon#gate configuration, the input signal is applied to the source terinal and the gate is at signal
ground. The coon#gate configuration shown in Figure -.*)) is biased with a constant#current source I1.
The gate resistor 52 prevents the buildup of static charge on the gate terinal, and the capacitor (2 ensures
that the gate is at signal ground. The coupling capacitor ((/ couples the signal to the source, and coupling
capacitor ((+ couples the output voltage to load resistance 5F.
The sall#signal e%uivalent circuit is shown in Figure -.*:. The sall#signal transistor resistance rO is
assued to be infinite.
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The output voltage is
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6.4.' Inp)& an# O)&p)& Impe#ance
In contrast to the coon#source and source#follower aplifiers, the coon#gate circuit has a low input
resistance because of the transistor. >owever, if the input signal is a current, a low input resistance is an
advantage. The input resistance is defined as
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6.6 THE THREE BASIC AMPLIFIER CO-FIG.RATIO-S, S.MMAR6 A-7 COMPARISO-
Table -./ is a suary of die sall#signal characteristics of the three aplifier configurations.
The input resistance loo&ing directly into the gate of the coon#source and source#follower circuits is
essentially infinite at low to oderate signal fre%uencies. >owever, the input resistance, of these discrete
aplifiers is the Thevenin e%uivalent resistance 5T> of the bias resistors. In contrast, the input resistance to
the coon#gate circuit is generally in the range of a few hundred ohs.
The output resistance of the source follower is generally in the range of a few hundred ohs. The output
resistance of the coon#source and coon#gate configurations is doinated by the resistance 54. The
specific characteristics of these single#stage aplifiers are used in the design of ultistage aplifiers.
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6.8 SI-GLE$STAGE I-TEGRATE7 CIRC.IT MOSFET AMPLIFIERS
In the last chapter, we considered three all#MOSFET inverters and plotted the voltage transfer characteristics.
!ll three inverters use an n#channel enhanceent#ode driver transistor. The three types of load devices are
an n#channel enhanceent#ode device, an n#channel depletion#ode device, and a p#channel enhanceent#
ode device. The MOS transistor used as a load device is referred to as an active load. $e entioned that
these three circuits can be used as aplifiers.
In this section, we revisit these three circuits and consider their aplifier characteristics. $e will ephasize
the sall#signal e%uivalent circuits. This section serves as an introduction to ore advanced MOS integrated
circuit aplifier designs considered in ?art II of the te't.
6.8.1 -MOS Amplifiers 0i&h Enhancemen& L"a#
The characteristics of an n#channel enhanceent toad device were presented in the last chapter. Figure
-.*68a9 shows an 0MOS enhanceent load transistor.
and Figure -.*6Db9 shows the current#voltage characteristics. The threshold voltage is 3T0F.
Figure -.*,8a9 shows an 0MOS aplifier with an enhanceent load.
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The driver transistor is M4 and the load transistor is MF. The characteristics of transistor M4 and the load
curve are shown in Figure -.*,8b9. The load curve is essentially the irror iage of the i#v characteristic of
the load device. Since the i#v characteristics of the load device are nonlinear, the load curve is also
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nonlinear. The load curve intersects the voltage a'is at 344 G 3T0F, which is the point where the current in
the enhanceent load device goes to zero. The transition point is also shown on the curve.
The voltage transfer characteristic is also useful in visualizing the operation of the aplifier. This curve is
shown in Figure -.*,8c9. $hen the enhanceent#ode driver first begins to conduct, it is biased in the
saturation region. For use as an aplifier, the circuit 1#point should be in this region, as shown in both
Figures -.*,Db9 and 8c9.
$e can now apply the sall#signal e%uivalent circuits to find the voltage gain. In the discussion of the
source follower, we found that the e%uivalent resistance loo&ing into the source terinal 8with 5S A H9 was
5O A 8l E g9 BB rO. The sall#signal e%uivalent circuit of the inverter is given in Figure -.)7, where the
subscripts 4 and F refer to the driver and load transistors, respectively. $e are again neglecting the body
effect of the load transistor.
The sall#signal voltage gain is
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6.8.' -MOS Amplifier 0i&h 7eple&i"n L"a#
Figure -.)+8a9 shows the 0MOS depletion#ode transistor connected as a load device and Figure -.)+8b9
shows the current#voltage characteristics. The transition point is also indicated. The threshold voltage 3T0F
of this device is negative, which eans that the v4S value at the transition point is positive. !lso the slope of
the curve in the saturation region is not zero@ therefore, a finite resistance rO e'ists in this region.
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Figure -.)*8a9 shows an 0MOS depletion load aplifier. The transistor characteristics of M4 and the load
curve for the circuit are shown in Figure -.)*8b9.
The load curve again, is the irror iage of the i#v characteristic of the load device. Since the i#v
characteristics of the load device are nonlinear, the load curve is also nonlinear. The transition points for both
M4 and MF are also indicated. ?oint ! is the transition point for M4, and point ; is the transition point for
MF. The 1#point should be appro'iately idway between the two transition points.
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The dc voltage 32S41 biases transistor M4 in the saturation region at the 1#point. The signal voltage vi
superiposes a sinusoidal gate#to#source voltage on the dc value, and the bias point oves along the load
curve about the 1#point. !gain, both M4 and MF ust be biased in their saturation regions at all ties.
The voltage transfer characteristic of this circuit is shown in Figure -.)*8c9. 5egion III corresponds to the
condition in which both transistors are biased in the saturation region. The desired 1#point is indicated.
$e can again apply the sall#signal e%uivalent circuit to find the sall#signal voltage gain. Since the gate#
to#source voltage of the depletion#load device is held at zero, the e%uivalent resistance loo&ing into the
source terinal is 5O A rO. The sall#signal e%uivalent circuit of the inverter is given in Figure -.)), where
the subscripts 4 and F refer to the driver and load transistors, respectively. $e are again neglecting the body
effect of the load device.
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6.8./ -MOS Amplifier 0i&h PMOS L"a#
C"mm"n$S")rce Amplifier
!n aplifier using an n#channel enhanceent#ode driver and a p#channel enhanceent ode active load is
shown in Figure -.):8a9 in a coon#source configuration. The p#channel active load transistor M+ is biased
fro M* and I;ias. This configuration is siilar to the MOSFET current source shown in Figure :.*, in
(hapter :. $ith both n# and p#channel transistors in the sae circuit, this circuit is now referred to as a
(MOS aplifier.
The i#v characteristic curve for M+ is shown in Figure -.):8b9. The source#to#gate voltage is a constant and
is established by M*. The driver transistor characteristics and the load curve are shown in Figure -.):8c9.
The transition points of both M/ and M+ are shown. ?oint ! is the transition point for M/ and point ; is the
transition point for M+. The 1#point, to establish an aplifier, should be appro'iately halfway between
points ! and ;, so that both transistors are biased in their saturation regions. The voltage transfer
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characteristics are shown in Figure -.):8d9. Shown on the curve are the sae transition points ! and ; and
the desired 1#point.
$e again apply the sall#signal e%uivalent circuits to find the sall#signal voltage gain. $ith vS2+ held
constant, the e%uivalent resistance loo&ing into the drain of M+ is "ust 5O A rop. The sall#signal e%uivalent
circuit of the inverter is then as given in Figure -.)-. The subscripts n and p refer to the n#channel and p#
channel transistors, respectively. $e note that the body terinal of M/, will he tied to ground, which is the
sae as the source of M/, and the body terinal of M+ will be tied to 344 which is the sae as the source of
M+. >ence, there is no body effect in this circuit.
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4iscussion= In die circuit configuration shown in Figure -.):8a9, we ust again apply a dc voltage to the gate
of M/ to achieve the IproperI 1#point.
CMOS S")rce$F"l"0er an# C"mm"n$Ga&e Amplifiers
The sae basic (MOS circuit configuration can be used to for (MOS source#follower and coon#gate
configurations. Figure -.).8a9 and 8b9 show these circuits.
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$e see that for the source#follower circuit, the active load 8M+9 is an n#channel rather than a p#channel
device. The input is applied to the gate of M/ and the output is ai the source of M/. For the coon#gate
aplifier, the active load 8M+9 is again a p#channel device. The input is applied to the source of M/ and the
output is at the drain of M/.
$e note that in both the source#follower arid coon#gate circuits, the body effect will need to be ta&en
into account. In both circuits, the body terinal of the aplifying transistor M/ will be connected to the
ost negative voltage, which is not the sae as the source terinal.
6.5 M.LTISTAGE AMPLIFIERS
In ost applications, a single#transistor aplifier will not be able to eet the cobined specifications of a
given aplification factor, input resistance, and output resistance. For e'aple, the re%uired voltage gain
ay e'ceed that which can be obtained in a single#transistor circuit.
Transistor aplifier circuits can be connected in series, or cascaded, as shown in Figure -.)6. This ay be
done either to increase the overall sall#signal voltage gain, or provide an overall voltage gain greater than
/, with a very low output resistance. The overall voltage gain ay not siply be the product of the individual
aplification factors. Foading effects, in general, need to be ta&en into account.
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There are any possible ultistage configurations@ we will e'aine a few here, in order to understand the
type of analysis re%uired.
6.5.1 7C Analsis
The circuit shown in Figure -.), is a cascade of a coon#source aplifier followed by a source#follower
aplifier. !s shown previously, the coon#source aplifier provides a sall#signal voltage gain and the
source follower has a low output ipedance.
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6.19 S.MMAR6
a. The application of MOSFET transistors in linear aplifier circuits was ephasized in this chapter. !
sall#signal e%uivalent circuit for the transistor was developed, which is used in the analysis and
design of linear aplifiers.
b. Three basic circuit configurations were considered= the coon source, source follower, and
coon gate. These three configurations for the basic building bloc&s for cople' integrated
circuits. The sall#signal voltage gains and output resistances for these circuits were analyzed. The
circuit characteristics of the three circuits were copared in Table -./.
c. The ac analysis of circuits with enhanceent load devices, with depletion bad devices, and
copleentary 8(MOS9 devices were analyzed.
E04 (>. -
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