University of Michigan, 598 design project, 2004.

A 10 bit 100MHz pipeline ADC.

Mark Ferriss, Joshua Kang

AbstractThis paper describes a 10 bit, 1.5 bit per stage

pipeline ADC. The ADC has a max sampling rate of 100 MHz, and
has been designed on a 0.25, 2.5V CMOS process. Several novel
design techniques have been introduced in order to address some
of the limiting factors in a state of the art ADC design. These
techniques have been verified in simulation, and an ENOB of 9.01
has been achieved.

I. INTRODUCTION

HE pipeline ADC is a popular architecture for data

conversion schemes which require a compromise between
speed and accuracy. Although the pipeline architecture is
inherently not as fast as a flash scheme, its serial nature results in
a linear scaling of power and area with resolution, apposed to
the exponential scaling which occurs in a flash, resulting in the
pipeline architecture being a more attractive solution around
and above the 9 bit level. Similarly, for very high resolution
schemes sigma delta architectures are generally used, however
the over-sampling nature of such schemes limits the maximum
speed to a fraction of the fastest possible sampling rate.
However the concurrent nature of a pipeline removes the
over-sampling required, in effect converting the over-sampling
speed limit into a latency problem.

Figure 1. ADC architecture is a compromise between resolution and speed.

A. Performance limits.
The accuracy limitation of most ADC architectures is a
function of various forms of comparator offset errors, which

limits the resolution of the ADC. However, a 1.5 bit per-stage

pipeline ADC can be made insensitive to comparator offset
errors, by resolving 1 bit per stage, and reserving 0.5bits for
error correction [1], resulting in relaxed offset requirements for
the comparator. The resolution limits of the ADC, then are set
by thermal noise limits (kT/C) and inter-stage amplification
error, which can generally be classified into two sections;
capacitor mismatch errors and amplifier errors (Input referred
offset, incomplete settling, and finite gain errors).
B. Recent trends.
As discussed above, one of the dominant sources of error in a
pipeline ADC is capacitor mismatch. However this source of
error has some characteristics which make it suitable for
calibration in a modern ADC scheme. Firstly, capacitor
mismatch errors result in a linear error, meaning that if the
mismatch can be measured, then the results of this error will be
predictable over the entire voltage range of the amplifier.
Secondly this is predominantly caused by a physical size
mismatch which will not drift with temperature, supply, or clock
speed variation. These two characteristics yield an error that is
very suitable for calibration correction, and several previous
works have demonstrated this. Hence, in a calibrated system, the
capacitor sizes can be reduced until the thermal noise starts to
dominate.
Errors in the amplifiers are more difficult to deal with. If the
amplifier does not settle in the allocated time, than the resulting
error can be very non-linear, as the settling error will tend to be
disproportional large the further the answer is from the
amplifiers starting point. Furthermore, the amplifier speed will
be dependant on temperature, supply, and clock speed
variations, which lead to an unpredictable error that cannot
easily be calibrated out. Several works have shown that
calibration of these errors is possible, however some
assumptions about temperature, supply variations, clock speed,
or the spectral content of the data must be made.
As process supplies shrink, these problems are compounded by
the fact that there is a smaller voltage supply to work with, hence
achieving large dc gains in single stage amplifiers becomes
challenging. As resolution increases, the capacitor sizes must
increase in order to overcome thermal noise. For these reasons
the inter-stage amplifier becoming the primary limiting factor in
a state of the art ADC.
This work will present some novel new techniques that attempt
to deal with these errors without relying on a calibration phase
of operation.
C. Performance limitations of 1.5bit stage review.
A single 1.5bit stage consists of an ADC, a DAC and a
summing gain of 2 amplifier as can be seen in Figure 2.

University of Michigan, 598 design project, 2004.

2
capacitor would be in danger of being swamped by parasitic
capacitances.

Figure 2: A 1.5bit stage.

One bit of resolution of the stage contributes to the over all

resolution of the ADC, while half a bit is used to correct for
offset errors in the comparator, and hence the comparator can be
shown to be insensitive to offsets [1]. However the multiplying
DAC errors and the amplification errors are not corrected,
hence the amplifier must be as accurate as the resolution of the
overall ADC. In practice, the MDAC uses an array of capacitors
and a high gain amplifier in order to implement both functions
as in Figure 2. As the input signal is effectively amplified further
down the pipeline, the resolution requirements for the later
amplifiers are significantly relaxed. Therefore the performances
of the first and second stages are the most critical, and hence this
paper will concentrate on correcting for errors in these stages.
II. OUR NOVEL IDEAS.
A. Capacitance sharing idea.
As can be observed in Figure 3 When stage 1 is amplifying,
stage 2 is sampling. When the amplification phase is complete,
the voltage across the feedback capacitance is identical to the
voltage across the two capacitances of the next stage.

Figure 3: As stage 1 amplifiers, the next stage samples.

Additionally, the resolution requirements are relaxed for later

stages of the pipeline, therefore the capacitance of the second
stage can be one half of that of the first stage. This results in the
voltage across, and the value of, the second stage sampling
capacitance being identical to that of the first stage feedback
capacitor.
Using this information, a novel method of passing the signal
from one stage to the next is proposed. Instead of charging up
the next stage sampling capacitors, move the entire feedback
capacitors of the first to the second stage, thus avoiding the
requirement for sampling capacitors of the second stage as in
Figure 4. Additionally, a similar relationship exists between the
second and third stage as to the first and second. Hence when the
second stage has completed its amplification phase, its feedback
capacitor can be passed to the third stage. This process can in
principle be continued down the entire pipeline, however in
practice, the capacitance halving from stage to stage is only
continued for a small number of stages, as a very small unit

Figure 4: Moving sampling capacitors to the next stage.

In this implementation, the scheme was used for the first three
stages. The net result of this is that the capacitance that the first
and second stages need to drive is divided by half compared
with the conventional scheme. This has the potential to half the
power requirements for charging and discharging of the
capacitors (not including the comparator capacitors). A demerit
of this scheme is that 2 separate capacitor sets need to be used,
in every second sample phase of the first stage. Mismatch
between the 2 sets may cause additional INL errors. However,
as already discussed, capacitor mismatch errors by their nature
lend easily to calibration methods. Amplifier errors, on the other
hand, do not, so this scheme not also saves power, but reduce
the speed requirements of the amplifier, as it is easier to achieve
complete settling.
B. Error cancellation scheme.
Next, the focus shifts to reducing the effects of the amplifier
errors. Consider the standard amplification phase as seen in
Figure 2.

Figure 5: Offset error due to amplifier.

Any error generated by the amplifier due to incomplete settling

can be modeled as a voltage offset in series with the gate.
Consider how big the voltage error caused by the amplifier
offset is across the feedback capacitor in Figure 5. One of the
quirks of the capacitance sharing scheme described in section A
is that although the voltage at the output node contains twice the
original error, the voltage across the feedback capacitor
contains only one offset error. (This can be observed if KVL is
done from the negative terminal of the amplifier to the output
node).
The offset is gained up in the same way as the signal and
hence is indistinguishable from the signal on the output node.
However, it can be observed that the error caused by the
amplifier (modeled in Figure 5 as a voltage source) is still
present on the original sampling capacitor; hence this can be
used in a later stage to cancel out the original error. As can be
seen in Figure 6, the charge stored on this capacitor can be

University of Michigan, 598 design project, 2004.

switched into the summing node of a later stage in order to
cancel this error source.

Figure 6: error cancellation scheme, the single ended version is shown.

The diagram shows the original sampling capacitor with its

bottom terminal tied to ground. In the practical implementation
this may in fact be tied to Vref+ or Vref-. However this does not
change the scheme, it simply means that, when the capacitor is
switched back into the signal path at a later stage, its bottom
plate must remain connected to the same voltage as it was
connected when it was used in the first stage, thus requiring a
small amount of additional logic.
Finally, as the signal propagates down the pipeline, it is gained
up by two by each stage, therefore it might be expected that the
error cancellation scheme described here would have to gain up
the error as well, if the error is to be cancelled in a later stage.
However, the resolution requirements are relaxed in later stages
of the pipeline, so the size of the capacitances can be halved
from one stage to the next, at least until the capacitance size
reaches some nominally small value. If we consider the error
stored on the input capacitance to be in the form of a charge,
then when this charge is added to the summing node of a later
stage (which is using smaller capacitances) then its affect will be
gained up by its ratio to the capacitances in correction stage.

3
referred offset errors, finite gain errors) two 40mV, 10MHz,
sinusoidal sources were placed in series with the negative
terminal of the first two amplifiers. Figure 7 shows the results of
a simulation where the input is ramped from 0 to full scale in a
transient simulation.
Figure 7 shows the input, the output for the non corrected case,
and the output for the corrected case. As can be seen, the
non-corrected case contains all of the amplifier errors
superimposed onto the original signal, which can only be
removed by ensuring the amplifier is of high enough quality to
keep that the errors small. On the other hand the simulation of
our scheme (The second output shown), which contains all of
the same error sources, produces and output which tracks the
original signal, with all of the errors successfully removed. In
conclusion, this demonstrates that our scheme has been
effective in removing these errors.
III. IMPLEMENTATION DETAILS.
A. Switch.
The first real circuit to be considered is the switch.

Figure 8(a) First charge injection scheme (b) second scheme.

Any extra capacitance added to the summing node of the

amplifier will reduce the feedback factor, and slow down the
amplifier. In General the feed back factor is given by
C2
(1)
feebackfactor =
C 2 +C 1+C switch

Figure 7: Plot showing the AHDL simulation results, for normal case and error
corrected case.

In order to verify the scheme described above, a model was

developed with the sub blocks such as the amplifiers,
comparators and switches implemented as AHDL code, and
with schematics which would otherwise be identical to the final
design. In order to mimic the effects of any offset errors of the
amplifier (which may consist of incomplete settling errors, input

Where Cswitch is the parasitic capacitances associated with the

extra switches attached to the summing node. The switches may
not cause much of a problem in a standard design, however in
our design a large number of switches will be connected into all
of the summing nodes because of the switches associated with
moving the capacitors around. Our first attempt at a switch can
be seen in Figure 8(a). The primary switching device is an
NMOS, with two dummy devices used to cancel the charge
injection caused by the main switch. The dummy devices turn
off as the main device turns on, hence effectively canceling the
capacitive feed through charge. The dummy devices are scaled
to half the size of the primary device, assuming that the injected
charge will be distributed equally to both side of the switch.
This scheme was found to do an excellent job for charge
injection cancellation, however as the dummy device is turned
on when the main switch is off, there is large parasitic
capacitance associated with this scheme due to the CGS of the
dummy. Instead, a combination of an NMOS and PMOS can be
used as can be seen in Figure 8(b). To turn off an NMOS the
gate goes from high to low, a PMOS is low to high; hence this
scheme was found to have reasonable charge injection
cancellation properties. Although the charge injection is not as
good as using dummy switches, this scheme crucially does not

University of Michigan, 598 design project, 2004.

have any devices which are turn on when the overall switch is in
the off state, therefore the associated parasitic capacitances are
very small. In our design, scheme Figure 8(b) was for used the
large number of switches required to move capacitors around,
while scheme Figure 8(a) was used for nodes less sensitive to
parasitic capacitances. No noticeable degradation in overall
performance was found due to charge injection effects.
B. Amplification scheme
In a pipeline ADC, the speed of the inter-stage amplifier is a
critical limiting factor in the over-all pipeline performance.
Conventionally, single stage amplifiers are used, as they do not
need complex stabilization schemes as there only one high gain,
high impedance node. Gain boosting techniques are used to
reduce the steady state errors. However, several key limitations
can be observed with such a scheme. Consider the single stage
amplifier in Figure 9(a).

Figure 9 (a) A conventional single stage amplifier

(b) The effects on settling due to slew limits.

If the amplifier has a bias current of Ib, then the maximum

current that can be delivered (to one of the outputs) is Ib/2.
Consider the case of a 2pF load capacitor, a 1V required swing
and 4ns of time to settle. If a full 2ns (50%) of the period is
allowed for settling, the minimum standing current can be
shown to be 2mA.
I
2V C
I out max = b I b min =
= 2 mA
(2)
t
2
This sets the lower bound of current that can flow in this
scheme. It should be noted at this point that conventionally a
single stage (or folded cascaded) is generally chosen as this
architecture can generate the best small signal performance
specs (position of poles, crossover freq, etc), however if the
amplifier is responding to a unit step input, then its non-linear
performance will dominate the settling time, i.e. because of the
slew limitations it may only act as a linear stage for a small
proportion of the settling. On the other hand, consider the
scheme proposed in Figure 10.

the two inputs are balance. Current Ib flows in each of the two
input devices, however current Ix is subtracted from Ib before it
is mirrored to the output. Therefore the static current flowing in
the output leg is
(3)
I static =( I b I x )n
If Ib is made similar to Ix, then the static current in the output
leg can be made close to zero, although for practical purposes,
more than 50uA of current will always flow in the output leg so
as to keep the common mode feedback amplifier alive, and to
keep all devices turned on. The static current in one of the input
current legs is Ib, but if n is large, then this can represent small
fraction of the overall power. Next, consider what happens if
there is a large input signal, and all of the current is flowing in
one of the input devices. In that case the current in the output
can be shown to be
(4)
I
=( 2 I I )n .

out max

If Ib is similar to Ix this simplifies to n*Ib. Hence the maximum

current that this scheme can deliver can be made much larger
that the static current flowing, hence effectively breaking the
link between the standing current in the amplifier and maximum
power that can be delivered. Additionally there still is only one
high impedance node, so stabilizing the amplifier is not
significantly different to that of the single stage amplifier,
although the extra current mirroring nodes can add some high
frequency parasitic poles. In the practical implementation of this
stage, the outputs were cascoded and gain boosted in order to
push the DC gain above 80dB, and a common mode feedback
amplifier was also included, which used a capacitor divider of
the output nodes to sense the common mode voltage. The final
scheme that was used can be seen in Figure 11.

Figure 11: The final switched capacitor amplification scheme

(Error correction and capacitance sharing ideas are not shown here).

The entire scheme, including biasing, gain boosting amplifiers

and common mode feedback, drew 1.5mA of current from the
supply, which is less then the 2mA current which would be
required for the output stage alone, using a conventional
scheme.
C. Comparator
Our comparator used a conventional scheme [3] which consists
of a PMOS differential input pair, a latch regenerative circuit
and an S-R latch. The comparator is used in conjunction with a
conventional switched capacitor scheme to sample the input
signal, and to sample the reference, as shown in Figure 12.

Figure 10: Our proposed amplification scheme.

The amplifier consists of a linearized input stage, using

resistor degeneration, and a class AB output stage. To
understand the circuit operation, first consider the case of when

University of Michigan, 598 design project, 2004.

5
Coherence test: M=5, 256 bins, Fs=100MHz => Fin=1.953125MHz

AHDL model

Figure 12: The switched capacitor comparator scheme, with timimg diagram.

IV. RESULTS
The top-level was verified under two conditions; 1 the
sub-blocks were modeled as AHDL, 2 the first three stages were
simulated as transistor level, including the amplifiers, switches,
comparators, and most digital blocks. A full transistor level
simulation was not completed. In Figure 13, the INL, and DNL
plots are shown for a sample selection of codes, with the DNL
and INL measured as less than 0.25 of an LSB for all cases. In
Figure 14, the results from a coherent test are shown.
AHDL model

Transistor model 1 to 3 stage

Transistor model 1 to 3 stage

SNDR 60.97dB (ENOB 9.83 bits)

SFDR 73.21 dB
THD -72.55 dB

SNDR 56.00 dB (ENOB 9.01 bits)

SFDR 64.60 dB
THD -62.09 dB

Figure 14, Results of the coherent test.

V. CONCLUSIONS.
In this paper, a 10bit 100MHz amplifier has been proposed,
and the performance verified in AHDL simulations, and partial
transistor level simulations. In addition, 3 novel new design
techniques have been introduced to attempt to deal with some of
the limitations of a conventional pipeline ADC. Firstly the
amount of capacitance the amplifier is required to drive has
been halved. Secondly, the settling requirement of the first 2
amplifiers has been removed, resulting in the overall
performance of the ADC being desensitized to the limits of the
first 2 amplifiers. Thirdly, amplifier architecture has been
proposed which breaks the link between the required standing
current, and the maximum output current by using a class AB
output.
REFERENCES

|DNL| < 0.1 LSB

|INL| < 0.11 LSB

|DNL| < 0.24 LSB

|INL| < 0.23 LSB

Figure 13: Results of the INL, DNL tests

The AHDL model produced an ENOB of 9.83bits while the

transistor level simulation produced an ENOB of 9.01bits. The
degradation in performance of the transistor level simulation
can be attributed to gain compression of our third amplifier. As
can be seen in the FFT plots there are noise spikes at the 3rd, 5th
and 7th harmonic locations, suggesting that the input signal has
been distorted and implying that the amplifier is compressing
the signal at large amplitudes. It is expected that this problem
can be fixed by redesigning the third amplifier optimized for a
larger feed back factor than was originally assumed.

[1] S. H. Lewis, P. H. Gray A pipelined 5-Msampled/s 9-bit Analog-to-digital

converter., JSSC, December 1987
[2] A. S. Abu Design for reliable low voltage switch capacitor circuits., thesis,
Berkeley 1992
[3] A High-Speed CMOS Comparator with 8-b Resolution. JSSC February
1992. G. M. Yin, F. Opt Eynde, and W. Sansen.
[4] Black, Hodges Time interleaved converter arrays, IEEE, JSSC, DEC
1980.
[4] Cho "Low-Power Low-Voltage Analog-to-Digital Conversion Techniques
using Pipelined Architectures," , thesis Berkeley 1995.
[5] Lewis et al, A 10-b 20-Msample/s Analog-to-Digital Converter, JSSC
March 1992.
[6] Gray, Hurst, Lewis and Meyer, Analysis and Design of Analog integrated
circuits, Wiley, Fourth addition.
[7] B. Razavi Data Conversion System Design, Wiley

APPENDIX
The simulation files are stored in the directory and library
/afs/engin.umich.edu/class/w04/eecs598/students/mferriss/ADC/.
The top cellview name is toplevel1 for first three stage transistor model, and
toplevel1_behav cellview is AHDL model.