Generic IC EMC Test Specification

Generic IC EMC Test Specification
I M PR E S SU M
©
Title: Generic IC EMC Test Specification ZVEI copyright 2010
Published by:
ZVEI - Zentralverband Elektrotechnik und Elektronikindustrie e.V.
(ZVEI – German Electrical and Electronic Manufactures' Association)
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Contact in the ZVEI:

Dr. Rolf Winter
Authors:
Joester, Michael Continental Automotive GmbH
Klotz, Dr. Frank Infineon Technologies AG
Pfaff, Dr. Wolfgang Robert BOSCH GmbH
Steinecke, Thomas Infineon Technologies AG
Photo (Cover):
Adam Opel GmbH

Infineon Technologies AG
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Revision: January 2010

Based on BISS Version 1.2 of November 2007
TA BL E O F CONT ENT
TABLE OF CONTENT
Introduction 1. Scope ....................................................................................................................................... 6
2. General and objective ............................................................................................................... 6
Normative References 3. Normative reference ................................................................................................................. 7
Definitions 4. Definitions ................................................................................................................................ 8
5. Splitting ICs into IC function modules ...................................................................................... 13
5.1 Matrix for splitting ICs ......................................................................................................... 13
5.2 Example of an IC built up with IC function modules ............................................................. 14
6. Test definitions ....................................................................................................................... 15
6.1 Test methods ..................................................................................................................... 15
6.2 Test parameters ................................................................................................................. 15
6.3 DUT Monitoring .................................................................................................................. 17
Test and Measurement 7. Test and measurement selection guide ................................................................................... 18
Selection Guide 7.1 Workflow for selection and test ........................................................................................... 18
7.1.1 Conducted tests ............................................................................................................ 19
7.1.2 Identification of IC function modules .............................................................................. 19
7.1.3 Pin Selection for Emission and Immunity ........................................................................ 19
7.1.4 IC function module and the coupling or injection points .................................................. 20
7.1.5 Selection guide emission ............................................................................................... 20
7.1.6 Selection guide immunity ............................................................................................... 21
7.2 Radiated tests .................................................................................................................... 22
7.2.1 Criteria for performing radiated Emission and Immunity Tests ........................................ 22
7.2.2 Selection guide emission ............................................................................................... 22
7.2.3 Selection guide immunity ............................................................................................... 22
Test and Measurement 8. Test and measurement networks ............................................................................................. 23
Networks 8.1 Port module ........................................................................................................................ 24
8.1.1 Line Driver .................................................................................................................... 24
8.1.2 Line Receiver ................................................................................................................ 25
8.1.3 Symmetrical Line Driver ................................................................................................. 26
8.1.4 Symmetrical Line Receiver ............................................................................................ 27
8.1.5 Regional Driver ............................................................................................................. 28
8.1.6 Regional Input ............................................................................................................... 29
8.1.7 High Side driver ............................................................................................................ 30
8.1.8 Low Side driver ............................................................................................................. 32
8.2 Supply module ................................................................................................................... 34
8.3 Core module ....................................................................................................................... 35
8.4 Oscillator module ............................................................................................................... 35
8.5 Signal decoupling- and monitoring setup ............................................................................. 36
8.6 Entire IC ............................................................................................................................. 38
Functional 9. Functional Configurations and Operating Modes ..................................................................... 39
Configurations and 9.1 Emission test configuration for ICs without CPU .................................................................. 39
Operating Modes 9.2 Immunity test configuration for ICs without CPU .................................................................. 41
9.3 Emission test configuration for ICs with CPU ...................................................................... 44
9.3.1 Test initialization software module for cores containing a CPU ....................................... 44
9.3.2 Immunity test configuration for ICs with CPU ................................................................. 47
9.3.3 Test loop software module for cores containing a CPU ................................................... 48
Test Board 10. Test board ............................................................................................................................ 49

TA BL E O F CONT ENT
IC EMC Test Limits 11. “Preliminary” IC EMC limits for Automotive ............................................................................ 50
11.1 Emission .......................................................................................................................... 50
11.1.1 Emission level scheme ................................................................................................ 50
11.1.2 General emission limit classes ..................................................................................... 51
11.1.3 Dedicated emission limits for 'external digital bus systems' .......................................... 53
11.2 Immunity .......................................................................................................................... 54
11.2.1 General immunity limit classes ..................................................................................... 54
Testing Documents 12. IC EMC Specification ............................................................................................................ 55
13. Test report ............................................................................................................................ 57
Terms of Usage 14. Copyrights and Liability ......................................................................................................... 58
15. Contacts and authors ............................................................................................................ 59
Annexes Annex A Layout Recommendation, (informative) ......................................................................... 60
Layout Example of 150 Ω networks on 2 layer and multi layer PCB ............................................. 60
Layout Example of 1 Ω network on 2 layer and multi layer PCB .................................................. 60
Layout Example of DPI network on 2 layer and multi layer PCB ................................................... 61
Layout Example of a TEM cell test board .................................................................................... 62
Layout Example for Digital systems built with IC types microcontrollers, RAMs ............................ 63
Annex B Test network modification (emission, normative) ........................................................... 69
Annex C Trace impedance calculation (informative) .................................................................... 71
Annex D Modulation definition (immunity, informative) ................................................................. 73
Annex E Example of an IC EMC specification (general, informative) ............................................ 74
Annex F Calculation of pin specific limits (general, informative) ................................................... 76
4
INTRO DUCT ION
Conditions of use
The use of the Generic IC EMC Test Specification is subject to the conditions of use
as stated in chapter 14.
By making use of the Generic IC EMC Test Specification the user acknowledges to
have taken notice of chapter 14 and to have agreed to the conditions of use stated in
chapter 14.
5
INTRO DUCT ION
1. Scope
The document is the technical basis to define common tests characterising the EMC behaviour
of Integrated Circuits (ICs) in terms of RF emission and immunity in the frequency range from
150 kHz to 1GHz. It contains all information to evaluate any kind of ICs in the same way. In
this document general information and definitions of IC types, pin types, test and
measurement networks, pin selection, operation modes and limit classes are given. This
allows the user to create an EMC specification for a dedicated IC as well as to provide
comparable results for comparable ICs.
2. General and objective

The objective and benefit of the document is
to obtain relevant quantitative measuring results
to reduce the number of test methods to a necessary minimum
to strengthen the acceptance of IC EMC test results
to minimize test effort to get comparable test results for IC suppliers and users
to release ICs based on IC level results
6
NO RMA TIVE R EF ER ENCE
3. Normative reference
International IC EMC standards

The following referenced documents are indispensable for the application of this document.
For dated references, only the edition cited applies. For undated references, the latest edition
of the referenced document (including any amendments) applies.
Emission:
[1] IEC 61967-1 Ed 1: 2002, Integrated circuits Measurement of electromagnetic

emissions 150 kHz to 1 GHz – Part 1: General conditions and definitions

emissions 150 kHz to 1 GHz – Part 2: Measurement of radiated emissions – TEM cell and
wideband TEM cell method

emissions 150 kHz to 1 GHz – Part 4: Measurement of conducted emissions - 1 Ω/150 Ω
direct coupling method
IEC 61967-4/A1/Ed 1: 2006, Amendment 1 to IEC 61967-4: Integrated circuits – Measurement

of electromagnetic emission, 150 kHz to 1 GHz - Part 4: Measurement of conducted emissions
– 1 Ohm/150 Ohm direct coupling method
[4] CISPR 25: Limits and methods of measurement of radio disturbance characteristics
for the protection of receivers used on board vehicles – second edition 2002-08
[10] IEC 61967-4-1/TR/Ed 1: APPLICATION GUIDANCE TO IEC 61967-4, Integrated

circuits - Measurement of electromagnetic emissions, 150 kHz to 1 GHz - Part 4:
Measurement of conducted emissions - 1 Ohm/150 Ohm direct coupling method
Immunity:

immunity 150 kHz to 1 GHz – Part 1: General and definitions
[6]* IEC 62132-2 (47A/774/CD), Integrated circuits Measurement of electromagnetic

immunity 150 kHz to 1 GHz – Part 2: Measurement of radiated immunity - TEM Cell and Wide
Band TEM Cell Method
[7] IEC 62132-4 Ed. 1: 2006, Integrated circuits Measurement of electromagnetic

immunity 150 kHz to 1 GHz – Part 4: Direct RF Power Injection Method
Other relevant documents
[8] IEC/TS 62228 Ed 1: 2007: Integrated circuits - EMC evaluation of CAN transceivers
[9]*** LIN EMC Test Specification, Version V1.0 (01.08.2004)
*) Working draft within IEC SC47A WG9

***) Working draft within German national working group DKE 767.13.5
7
D EF IN IT IO NS
4. Definitions
• analog
"Pertaining to the representation of information by means of a physical quantity which

may at any instant within a continuous time interval assume any value within a continuous
interval of values. Note. - The quantity considered may, for example, follow continuously
the values of another physical quantity representing information."
[IEV 101-12-05]
• Core
An →IC function module without any connection to outside of the IC via pins. (Note: The
supply is connected via the IC function module supply to pins, signals to pins are
connected via IC function module driver)
• digital
"Pertaining to the representation of information by distinct states or discrete values."
[IEV 101-12-07]
• EMC pin type
global pin
A 'global' pin carries a signal or power, which enters or leaves the application board
local pin
A 'local' pin carries a signal or power, which does not leave the application board. It
remains on the application PCB as a signal between two components with or without
additional EMC components.
• Fixed Function Unit (FFU)
Functional core sub-unit of the →IC function module 'Core', designed to perform one
fixed function without instruction decoding and executing capability.
• IC type
IC with a characteristic set of functions built in. These functions are realized with →IC
function modules.
8
D EF IN IT IO NS
• IC function module
An IC function module is a device functional part of an IC with at least one function and
its supply connection, if needed.
Passive IC function module: No supply system for supply connection

function
Active IC function module: A dedicated supply IC Function

inputs outputs
connection needed for function. Module
Note: The supply connection is handled as a supply reference

separate input/output pair as it has a dedicated connection
EMC behavior. Figure 1, Common definition of an
IC function module
• Integrated Circuit (IC)
An integrated circuit (IC) is a set of implemented

→IC function modules in one die or package.
• Pin
is an interface between an IC and its circuit environment.
• Port
An →IC function module containing minimum one Driver and/or minimum one Input each
connected to a signal pin.
• Active port:
An active port is initialized to a defined configuration or connected to a →fixed-function

module unit and is in operating mode during EMC measurements.
• Inactive port:
An inactive port is initialized to a defined configuration or connected to a →fixed-function

module unit and remains in a defined static mode.
• Test port:
A port selected for IC EMC tests.
• Printed Circuit Board (PCB):
A piece of isolating material with fixed metal traces to connect electronic components.
• Supply pin pairs
Supply pin pairs are all supply voltage pins of the same supply voltage system with their
related ground pin(s) of an IC supply module.
9
D EF IN IT IO NS
IC function modules
Port module
It is a set of minimum one port module 'Driver' and/or minimum one port module ´Input´.
Port modules are:

PLL factor
a) Line Driver
Supply module Supply module
Core Oscillator
drives signals leaving the application board (global Supply Supply
Oscillator
(PLL)
pin).
Digital Logic Digital Logic
Examples: ISO9141 outputs, LIN outputs or analog

Fixed-function Unit
or analog
Fixed-function Unit
b) Line Receiver Core

or analog or analog
receives signals from outside of the application Fixed-function Unit Fixed-function Unit
board (global pin).

Supply module
Port
Examples: ISO9141 inputs, LIN inputs Port Driver or
Input
Driver or
Input
Driver or
Input
Driver or
Input
Supply
c) Symmetrical Line Driver
drives differential signals leaving the application

board with two phase-correlated outputs (global pin)
Examples: CAN outputs, LVDS outputs
d) Symmetrical Line Receiver
receives differential signals from outside of the application board with two phase-correlated
inputs (global pin)
Examples: CAN inputs, LVDS inputs
e) Regional Driver
drives signals not leaving the application board (local pin).
Examples: serial data outputs, operational amplifier outputs
f) Regional Input
receives signals from the application board (local pin).
Examples: serial data inputs, Input stages of operational amplifiers, Analog-Digital-Converter

(ADC) inputs
g) High Side driver
drives power into loads. The current flows out of the driver (local or global pin).
Examples: High side switch, Switched mode power supply current output (buck converter)
h) Low Side driver
drives power into loads. The current flows into the driver (local or global pin).
10
D EF IN IT IO NS
Examples: Low side switch, Switched mode power supply current input (boost converter)
Supply module
distributes supply current to at least one IC PLL factor
function module (local or global pin). Supply module Supply module
Core Oscillator Oscillator

It is an IC function module with at least one current Supply Supply (PLL)
input pin of same supply system and minimum one

current output pin. It may contain active elements or analog

Fixed-function Unit
or analog
Fixed-function Unit
like voltage stabilization and/or passive elements

like internal charge buffering, current limiting Digital Logic Digital Logic
elements etc. or analog

Fixed-function Unit
or analog
Fixed-function Unit
Core module Supply module
Port Driver or Driver or Driver or Driver or

Supply Input Input Input Input
It is an IC function module without any connection
to outside of the IC via pins. The core is supplied
via the IC function module supply. It contains a set
of minimum one core module described below.
Core modules are:
a) Central Processing Unit (CPU)
A CPU decodes and executes instructions, can make decisions and jump to a
PLL factor
new set of instructions based on those decisions.

Supply module Supply module

Supply Supply (PLL)
Sub-units within the CPU decode and execute instructions (Sub-Unit CU
(Control Unit)) and perform arithmetic and logical operations (Sub-Unit ALU
Digital Logic
or analog
Digital Logic
or analog
(Arithmetic/Logic Unit)), making use of small number-holding areas called
Fixed-function Unit
registers.
Fixed-function Unit
Core
Digital Logic Digital Logic b) Digital Logic Fixed-Function Unit
or analog or analog
Fixed-function Unit Fixed-function Unit
Functional core sub-unit, designed to perform one fixed core digital logic
Supply module
function without instruction decode and execute capability.
Driver or Driver or Driver or Driver or
Port Input Input Input Input
Supply Examples: Clock distribution, Memory logic and arrays, Registers, Timer,
Watchdog Timer, State Machines, Programmable Logic Arrays (PLA).
11
D EF IN IT IO NS
c) Analog Fixed-Function Unit
Functional core analog sub-unit, clocked or unclocked, designed to perform one fixed core
analog function without instruction decode and execute capability.
Examples: Analog-to-digital-converter (ADC), Digital-to-analog-converter (DAC), Sample-

and-hold-circuits, Switched capacitor filter, Charge Coupled Devices (CCDs).
Dedicated Analog Fixed Function Unit: Sensor element
A sensor element is a converter of an environmental value into an electrical value and

therefore a FFU.
Examples: Hall sensor element for magnetic field sensing, E-field sensing, Acceleration
sensing. It can be combined with a precision amplifier (FFU), a supply module and a line driver
to realize an IC type "sensor".
Oscillator module
generates a periodic signal internally as a charge pump or clock generator by using a

combination of a fixed function module of the core with regional drivers and
PLL factor regional inputs. Due to the EMC behaviour it is dedicated to be defined as a
Supply module
separate IC function module.
Supply module

Supply Supply (PLL) A fixed-frequency-oscillator may be part of a Phase Locked Loop (PLL) circuit
with Voltage Controlled Oscillator (VCO), Low pass filter, Frequency Divider
and Phase Detection. All pins related to these circuits (for example divider,
or analog or analog
digital logic input pins) are part of this IC function module.

Core
or analog or analog
Supply module
Driver or Driver or Driver or Driver or
Port Input Input Input Input
Supply
12
SPLITTING IC S INTO IC FUNCTION MODULES
5. Splitting ICs into IC function modules
5.1 Matrix for splitting ICs

Functional module local external
connection external circuit via pin no pin
supply connection
circuits
IC Function
Driver (Outputs) Inputs Supplies Core Core/Inputs
inputs outputs
Module
All IC Function Module Supplies
Central Processing Unit (CPU)

supply reference
Analog Fixed Function Unit

Symmetrical Line Receiver
Digital Fixed Function Unit

connection
Symmetrical Line Driver
Regional Signal Driver
High Side Driver
Low Side Driver
Regional Input
Line Receiver
Line Driver
Oscillator
IC type examples
Microcontrollers • • • • • • •
Analog ICs Digital ICs
RAM, ROM,
• • • •
Bus Drivers
Logic Gate ICs • • • •
Operational
(•) (•) • • • •
Amplifier
VCOs • • • • •
Sensor Circuit • (•) (•) • •
High Side
(•) • • • • (•) (•)
Power driver
Switch
Low Side
(•) • • • • (•)
Switch
Bridge (•) • • • • • (•) (•)
symmetrical
communication
• • • • • • (•) (•)
Interface driver
(e.g. CAN,
LVDS)
asymmetrical
communication
• • • • • • (•) (•)
(e.g. LIN, Single
Wire CAN)
voltage regulator,
(•) • • (•) • (•) (•)
linear
voltage regulator,
(•) • (•) • (•) • (•) (•) (•)
switch mode
ASICs any combination
• = typical configuration
(•) = additional or alternative configuration
Table 1: Matrix showing which typical IC function module is integrated in several well known
IC’s.
13
SPLITTING IC S INTO IC FUNCTION MODULES
5.2 Example of an IC built up with IC function modules
Port Module Supply Module
Reginal I/O
Input Supply
Clock
input Flash / EPROM Type of memory
Port Supply Module
Digital Logic Analog
Port Module Fixed Function Unit: Fixed Function Unit:
DATA Program
Regional Clock Step up Voltage
Bus
Driver Converter
Core
Distribution Supply
Port Module Digital Logic Digital Logic

Fixed Function Unit: Fixed Function Unit:
Reginal Flash Memory
Data/Adress
Input Programming
Registers
ADDRESS Port Digital Logic Digital Logic Supply Module

Bus Fixed Function Unit: Fixed Function Unit:
Port Module Core
Memory (RAM/ Address
Reginal ROM) Arrays selection logic Supply
Input
Supply Module
Supply Module
I/O Port Module
I/O
Supply Reginal
Supply
Input
Selection
Signals
Figure 2, Example of a Memory IC built up with the IC function modules
14
T E ST D EF INIT ION S
6. Test definitions
6.1 Test methods

Conducted test methods
The conducted tests have to be performed for all ICs.
Test type Coupling Method Method name Reference

Conducted 150 Ω / 1 Ω
Direct coupling via 150 Ω / 1 Ω network IEC61967-4
Emission method
Conducted Direct RF-power injection via DC block Direct Power
IEC62132-4
Immunity capacitor Injection (DPI)
Table 2: Conducted test methods
Radiated test methods
The radiated tests have to be performed only for dedicated ICs.
Test type Coupling Method Method name Reference

Radiated TEM-cell
E- and H-field radiation of entire IC IEC61967-2
Emission method
Radiated TEM-cell
E- and H-field radiation on entire IC IEC62132-2
Immunity method
Table 3: Radiated test methods
6.2 Test parameters
Test conditions
Environment: Temperature 23°C +/-5°C
Supply: nominal Voltage +/- 5%
Emission bandwidths and frequency step sizes related to frequency ranges

For all measurements the noise floor must be minimum 6dB below the limit.
Receiver Analyzer
Method Frequency range
BW Step size RBW Sweep time**
150 kHz to 30 MHz 9 kHz 5 kHz 9/10kHz NP ⋅ LT ⋅ FR
1Ω
ts =
150 Ω
30 MHz to 200 MHz

TEM
120 kHz*** 60 kHz 100/120kHz*** RBW

* 200 MHz to 1000 MHz
*) Note: Upper frequency range of 1 Ω method is critical to handle, see layout recommendations
**) Note: NP=Number of Points; LT=Loop time or minimum period; FR=Frequency range
***) Note: Instead of 120 kHz / 100 kHz a bandwidth of 10 kHz / 9 kHz (with appropriate step size) can be used to reduce the
noise level in case of no difference of the disturbances.
Table 4: General test parameters: Emission

Detector type: Peak detector
Measurement time: The emission measurement time at one frequency shall be minimal the
period or test software loop duration.
15
Immunity test parameters to perform immunity tests

Frequency step sizes: Frequency step sizes related to frequency ranges are shown in
Table 5. Critical frequencies such as clock frequencies, system
frequencies of RF devices etc. should be tested using smaller
frequency steps agreed by the users of this procedure. Deviations
have to be stated in the test report.
Step size
Method Frequency range
linear
150 kHz to 1 MHz 100 kHz
1 MHz to 10 MHz 0.5 MHz
10 MHz to 100 MHz 1MHz
TEM
DPI

Table 5: General test parameters: Immunity
Dwell time: The dwell time at each frequency should be minimal 1000 ms. If
shorter or longer dwell times are used, the deviation has to be stated in the test report
DPI Immunity characteristic: The immunity diagram shows maximum RF forward power
without any monitored failure measured with increasing power up to the required limit.
TEM Immunity characteristic: The immunity diagram shows maximum field strength calculated
from the forward power (substitution method) without any monitored failures measured with
increasing field strength up to the required limit.
Modulation definition: Continuous Wave (CW) is mandatory.
An Amplitude Modulation (AM) test is optional and has to be

performed only on special request. Parameters: 1 kHz, 80%,
according ISO automotive specifications: reduced carrier for
same peak CW and AM (see Annex D).
same peak value
reduced
CW AM 80 %
carrier
reduced carrier
carrierAM = carrierCW / 1.8
am_mod_reduced_carrier.xls
Figure 3: General test parameters: Immunity, definition of AM modulation

carrier
16
6.3 DUT Monitoring

The pins to be monitored shall be specified in the dedicated IC EMC test specification.
Generally, all DUT functions, which are decided to be monitored, have to be checked. For
conducted immunity the DUT functions can be monitored direct or indirect at output ports. For
radiated immunity tests the distinction between direct and indirect monitoring is not possible.
All monitored signals shall be within the failure criteria of the IC EMC test specification.
Direct monitoring: The signal of the functional module at the injection point where the RF
power is applied is monitored.
Indirect monitoring: The signal of another functional module output port where the RF
power is not directly applied is monitored.
RF decoupling: RF filter are necessary to prevent the monitoring device from the
disturbance RF.
Monitoring device: The monitoring can be realized e.g. by a microcontroller (µC) test
application with a cycling test program, an
DUT Monitoring device
oscilloscope with a programmable signal
RF injection
failure
tolerance mask, a multimeter.
direct monitoring criteria
function
RF pass An example how the monitored signals
decoupling fail
can be combined to a logical sum "within
function
output signal
indirec t monitoring specification or out of specification” is

DUT within spec.
function
RF pass shown in Figure 4
OR or
output signal
function decoupling fail
one or more functions
out of spec.
function
output signal RF pass
function
decoupling fail
Figure 4: DUT monitoring for immunity tests
Failure criteria: For monitored signals failure criteria have to be defined in the
dedicated IC EMC test specification. A failure criterion is defined by its nominal signal values
and allowed tolerances. An example of a failure criteria table with typical signals is shown in
Table 6.
Monitored pin Failure criteria

Injection Point
Analogue output 2.5 Volts ± 0.2V
'Status' output digital signal '1'
… …
Table 6: Example of a failure criteria table
17
T EST AND MEA SU REM ENT GU ID E
7. Test and measurement selection guide
7.1 Workflow for selection and test

The following workflow shows in sequential order the steps required to generate a dedicated
IC EMC specification and to perform the EMC measurements. A template of the IC EMC
specification is provided in Chapter 12.
EMC Specification
Identification of all IC function modules and selection of the EMC relevant modules
(as defined in chapter 5)
Listing of all related pins and classification in local and global pins
Selection of pins to be measured (7.1.1) and monitored (6.3)
Selection of functional configuration, operation mode and software requirements

Selection of test- and measurement networks

Add radiated test methods, if criteria are met (see chapter 7.2)
selection of the test limits and monitoring definition

(as defined in chapter 11 and 6.3)
EMC - Test
Design of test schematic and board layout (see chapter 10)
Performing measurements according EMC specification (see chapter 7, 12)
Test Report (see chapter 13)
Figure 5: Workflow to perform IC EMC measurements
18
7.1.1 Conducted tests

The pin, test and measurement selection guide for conducted tests describes typical selection
criteria for the coupling and injection points to be tested, the configurations and the operating
functions of the IC under test for the characterization of its EMC behavior (relevant pins). The
dedicated selection, configuration and function have to be defined by the typical application of
the IC or by a dedicated IC EMC test specification.
7.1.2 Identification of IC function modules

To define the relevant IC function modules influencing the EMC behavior of an IC significantly
all integrated functions have to be classified according to the definitions in Chapter 6.
7.1.3 Pin Selection for Emission and Immunity

If an IC function module has a related IC pin it has to be checked if this pin is relevant for the
EMC behavior of the IC application according the following selection criteria. The
classifications of IC function modules and pins have to be listed.
Port modules
All global pins have to be measured.
At a global driver pins the emission and immunity of the direct pin function, the crosstalk
behavior pin to core and the crosstalk behavior port to pin can be measured.
At a global receiver pin only the crosstalk core to pin and port to pin can be measured.
Local pin measurements are not mandatory.
Local pin measurements are optional and should be performed only on special request or if no
pin could be defined as a global pin for measurements.
Supply modules
All supply pins have to be measured.
Core modules
The core cannot be measured directly only by crosstalk at global or local pins.
Oscillator modules
The emission of the oscillator should be measured only by crosstalk at global or local pins.
Immunity measurements can be performed optional directly at the oscillator.
19
7.1.4 IC function module and the coupling or injection points

Coupling and injection point
IC function module
Port Pin Supply Pin Core Oscillator (Pin)
Port module • •
Supply module •
Core module • •
Oscillator module • • (•)
Table 7: Conducted tests: Coupling and injection points
7.1.5 Selection guide emission
The following table provides the necessary details to apply the selection part of the workflow
for a dedicated IC. It starts with the selection of function modules with the related pin types,
defines the measurement networks to be connected and it shows the operation modes and the
expected coupling mechanisms in order to select the correct functional configuration and
software if necessary.
Coupling mechanism Functional Configuration

Coupling point
Without CPU With CPU
Direct Indirect
(see chapter 9.1) (see chapter 9.3)
Crosstalk port module to
Crosstalk core module
Measurement network
Crosstalk oscillator
IC function module
Operation mode *
Oscillator module
Functional signal
(see chapter 8)
Core module
Core module
Port module
Port module
module to
Oscillator
Pin type
to
T • PM1 C1-S3
Line Driver global 8.1.1 H • CM1 C4-S2
H • OM1 C6-S0
Line Receiver global 8.1.2 IA (•) CM1 C4-S2
T • PM3 C1-S3
Sym. Line Driver global 8.1.3 IA • CM1 C4-S2
IA • OM1 C6-S0
Sym. Line
global 8.1.4 IA (•) CM1 C4-S2
Receiver
8.1.5 A T • PM5 C1-S3
H, L • CM1 C4-S2
Regional Driver local H, L • OM1 C6-S0
C1-S2
8.1.5 B H, L • PM5
C1-S3
Regional Input local 8.1.6 IA (•) CM1 C4-S2
T • PM7 C1-S3
local,
High Side Driver 8.1.7 H • CM1 C4-S2
global
H • OM1 C6-S0
T • PM8 C1-S3
local,
Low Side Driver 8.1.8 H • CM1 C4-S2
global
H • OM1 C6-S0
H • SM1 C1-S3
local,
Supply 8.2 H • CM1 C4-S2
global
H • OM1 C6-S0
* Note: T = Toggle; H = static high potential, L = static low potential

IA = defined inactive, realized with internal or external pull up or pull down
(•) = Test is optional
Table 8: Selection guide emission
20
7.1.6 Selection guide immunity

The following table provides the necessary details to apply the selection part of the workflow
for a dedicated IC. It starts with the selection of function modules with the related pin types,
defines the measurement networks to be connected and it shows the operation modes in order
to select the correct functional configuration, the software if necessary and the kind of
monitoring.
Functional configuration
(see chapter 9.3)

Kind of
Injection point without CPU
monitoring
(see chapter 9.2)
with CPU
Port-, Core-, Oscillator
IC function module
Oscillator module
Operation mode*
(see chapter 8)
Test network
Core module
Port module
modules
Pin type
Indirect
Direct
T PM9 CM2 OM2 C10-S3 • •
Line Driver global 8.1.1 H PM9 CM2 OM2 C10-S3 • •
IA CM3 • •
A PM10 CM2 OM2 C10-S3 •
Line Receiver global 8.1.2
IA CM3 • •
T PM11 CM2 OM2 C10-S3 • •
Sym. Line Driver global 8.1.3 IA PM11 CM2 OM2 C10-S3 • •
IA CM3 • •
A PM12 CM2 OM2 C10-S3 • •
Sym. Line Receiver global 8.1.4
IA CM3 • •
T PM13 CM2 OM2 C10-S3 • •
(H) PM13 CM2 OM2 C10-S3 • •
Regional Driver local 8.1.5 A
(L) PM13 CM2 OM2 • •
IA CM3 • •
A PM14 CM2 OM2 C10-S3 • •
Regional Input local 8.1.6
IA CM3 • •
T PM15 CM2 OM2 C10-S3 • •
local, (H) PM15 CM2 OM2 C10-S3 • •
High Side Driver 8.1.7
global (L) PM15 CM2 OM2 C10-S3 • •
IA CM3 • •
T PM16 CM2 OM2 C10-S3 • •
local, (H) PM16 CM2 OM2 C10-S3 • •
Low Side Driver 8.1.8
global (L) PM16 CM2 OM2 C10-S3 • •
IA CM3 • •
local, H SM2 CM2 OM2 C10-S3 • •
Supply 8.2
global H SM2 CM3 • •
Oscillator local 8.4 T PM9 CM2 C10-S3 • •
A = defined active; IA = defined inactive, realized with internal or external pull up or pull down
( ) = Test is optional
Table 9, Selection guide immunity
21
7.2 Radiated tests

7.2.1 Criteria for performing radiated Emission and Immunity Tests
Emission:
• the IC has a CPU, or
• the IC has a digital logic FFU or an oscillator module with an operating frequency higher
than 10MHz and a package diagonal dimension greater than 25mm
Immunity:
• the IC has an analogue FFU as sensing element working with electrical or magnetic
fields, or
• the IC has an analogue or digital FFU with charge coupled devices (CCD) for filtering
7.2.2 Selection guide emission

Coupling structure Test setup
without CPU with CPU
entire IC chapter 8.6 CM1 C1-S2
Table 10, Selection guide emission
7.2.3 Selection guide immunity
Injection structure Test setup
without CPU with CPU
CM2 C10-S3
entire IC chapter 8.6
CM3 C11-S3
Table 11, Selection guide immunity
22
T E ST AND MEA SU RM ENT N ET WO RK S
8. Test and measurement networks

This chapter describes the coupling, injection and monitoring networks for the emission
measurements and immunity tests. All pins not used for emission measurement, immunity test
or monitoring have to be set in a defined state and configuration according to the IC data
sheet and documented in the test report. The electrical characteristics (power dissipation,
voltage, current, frequency properties) of the passive components on the test PCB have to
meet the functional and RF requirements.
23
8.1 Port module

8.1.1 Line Driver
For line drivers type LIN refer to specification 'EMC-Evaluation of LIN-Transceivers' [9]
(Ztrace = 50 Ω)
(Ztrace = 50 Ω) RAn
Line Driver
Line Driver
CBn
IC IC
Core
Core
R1 CB2
RA2
C1 CB1
R2 RA1
© 2007 BISS R2
© 2007 BISS
Configuration A: Single Line Driver port Configuration B: Multiple Line Driver port*
*) Use circuit B, if more than one driver should be tested simultaneously (means: all driver are active) of a multiple Line Driver port.
Emission setup component variation

R1 120 Ω
R2 51 Ω
C1 6.8 nF or less as max. load capacitance according IC data sheet
RA1=
RA ± 5% = 120Ω ⋅ n n = number of Line Drivers
RA2=..=
RAn Select a resistor according resistor standard set within tolerance of 5%
CB1= C1
CB2=..=
CB ± 5% = n = number of Line Drivers
n
CBn Select a capacitor according capacitor standard set within tolerance of 5%
Immunity setup component variation

R1 0 Ω as default, up to 100 Ω for load current limitation according data sheet
R2 open
RA1=
RA ± 5% = R1 ⋅ n n = number of Line Drivers
RA2=..=
CB1= C1
CB2=..=
n
Table 12: Emission and immunity setup for IC module line driver
24
8.1.2 Line Receiver

For line receivers type LIN refer to specification 'EMC-Evaluation of LIN-Transceivers' [9]
(Ztrace = 50 Ω)
Decoupling Device
RAn
Line Receiver
CBn
Zdd IC
Input Signal
Core
Cdd
Line Receiver
(Ztrace = 50 Ω) CB2
C RA2
Core
R1 CB1
C2
RA1
R2
R2
© 2007 BISS
© 2007 BISS
Configuration A: Single Line Receiver port Configuration B: Multiple Line Receiver port*
*) Use circuit B, if more than one driver are tested simultaneously of a multiple Line Receiver port.

For receiver ports emission tests are not mandatory

R2 open
Zdd > 400 Ω
Cdd 10 nF or acc. max. frequency of input signal
RA1=
RA ± 5% = 120Ω ⋅ n n = number of Line Drivers
RA2=..=
CB1= C1
CB2=..=
n
Table 13: Immunity setup for IC module line receiver
25
8.1.3 Symmetrical Line Driver

For symmetrical line drivers type CAN refer to specification 'EMC-Evaluation of
CAN-Transceivers' [8]
(Ztrace = 50 Ω)
Symmetrical
Line Driver
IC RA
CB
Core
RB
RA
CB
R2
© 2007 BISS
Setup component variation

Bus system type
Item Value
with separate termination1 with termination
RB acc. Bus specification open •

RA 240 Ω Note: : the resistors shall be matched with tolerance better than 0.1%
R2 51 Ω
6.8 nF or max. load capacitance according IC data sheet
CB
Note: the capacitors shall be matched with tolerance better than 1%

0 Ω as default, up to 100 Ω for load current limitation according data sheet
RA
Note: the resistors shall be matched with tolerance better than 0.1%
R2 open
6.8 nF or less as max. load capacitance according IC data sheet
CB
Table 14: Emission and immunity setup for IC module symmetrical line driver
1 Termination not part of the test network, but may be needed for the symmetrical line driver
26
8.1.4 Symmetrical Line Receiver

For symmetrical line receivers type CAN refer to specification 'EMC-Evaluation of CAN-
Transceivers' [8]
(Ztrace = 50 Ω)
Line Receiver
Symmetrical
IC RA
CB
Core
RB
RA
CB
R2
© 2007 BISS

Bus system type
Item Value
with separate termination2 with termination
RB acc. Bus specification open •

For symmetrical line receiver ports emission tests are not mandatory

0 Ω as default, up to 100 Ω for load current limitation according data sheet
RA
Note: the resistors shall be matched with tolerance better than 0.1%
R2 open
6.8 nF or less as max. load capacitance according IC data sheet
CB
Table 15: Immunity setup for IC module symmetrical line driver
2 Termination not part of the test network, but may be needed for the symmetrical line receiver
27
8.1.5 Regional Driver

(Ztrace = 50 Ω)
Vcc
R1 RPullup/Pulldown (Ztrace = 50 Ω)
RPullup VDD/ GND
Regional Driver
C1 C1
Regional Ports
R2
IC R1
Core
VDD/ GND
Core
1 (Ztrace = 50 Ω)
RPulldown R3 R2
VDD/ GND
49 Ω C2
R4
1Ω
CLOAD
Z=f(Cload, RPullup/Pulldown) © 2007 BISS
© 2007 BISS 1 Ω Probe 2
Configuration A Configuration B: Set up for Crosstalk measurement pin to pin
General setup component variation

Digital signal: according IC data sheet (typical value), if it is needed for
RPullup external pull up (default 3300 Ω)
Analog signal: signal connection to functional required circuit
RPulldown according IC data sheet (typical value)
Cload max. load capacitance according IC data sheet
or
Z=f(Cload, real loads (e.g. memory) or passive substitution networks according IC data or
RPullup/Pulldown) application sheet
Emission setup component
R1 120 Ω
R2 51 Ω
Test 1 RPullup-down ≤ 30 Ω or DC mode
network 2 RPullup-down > 30 Ω
Immunity setup component

R2 open
Table 16: Emission and immunity setup for IC module regional driver
28
8.1.6 Regional Input
Decoupling Device
Zdd
Input Signal
Regional Input
(Ztrace = 50 Ω)
Cdd
IC
Core
R1
C2
R2
© 2007 BISS

For input ports emission tests are not mandatory

C1 6.8 nF or less as max. load capacitance according IC data sheet)
Zdd > 400 Ω
Cdd 10 nF or acc. max. frequency of input signal
Table 17: Immunity setup for IC module regional input
29
8.1.7 High Side driver

• Emission: In addition to IEC61967-4, the impedance determining 150 Ω network and the
load impedance are decoupled by a 5 µH coil (L BAN ), to get results independent from the
load impedance.
• Immunity: In addition to IEC62132-4, a broadband artificial network (BAN) consisting of a

5 µH coil (LBAN ) and a 150 Ω matching network (R BAN , C BAN ) for impedance fixing is
added.
(Ztrace = 50 Ω)
supply
R1
(Ztrace = 150 Ω) C1
High Side
IC output R2
Driver
Core
LBAN 1
reference
RLoad
RBAN
C2
CBAN
© 2007 BISS
Configuration high side driver / linear voltage regulator
1 Decoupling and coupling network 2 decoupling network

(Ztrace = 50 Ω)
supply
R1
(Ztrace = 150 Ω) C1
High Side
IC output R2
Driver
Core
L1 LBAN 1
reference
RLoad
RBAN 49 Ω
D1
C2
1Ω
CBAN
© 2007 BISS 1 Ω Probe 2
Configuration switched mode power supply
30

Circuit type
Item Value linear voltage switched mode power
high side driver
regulator supply (Buck converter)
LBAN 5 µH independent of load current (no saturation effects)
L1 acc. IC data sheet shorted shorted •
D1 acc. IC data sheet open open •
C2 acc. IC data sheet open • •
∆T
I mes =
RLoad According Imes* Rth ⋅ Ron,150°C Imes = 80% of Inom Imes = 80% of Inom
(∆T = 65 K, Imes ≤ 10 A)
*) The IC dissipation power Pdissipation is basically limited by Rth of the housing and the maximum temperature Tmax of the
semiconductor at a maximum ambient temperature Tamb according data sheet. With the definitions Tmax = 150°C at
Tamp = 85°C a ∆T = 65K is given. The typical dissipation power is additionally given by Ron,150*C and a typical load
current ILoad: Pdissipation = I Load 2 ⋅ Ron,150°C and ∆T = Pdissipation ⋅ Rth .

R1 120 Ω • • •
R2 51 Ω • • •
C1 6.8 nF • • •
Test 1 RLoad ≤ 30 Ω or DC mode • •
network 2 RLoad > 30 Ω open open
RBAN 150 Ω open open open
CBAN 6.8 nF open open open

R2 open
RBAN 150 Ω • • •
CBAN 6.8 nF • • •
Table 18: Emission and immunity setup for IC module high side driver
31
8.1.8 Low Side driver

• Emission: In addition to IEC61967-4, the impedance determining 150 Ω network and the
load impedance are decoupled by a 5 µH coil (LBAN), to get results independent from the
load impedance.
• Immunity: In addition to IEC62132-4, a broadband artificial network (BAN) consisting of a

5 µH coil (LBAN) and a 150 Ω matching network (RBAN , CBAN) for impedance fixing is
added.
VSupply
1 Decoupling and coupling network
2 1Ω decoupling network
RLoad,1
supply
LBAN1 (Ztrace = 50 Ω)
(Ztrace = 150 Ω)
Low Side
output
Driver
Core
R1
C1
reference R2
49 Ω
1
RBAN1
1Ω
CBAN1
1 Ω Probe 2 © 2007 BISS
Configuration Low Side Driver
VSupply (Ztrace = 150 Ω) (Ztrace = 50 Ω)
R1
LBAN1 C1
R2
supply
1
C3 L1 (Ztrace = 150 Ω) (Ztrace = 50 Ω)
Low Side
C output
Driver
Core
R3
D1 LBAN2 C2
reference R4
C4 RLoad,2
RBAN1 1
RBAN2
CBAN1 CBAN2
© 2007 BISS
Configuration switched mode power supply
32

Circuit type
Item Value switched mode power supply
Low Side Driver
(Boost converter)
L1 acc. IC data sheet shorted •
LBAN1 5 µH independent of load current (no saturation effects)
LBAN2 5 µH shorted •
D1 acc. IC data sheet shorted •
C3 acc. IC data sheet open •
C4 acc. IC data sheet open •
∆T
I mes =
RLoad,1 According Imes* Rth ⋅ Ron ,150°C shorted
(∆T = 65 K, Imes ≤ 10 A)
RLoad,2 According Imes Imes = 80% of Inom
*) The IC dissipation power Pdissipation is basically limited by Rth of the housing and the maximum temperature Tmax of the
semiconductor at a maximum ambient temperature Tamb according data sheet. With the definitions Tmax = 150°C at
Tamp = 85°C a ∆T = 65K is given. The typical dissipation power is additionally given by Ron,150*C and a typical load current
ILoad: Pdissipation = I Load 2 ⋅ Ron,150°C and ∆T = Pdissipation ⋅ Rth .

R1, R3 120 Ω • •
R2, R4 51 Ω • •
C1, C2 6.8 nF • •
1 RLoad ≤ 30 Ω or DC mode •
Test network
2 RLoad > 30 Ω open
RBAN1, RBAN2 150 Ω open open
CBAN1, CBAN2 6.8 nF open open

R1, R3 0 Ω as default, up to 100 Ω for load current limitation according data sheet
R2, R4 open
C1, C2 6.8 nF or less as max. load capacitance according IC data sheet
RBAN1, RBAN2 150 Ω • •
CBAN1, CBAN2 6.8 nF • •
Table 19: Emission and immunity setup for IC module low side driver
33
8.2 Supply module

Emission: In addition to IEC61967-4, the impedance determining 150 Ω network and the load
impedance are decoupled by a 5 µH coil (L BAN ), to get results independent from the load
impedance.
Immunity: In addition to IEC62132-4, a broadband artificial network (BAN) consisting of a 5 µH

coil (LBAN ) and a 150 Ω matching network (RBAN , C BAN ) for impedance fixing is added.
Vsupply
LBAN1 © 2007 BISS Vsupply(1) Vsupply(x) (Ztrace = 50 Ω)

(Ztrace = 50 Ω)
VS1 LBAN1 LBANx R1
R1
Function module supply
C1
CD1 R2
Function module

C1 VS1
VGND1 R2 RBAN1
Function module
VS2..n
CD1
IC VGND1 (Ztrace = 50 Ω)
VSx RBAN1 VGND2..n
CBAN1 R3
VSx
C2
VGNDx CBAN1 VGNDx CDX RBANx R4
© 2007 BISS
CBANx
Configuration A: All supplies combined Configuration B: Supplies partly combined
Vsupply(1) Vsupply(X)
© 2007 BISS
Vsupply(1) Vsupply(x) (Ztrace = 50 Ω) LBAN1 LBANX
© 2007 BISS
LBAN1 LBANx R1 VS1
C1
R2 CD1 CDX
Function module
VS1
RBAN1 VGND1
Function module
CD1 IC 49 Ω
IC VGND1 (Ztrace = 50 Ω)
1Ω
VSx
CBAN1 R3
VSx
C2
VGNDx CDX RBANx R4 VGNDx 1 Ω Probe
CBANx
Configuration C: All supplies separated Configuration D: All supplies combined 1Ω method

CD1…CDx Supply Decoupling Capacitor acc. IC data sheet
LBAN1...LBANx 5 µH independent of load current (no saturation effects)

R1, R3 120 Ω
R2, R4 51 Ω

R1, R3 0 Ω as default, up to 100 Ω for load current limitation according data sheet
R2, R4 open
RBAN1…RBANx 150 Ω
CBAN1…CBANx 6.8 nF
Table 20: Emission and immunity setup for IC module supply
34
8.3 Core module

The conducted emission and immunity of the core module cannot be measured directly. All
emission or immunity tests shall be performed by using cross talk effects between
• core and supply
• core and port
• core and oscillator
8.4 Oscillator module

The emission of the oscillator should be measured only by crosstalk at global or local pins.
Immunity measurements can be performed optional directly at the oscillator.
(Ztrace = 50Ω)
JMP1
Output
R1 R3
Oscillator
IC C1
Core
quartz
(Ztrace = 50Ω)
Input
JMP2
R2 R4
C2
© 2007 BISS

R1, R2 0Ω
C1, C2 Oscillator capacitors: 33 pF or according data sheet
JMP1, JMP2 Jump plug (50 Ω) in case of no injection (immunity test)
R3, R4 50 Ω

For oscillator module emission tests are not required

JMP1, JMP2 Jump plug (50 Ω) connected to the not used injection point3
Table 21: Immunity setup for IC module oscillator
3 The internal impedance of the connected RF system substitutes the 50 Ω of the jumper plug.
35
8.5 Signal decoupling- and monitoring setup

The signal decoupling- and monitoring setup with or without external filter elements should not
affect the functional signal of the function module and not reduce the RF power at the
monitored pin. It is recommended that the impedance of the filter is higher than 400 Ω in the
test frequency range. An example for filter definition is shown in Figure 6.
supply
to supply network
in-/ 2
Port/Supply/
Oscillatore
IC output
Module
to load network /
Core
from signal source
1
reference
R1
Ulowpass,in Ulowpass, out
C1
© 2007 BISS
Configuration 1: Monitoring network at input or output Configuration 2: Monitoring network supply
Figure 6, General setup for a decoupling network for monitoring
Base of calculation:
U lowpass ,out 1
Transfer ratio: a= =
U lowpass ,in 1 + j 2πfR1 ⋅ C1
Magnitude of the transfer ratio in dB

U lowpass ,out 1
a = = 20 ⋅ log{ }
U lowpass ,in 1 + 4π f R1 C1
2 2 2 2
Limit for the magnitude of the transfer ratio < -20 dB, requires R 1 > 400 Ω in the test frequency
range
Note: Reflection coefficient for R1 ≥ 400 Ω in a 50 Ω system ≥ 0.8
36
-10
R=400Ohm, C=0.5nF
-20 R=400Ohm, C=10nF
R=1kOhm, C=1nF
R=6.8kOhm, C=2nF
transfer ratio / dB -30 R=10kOhm, C=6.8nF
-40
-50
-60
-70
-80
transfer function chart for examples for different
values of R1, C1
-90
for direct and indirect monitoring
-100
0,01 0,1 1 10 100 1000
frequency f / MHz
Figure 7, Decoupling network for monitoring: transfer function charts for low pass circuitry
examples
37
8.6 Entire IC
The measurement of radiated electromagnetic fields and the immunity against electromagnetic
fields are measured according [2], [6] with the (G)TEM cell.
With the (G)TEM Cell the field coupling between the IC structure and the (G)TEM cell septum
is measured. Therefore the IC is mounted on one side of the test board, which is oriented to
the septum of the (G)TEM cell. All the other circuit elements are located on the other side of
the test board and therefore outside of the (G)TEM Cell.
(G)TEM cell measurements have to be performed in minimum two orientations with 90°
difference in the x- and y- plane. The data sets shall be documented separately for each
direction.
Direction X Direction Y
Pin 1
Pin 1
© 2007 BISS © 2007 BISS
Figure 8: Example of "Direction X" and "Direction Y" of TEM cell test PCB
38
FU NT IONAL CO NFIG URAT ION S AN D O PERAT ING MOD ES
9. Functional Configurations and Operating Modes

The functional configuration of the FFUs describes the operation of the sources and sinks in a
FFU during the emission measurement or immunity test period. The pin loading is given by the
test and measurement networks described in chapter 8. Any deviations of the functional or
hardware configuration have to be noted in the test report.
9.1 Emission test configuration for ICs without CPU

Line Driver
To measure the direct switching noise of a line driver the driver shall operate
with the maximum frequency and the shortest switching time as specified in the
IC Data Sheet. The duty cycle should be set to 50%. If there is a function
integrated to use EMC optimized operation modes they should be measured
additionally. If more than one driver is tested simultaneously all drivers have to
PM1 be controlled synchronously.
For core cross coupling noise measurement the line driver has to be set in a
permanent high state. This measurement should be performed only if a cross
coupling by internal periodical sources with frequencies above 1MHz is
expected.
LIN communication drivers have to be tested according to EMC-Evaluation of
LIN transceivers [9].
Line Receiver
To measure the core cross coupling emission at a line receiver the receiver has
to be set in the normal receiving mode. This measurement should be performed
PM2 only if a cross coupling by internal periodical sources with frequencies above
1MHz is expected.
Port modules
LIN communication receivers have to be tested according to EMC-Evaluation of

Symmetrical Line Drivers
To measure the direct switching noise of a symmetrical line driver the drivers
shall operate with the maximum frequency and the shortest switching time as
specified in the IC Data Sheet. The duty cycle should be set to 50%. If there is a
function integrated to use EMC optimized operation modes they should be
measured additionally.
PM3
For core cross coupling emission measurement the line driver has to be set in a
permanent high state. This measurement should be performed only if a cross
coupling by internal periodical sources with frequencies above 1MHz is
expected.
CAN symmetrical line drivers have to be tested according to specification EMC-
Evaluation of CAN-Transceivers [8].
To measure the core cross coupling emission of a symmetrical line receiver the
receiver has to be set in the normal receiving mode. This measurement should
PM4 be performed only if a cross coupling by internal periodical sources with
frequencies above 1MHz is expected.
CAN communication receivers have to be tested according to EMC-Evaluation of
CAN transceivers [8].
Table 22, Emission test configuration for ICs without CPU
Regional Driver
To measure the direct switching noise of a regional driver the driver shall operate
modules
Port
PM5 with the maximum frequency and the shortest switching time as specified in the
IC Data Sheet. The duty cycle should be set to 50%. If there is a function
integrated to use EMC optimized operation modes they should be measured
39
additionally.
For core cross coupling noise measurement the regional driver has to be set in a
permanent high state to measure effects caused by internal periodical sources.
This measurement should be performed only if a cross coupling by internal
periodical sources with frequencies above 1MHz is expected.
To measure the pin to pin cross coupling noise caused by the neighborhood pins
the measured pin shall be set at high level and the neighborhood pins shall
operate with the maximum frequency and the shortest switching time as specified
in the IC Data Sheet. The duty cycle should be set to 50%.
Regional Input
For core cross coupling noise measurement the regional input shall stay in the
PM6 default state to measure effects caused by internal periodical sources. This
measurement should be performed only if a cross coupling by internal periodical
sources with frequencies above 1MHz is expected.
High Side driver
To measure the direct switching noise of a high side driver the driver shall
operate with the maximum frequency and the shortest switching time as specified
in the IC Data Sheet. The switching time should take less than 1% of the
switching period. The duty cycle should be set to 50%. If there is a function
PM7 integrated to use EMC optimized operation modes they should be measured
additionally with the same frequency as before.
For core cross coupling noise measurement the high side driver has to be set in
a permanent high state to measure effects caused by internal periodical sources.
Low Side driver
To measure the direct switching noise of a low side driver the driver shall operate
with the maximum frequency and the shortest switching time as specified in the
IC Data Sheet. The switching time should take less than 1% of the switching
period. The duty cycle should be set to 50%. If there is a function integrated to
PM8 use EMC optimized operation modes they should be measured additionally with
the same frequency as before.
For core cross coupling noise measurement the low side driver has to be set in a
permanent high state to measure effects caused by internal periodical sources.
To measure the emission on the supply the IC shall be powered as for normal
module
Supply
operation. All modules shall operate as defined for normal operation according
SM1
data sheet. All internal periodical sources shall be active and operate with
maximum frequency and power.
The core module shall operate as defined for normal IC function. All internal
module
Core
CM1 periodical sources shall be active and operate with maximum frequency and
power.
Oscillator
module
If an oscillator is used it has to be activated and operate with maximum

OM1
frequency and power as specified.
Table 22, Emission test configuration for ICs without CPU, continued
40
9.2 Immunity test configuration for ICs without CPU

Line Driver
To measure the immunity of a line driver two functional operation modes have to
be tested. In the first mode the driver shall operate with a typical frequency and
the typical switching time as specified in the IC data sheet. The duty cycle should
be set to 50%. In the second mode the driver has to be set in a permanent high
state.
For both operation modes the functionality shall be monitored directly at the line
PM9
driver pin and indirectly at another functional module output port of the IC to
detect cross coupling effects to other FFUs.
If there is a function integrated to use EMC optimized operation modes they
should be measured additionally. If more than one driver is tested simultaneously
all drivers have to be controlled synchronously.
LIN communication drivers have to be tested according to EMC-Evaluation of LIN
transceivers [9].
Line Receiver
To measure the immunity at a line receiver the receiver has to be set in the
normal receiving mode.
The monitoring shall be done indirectly at another FFU functional module output
PM10 port of the IC to detect cross coupling effects to other FFUs. There is no
possibility to distinguish between the immunity behavior of the receiver and cross
coupling effects into other FFUs.
Port Modules
LIN communication receivers have to be tested according to EMC-Evaluation of

Symmetrical Line Driver
To measure the immunity of a symmetrical line driver two functional operation
modes have to be tested. In the first mode the driver shall operate with a typical
frequency and the typical switching time as specified in the IC data sheet. The
duty cycle should be set to 50%. In the second mode the driver shall be
deactivated and stay in the default state.
PM11 For both operation modes the functionality shall be monitored directly at the line
driver pin and indirectly at another functional module output port of the IC to
should be measured additionally.
CAN communication drivers have to be tested according to EMC-Evaluation of
To measure the immunity of a symmetrical line receiver the receiver has to be
set in an active receiving mode.
The monitoring shall be done indirectly at another functional module output port
PM12 of the IC to detect cross coupling effects to other FFUs. There is no possibility to
distinguish between the immunity behavior of the receiver and cross coupling
effects into other FFUs.
CAN communication receivers have to be tested according to EMC-Evaluation of
Table 23, Immunity test configuration for ICs without CPU
41
Regional Driver
To measure the immunity of a regional driver three functional operation modes
are possible. The test shall be performed at least in the toggling mode with a
typical frequency and the typical switching time as specified in the IC Data Sheet.
The duty cycle should be set to 50%. Optionally the driver can be tested in a
PM13 permanent High state and/or Low state.
For all operation modes the functionality shall be monitored directly at the
regional driver pin and indirectly at another functional module output port of the
IC to detect cross coupling effects to other FFUs.
should be tested additionally.
Regional Input
To measure the immunity of a regional input the input has to be set in an active
mode.
PM14 The monitoring shall be done indirectly at another functional module output port
of the IC to detect cross coupling effects to other FFUs. There is no possibility to
distinguish between the immunity behavior of the input and cross coupling effects
into other FFUs.
Port Modules
High Side Driver

To measure the immunity of a High Side driver three functional operation modes
For all operation modes the functionality shall be monitored directly at the High
Side driver pin and indirectly at another functional module output port of the IC to
Low Side Driver
To measure the immunity of a Low Side driver three functional operation modes
For all operation modes the functionality shall be monitored directly at the Low
Side driver pin and indirectly at another functional module output port of the IC to
To measure the immunity of the supply the IC shall be powered as for normal
operation. All modules shall operate as defined for normal operation according
module
SM2 data sheet. All internal periodical sources shall be active and operate with
Supply
maximum frequency and power.

The monitoring shall be done indirectly at the supplied FFUs of the IC.
Table 23, Immunity test configuration for ICs without CPU, continued.
42
Core active mode

CM2 The core module shall operate as defined for normal IC function. All internal
Core module
functions shall be active and operate with typical frequency and power.
Core sleep modes
CM3 If it is possible to set the IC in other modes different to the normal mode such as
sleep mode, standby mode etc. they should be tested additionally.
Oscillator
If an oscillator is used it has to be activated and operate with typical frequency

module
OM2
and power as specified.
Table 23, Immunity test configuration for ICs without CPU, continued.
43
9.3 Emission test configuration for ICs with CPU

9.3.1 Test initialization software module for cores containing a CPU
Configuration Software
Module
Description and definition of test initialization software module
Description
Number
Name
Short System clock: - frequency = fmax

CPU: - active
FFUs: - all Fixed-function Units active, if
available: system clock output active
Active ports: - all multifunction ports switched to FFU
function
‘Worst case’ setting
- fastest slew rate of drivers

Reference
Inactive Ports: - all other ports

C1 Memory access: - choose the memory access for the loop
software module with highest emission
potential available, for example:
- synchronous access from external
memory (burst mode)
- asynchronous access from external
memory
- internal access from on-chip
memory
System clock: - frequency = fmax
CPU: - active
synchronous bus access/
Program execution with
FFUs: - all Fixed-function Units inactive, except

the memory interface
system clock
Bus mode
Active ports: - buses

C2 - bus clock (system clock output active)
1

Memory access: - memory access for the loop software
module: synchronous access from
external memory (burst mode)
Table 24, Test initialization software module for cores containing a CPU
44

CPU: - active
asynchronous bus access/

Program execution with
the memory interface
system clock
Active ports: - buses
C3 - fastest slew rate of drivers
2
- bus clock (System clock output inactive)
module: asynchronous access from
external memory
On-chip execution without
CPU: - active
system clock output
FFUs: - all Fixed-function Units inactive

Active ports: - none
C4 Inactive Ports: - all ports (Buses and all other ports)
3
- bus clock (System clock output inactive)

module:
internal access from on-chip memory
CPU: - active
the FFU corresponding to a tested driver
(if system clock output is available,
its test is required)
Active ports: - driver slew rate switched to
I. Required: fastest slew rate
Driver slew rate test
II. Optional: slower slew rates

Driver
C5 Memory access: - choose the memory access for the loop

software module with lowest emission
potential (low, medium, high) available,
for example:
low internal access from on-
chip memory
medium asynchronous access from
external memory
high synchronous access from
external memory (burst
mode)
Table 24, Test initialization software module for cores containing a CPU, continued.
45

CPU: - inactive ('wait' mode, 'hold' mode), if
Idle (Oscillator) Mode

available
Oscillator
FFUs: - all Fixed-function Units functionally
C6 inactive and unclocked
Inactive Ports: - all ports
module: none
- maximum clock tree frequency in clock
Active Clock Tree Mode
tree distribution
Clock Tree
available
C7 FFUs: - all Fixed-function Units clocked, but
functionally inactive
module: none
CPU: - minimum required activity
the FFU under investigation
Active ports: - controlled ports by FFU under
investigation
Test single FFU
Memory access: - choose the memory access for the loop

Single FFU
software module with lowest emission

C8
potential (low, medium, high) available,
for example:
low internal access from on-
chip memory
external memory
external memory (burst
mode)
System clock: - frequency < fmax
On-chip execution at
Reduced system
reduced system
frequency
frequency
C9
combined with Configuration Modules C1..C8
Notes: 1. The measurement should start after finishing the initialization.

. 2. This table may be extended by further tests agreed between the customer and IC supplier
Table 24, Test initialization software module for cores containing a CPU, continued.
46
9.3.2 Immunity test configuration for ICs with CPU

Configuration Software
Module
Description and definition of test initialization software module
Descrip-
Number
Name
Short
tion
System clock:
- frequency = fmax
- active CPU:
FFUs:
- all Fixed-function Units active, if
available: system clock output active
Active ports: - all multifunction ports switched to FFU
function
Monitor pin: - a pin of a non-multifunction port without
FFU function, toggle signal with fixed
relation to system clock (constant
Functional ‘Worst case’ setting
frequency), CPU-driven
Immunity Reference
Error detection: - all possible error detections should be

active (e.g. watchdog, oscillator loss of
C10 lock, internal/external bus errors / FFU-
errors, traps, interrupts)
- load/compare/store loop inside
internal/external memory
- each error case should stop the toggling
signal on the monitor pin
Memory access: - choose the memory access for the loop
software module with highest functional
potential (high, medium, low) available,
for example:
external memory (burst mode)
external memory
low internal access from on-chip
memory
System clock: - frequency = foscillator
Idle Mode (Oscillator test-mode)
available
FFUs: - all Fixed-function Units functionally
inactive and unclocked
Oscillator
OSC: - all different Oscillator-driver-settings

C11 must be tested on a typical crystal (e.g.
according data sheet like 4/16 MHz)
Active ports: - clock output or a toggling port for
monitoring
module: none
Notes: 1. The measurement shall start after finishing the initialization.
2. This table may be extended by further tests agreed between the customer and IC supplier
Table 25, Immunity test configuration for ICs with CPU
47
9.3.3 Test loop software module for cores containing a CPU

The test software should be developed with respect to the expected measuring time. The loop
time should not exceed 100 ms.
Loop Software module Description and definition of test loop

Number Short description software module
S0 Idle None
S1 Fastest instruction loop label: jump(unconditional) label
Copied data range is equal or more than 10%
of available RAM. Data pattern is alternating
$AA.. and $55.. (length depending on data bus
width) in consecutive RAM access. Source
memory area and destination memory area
shall differ by the maximum number of address
bits
Upper memory limit
101010101...
010101010...
10 % Upper
S2 RAM copy memory vector memory
-1 decrement area
memory vector
10 % Lower
+1 increment
memory
area
010101010...
101010101...
Lower memory limit
S3 Driver output action Toggling driver outputs

[IEC 61967-1, annex B]: "This simple routine
implements a counter function using a single 8-
bit port. Every 100 µs, the port output is
incremented or decremented. After 10 count
S4 IEC Increment cycles (256 ms) an LED output is
complemented. This will provide a blinking light
indication with a frequency of about 2 Hz. For
consistency, equivalent loop times shall be
maintained."
CPU runs at minimum required activity for FFU
controlling, target is autonomous running mode
S5 FFU dedicated software of the FFU under investigation.
All FFU parameters: Adjust to EMC worst case
condition
S6 Read Receiver/Input Read receiver/input register
Note: Take care of software loop times according emission measurement dwell time.
Table 26, Test loop software module for cores containing a CPU
48
T EST BOA RD
10. Test board

The minimum requirement for the test PCB is a two-layer board with a common ground plane
on the bottom side used as reference ground.
In general all ground areas have to be connected to a common ground system with low
impedance.
For conducted measurements the geometry of the board may have any rectangular or circular
shape. This is dependent on the IC specific application and necessary additional components,
measuring- and decoupling networks. The DUT and all mandatory components needed to
operate the DUT, as described in the data sheet or application note should be mounted onto
the topside of the test board. As much wiring as possible should be routed in the top layer.
The device under test should be placed in the centre of the PCB, while the needed matching
networks should be placed around this centre. The wiring between the IC pins and the
matching network should be as short as possible. A trace length equal to 1/20 of the shortest
wave length (1 GHz) applied is a reasonable target. The wiring of the outputs of the matching
networks should be designed to have a line impedance of 50 Ω connected with a RF-
connector (e.g. SMA or SMB) at the end. In case that the 1Ω -Method is used a socket for the
RF current probe should be used. The shield of the RF current probe tip shall be connected to
RF- peripheral ground by the socket, while the measured IC Pin is connected to the current
probe tip. The connection between the IC Pin and the probe tip should be as short as possible.
In any case the trace length should not exceed 15 mm (at 1 GHz upper frequency range limit).
In general the transfer characteristic of each RF measurement point at the test board including
all functional, decoupling and measuring components without the DUT shall be measured and
documented in the test report. The DUT has to be substituted by 50 Ω resistors to ground at
the DUT pin pads.
For radiated measurements the geometry of the board is given by the hole in the TEM cell
where the board has to fit in. To fulfill the requirements of the application on such a limited
board a more layer board should be used. In any case the DUT has to be mounted onto the
bottom side with the common ground plane.
In “Annex-A” some examples of board layouts for 150 Ω -, 1 Ω - , DPI- and TEM-cell testing
are shown.
49
I C E MC L IM IT S
11. “Preliminary” IC EMC limits for Automotive

All relevant pins of an IC shall be classified according to the limits given in the following chapters.
Mandatory components are regarded as part of the IC and shall be added for the test.
The currently defined limits are based on a small data base and must be updated if more
experience is collected. Therefore they are for orientation at the moment.
The limit classes are different depending on the requirements given by the application. The
application EMC effort is defined by the application itself, ECU housing, number of layers, filters
elements etc.
Limit class Description

I high application EMC effort
II medium application EMC effort
III low application EMC effort
C customer specific
C-BS customer specific: external bus systems
11.1 Emission
11.1.1 Emission level scheme
The following level scheme can be used to describe the emission of ICs in a simplified way.
84 A
1
78 B 2
3
72 C
4
66 D 5
6
60 E
7
54 F 8 a
[Voltage] dBµV
9 b
48 G c
10 d
e
42 H 11 f
g
12
36 I i h
13 k
30 K l
14 m
n
15
24 L po
16 q
18 M r
17 s
18 u t
12 N v
19 w
6 O x
y
z
0
0,01 0,1 1 10 100 1000
[frequency] MHz
Figure 9, Emission level scheme according IEC61967-2 and IEC61967-4

By selecting the right emission level and defining a limit class for a dedicated IC pin the
desired functionality and operation mode has to be considered.
Toggling digital data pins, periodically switching analogue power outputs etc. generate
switching harmonics as a matter of principle. This may violate emission requirements in terms
of standard limit classes but cannot be avoided by IC design measures for functional reasons.
50
I C E MC L IM IT S
The resulting spectrum can be calculated by Fourier transformation of the functional specified
signal waveform as described in Annex F. This calculated spectrum describes the limitation of
the minimal emission and has to be considered to define superimposed specific limits for
those pins.
11.1.2 General emission limit classes

150 Ω method 1 Ω method
Limit class TEM cell method
global local global local
I 8-H 6-F 10-K 8-H I
II 10-K 8-H 12-M 10-K L
III 12-M 10-K 14-O 12-M N
C customer specific
Table 27, General emission limit classes
51
I C E MC L IM IT S
Conducted emission 150Ω method limit line set for all IC function modules
102 102
96 96
90 90
6
84 84
78 78
8 8
72 72
66 66
[Voltage] dBµV
[Voltage] dBµV
10 10
60 60 Class I
F
54 54
12
48 Class I 48 Class II
H H
42 42
36 Class II 36 Class III
K K
30 30
24 24
M Class III
18 18
12 12
6 6
0.1 1 10 100 1000 0.1 1 10 100 1000
0,15 0,15
[frequency] MHz [frequency] MHz
Figure 10: Limit line set for global pins Figure 11: Limit line set for local pins
Conducted emission 1Ω method limit line set for all IC function modules
96 96
90 90
84 84
78 78
8
72 72
66 66
10 10
60 60
[Voltage] dBµV
[Voltage] dBµV
54 54
12 12
48 48
H Class I
42 42
14
36 36 K Class II
K Class I
30 30
24 Class II 24 Class III
M M
18 18
12 Class III 12
O
6 6
0 0
0.1 1 10 100 1000 0.1 1 10 100 1000
0,15 0,15
Radiated emission TEM cell method limit line set for dedicated IC types (see chapter 7.1.1)
84
78
72
66
60
54
[Voltage] dBµV
48
42 Class I
I
36
30 Class II
L
24
18 Class III
N
12
6
0
0,15
0,1 1 10 100 1000
[frequency] MHz
Figure 14: Limit line set for TEM cell
52
I C E MC L IM IT S
11.1.3 Dedicated emission limits for 'external digital bus systems'

Adapted limits C-BS for bus communication of microcontrollers with RAM or flash in configuration
C1 and software loop S2.
Background: The performance of current 'digital systems' built of IC types

microcontrollers, RAMs and flashes, connected via busses, leads to higher emission
values. To attend this technical phenomenon, other emission values are allowed for this
kind of IC type combination. In the case of applying such an IC type combination in an
application, all other IC types used in the same application shall fulfill the limit of the
agreed region.
90
80
0.15 MHz
69.31 dBµV
70
60
Figure 15,
[value] dBµV
100 MHz
50 45 dBµV
300 MHz
Conducted 10 MHz
39 dBµV
40
emission 150 Ω 45 dBµV
limit Port Pins 30

600 MHz
30 dBµV
20
10
0
0.15
0,1 1 10 100 1000
[frequency] MHz
90
80
70
0.15 MHz
59.3 dBµV
60
Figure 16,
[value] dBµV
50
Conducted 100 MHz
40 35 dBµV
emission 150 Ω 300 MHz
29 dBµV
10 MHz
limit Supply pins 30 35 dBµV
20
600 MHz
20 dBµV
10
0
0,1 0.15 1 10 100 1000
[frequency] MHz
90
80
70
60
[value] dBµV
50
Figure 17, 0.15 MHz 100 MHz
TEM cell limit 40 35 dBµV 35 dBµV 300 MHz
Microcontroller
29 dBµV
30
20
600 MHz
20 dBµV
10
0
0.15
0,1 1 10 100 1000
[frequency] MHz
53
I C E MC L IM IT S
11.2 Immunity
11.2.1 General immunity limit classes
DPI TEM
Immunity limit classes [forward power] dBm [E-field] V/m
global pin local pin entire IC
I 18 0 200
II 24 6 400
III 30 12 800
C customer specific
Table 28, General immunity limit classes
Conducted immunity DPI method limit line set for all IC function modules
42 42
39 39
36 36
33 30 dBm Class III 33
30 30
[foreward power] dBm
[foreward power] dBm
27 24 dBm Class II 27
24 24
21 21
18 dBm Class I
18 18
15 15 12 dBm Class III
12 12
9 9 6 dBm Class II
6 6
3 3 Class I
0 dBm
0 0
-3 -3
0,15 0,15
0,1 1 10 100 1000 0,1 1 10 100 1000
Radiated immunity TEM cell method limit line set for dedicated IC types (see chapter 7.2.1)
1000
900
Class III
800
700
600
[E-field] V/m
500
Class II
400
300
Class I
200
100
0
0,15
0,1 1 10 100 1000
[frequency] MHz
Figure 20: Limit line set for TEM cell
54
I C EMC SPEC IF ICA TIO N
12. IC EMC Specification

The IC EMC Specification contains the EMC requirements and the EMC Test Specification for
a dedicated IC. It is either provided by the customer or by the IC supplier. The IC EMC
Specification contains the pin selection, functional configuration, measurement method and
limits (EMC requirements) for emission and immunity tests as defined in Table 29 and Table
30. Additionally the test board’s schematic and special agreements may be included. An
example is given in Annex E.
Emission
Test method selection

Coupling point Coupling mechanism with limit
(Class I-III,C,C-BS)
Pin (if available)
Operation Mode*
core crosstalk
osc. crosstalk
port crosstalk
Configuration
IC function
Functional
Pin Type
(global/local)
module
150 Ω
direct
TEM
1Ω
Name
No.:
Function
Example:
System clock Regional
local C1-S2 T III
output driver
Regional
Data bus local C1-S2 T III
driver
Regional
Address bus local C1-S2 T III
driver
Regional
ALE signal pin local C1-S2 T III
driver
All Chip select Regional
local C1-S2 T III
(CS) driver
Regional
Read (R) local C1-S2 T III
driver
Regional
Write (W) local C1-S2 T III
driver
Table 29, Structure of an IC EMC specification, part emission
55
I C EMC SPEC IF ICA TIO N
Immunity
Injection point Monitoring Test method
Pin Monitoring pins
Functional Configuration
Operation Mode*
Failure criteria
(global/local)
TEM
DPI
Port IC function
Pin Type
Function
Function
module
Name
Name
No.
No.
CW AM CW AM
Example:
Regional C1-S2 A I/O Port 1 III
Reset local
Input C1-S2 A Reset 2 III
III
Regional CLK out or
PLL-freq1..x local C1-S2 A 1 III
Input toggling port
III

Table 30, Structure of an IC EMC specification, part immunity (1)
Failure criteria
No. Description Tolerance

1 Toggling port toggling, constant frequency
2 Voltage at pin as specified in data sheet
Table 31, Structure of an IC EMC specification, part immunity (2)
56
T EST R EPORT
13. Test report

Following items shall be part of the test report:
• Reference to used EMC specification
• Schematic diagram of test board
• Picture of test board layout or parts of it
• Transfer characteristics of RF coupling paths
• Functional configurations of FFUs and description of implemented software modules

for ICs with CPU
• Description of test equipment
• Description of monitoring points and failure criteria for immunity tests
• Description of any deviation from previously defined test parameters
• Result diagrams (Emission: scaled in dBµV and all limit lines, Immunity: scaled in
dBm for DPI or V/m for TEM with target value lines, as shown as figures in chapter
11)
57
CO PYR IGHTS AND L IAB IL IT Y
14. Copyrights and Liability
Copyrights:
§1 With respect to the Specification Document sent in the form of either paper or data, the
companies Bosch, Continental and Infineon provide this specification to their respective
business partners and any other third parties according to the following conditions. All
interested users may:
§1.1 use the Specification Document in terms of the specification for the compilation and
implementation of the IC Tests and incorporate the Specification Document into their
respective in-house specifications with the existing copyright notices;
§1.2 publish, subject to the protection of the copyright notices, the Specification
Documentation free of charge;
§1.3 revise or further develop the Specification Documentation. In this case, any changes have
to be made visible as such; and
§1.4 make the Specification Document available to their respective business partners (in the
form of paper or data) subject to the aforementioned conditions.
§2 Any user shall point out to its respective business partners or any interested third party
that the copyright notices which are found on the Specification Document and which exist
for the benefit of the Bosch, Continental and Infineon, may not be removed or modified by
such business partners or any other third party; this also applies in cases of revisions or
further developments thereto.
§3 Any user shall point out to its respective business partners or any interested third party
that utilization of the Specification Document by them or by their respective business
partners or any other third party on a remunerative basis is not permitted.
Liability:
§ 1 Bosch, Continental and Infineon are liable without limitation for deliberate acts and acts
committed with gross negligence.
§ 2 With the exception of injuries to life, body and health, Bosch, Continental and Infineon are
liable for acts committed with slight negligence only insofar as principal obligations with
regard to the providing of the Specification Document are infringed. Also, liability is
restricted to the typical and foreseeable damages.
§ 3 Liability for indirect and unforeseeable damages, for standstill of production and recovery
for loss of use, loss of data, lost profits as well as expenses incurred for development,
supplementary labour or product recall as well as pure economic loss due to third-party
claims are excluded in the event of slight negligence.
§ 4 Further liability in excess of what is specified herein is excluded regardless of the legal
nature of the claim asserted.
58
A NN E XES
15. Contacts and authors

The following table shows company contact persons listed in alphabetic order:
Name Company Email address

Continental Automotive GmbH
AQL RBG 42 michael.joester@continental-
Michael Joester
P.O. Box 10 09 43 corporation.com
93009 Regensburg
Automotive Power – EMC Center
Dr. Frank Klotz frank.klotz@infineon.com
ATV PTS PD EMC
81726 München
Robert Bosch GmbH
AE/EMC-G
Dr. Wolfgang Pfaff wolfgang.pfaff@de.bosch.com
P.O. Box 300240
70442 Stuttgart
Automotive Microcontrollers
Thomas Steinecke thomas.steinecke@infineon.com
ATV MC D IPI EMC
81726 München
Table 32, List of contact persons
The specification was created by a working group with experts and members of the german
national standardization organization DKE from Bosch, Infineon and SiemensVDO. The
Authors are listed in alphabetical order by Companies:
Robert Bosch GmbH:
Dr. Joerg Brueckner, Dr. Wolfgang Pfaff, Herman Roozenbeek, Andreas Rupp
Infineon Technologies AG:
Dr. Frank Klotz, Christoph Schulz-Linkholt, Thomas Steinecke, Markus Unger
Continental:
Michael Joester, Hartwig Reindl, Christian Roedig, Gerhard Schmid
59
A NN E XES
Annex A
Layout Recommendation,
(informative)
Several networks
Layout Example of 150 Ω networks on 2 layer and multi layer PCB
Signal or supply to IC pin Signal or supply to IC pin
50 Ω micro stripline 50 Ω micro stripline
length < λ/20 length < λ/20
= top layer = top layer

ZX ZX = 1st inner layer
R1 C1 = bottom layer circuit ground R1 C1 .
TEM cell RF ground plane .
120Ω 6.8nF 120Ω 6.8nF = other inner layer
IC IC .
51Ω 51Ω .
CX CX = bottom layer reserverd for
R2 R2 TEM cell RF ground plane
DUT on bottom side Components as close SMA or SMB connector DUT on bottom side Components as close SMA or SMB connector
together as possible on top side together as possible on top side
Conducted Emission Conducted Emission

configuration configuration
ZX ZX
R1 6.8 nF R1 6.8 nF
SMA or SMB SMA or SMB
IC-Pin IC-Pin
C1 connector C1 connector
120 Ω 120 Ω
CX R2 CX R2
51 Ω 51 Ω
ZX e.g.: 0 Ω for connection to circuit or ZX e.g.: 0 Ω for connection to circuit or

pullup resitor for input mode pullup resitor for input mode
CX e.g.: Output mode load capacitor or CX e.g.: Output mode load capacitor or
supply buffer capacitor supply buffer capacitor
150 Ω network on 2 layer PCB 150 Ω network on multi layer PCB
• The impedance of the signal island at the IC pin is not 150 Ω, but can be neglected as it is as small as possible.
Notes
: • This layout recommendation can be configured to perform Direct Power Injection (DPI) according IEC62132-4.
• The distance of the 50 Ω trace edges to the ground copper edges on the same layer should be minimum twice of the
distance between the 50 Ω trace and the ground plane underneath the trace.
Figure 21, Layout recommendation 150 Ω network
Layout Example of 1 Ω network on 2 layer and multi layer PCB

50 Ω micro stripline
length < λ/20
= top layer
.
. inner layers
= bottom layer circuit ground
IC TEM cell RF ground plane
DUT on bottom side

SMA or SMB connector
IC sum ground island on top side
Conducted emission
1 Ω method
VSupply Pin
VSupply Pin CDecoupling
CDecoupling
IC-ground-pin 1 Ω Probe
IC-ground-pin
IC-ground-pin
1Ω
Ground
island Signal
ground
Figure 22, Layout recommendation 1 Ω network
60
NOT ES
Layout Example of DPI network on 2 layer and multi layer PCB

Signal or supply to IC pin Signal or supply to IC pin
50 Ω micro stripline 50 Ω micro stripline
length < λ/20 length < λ/20
= top layer = top layer
ZX = bottom layer circuit ground ZX = 1st inner layer
R1 C1 R1 C1 .
TEM cell RF ground plane
.
0Ω 6.8nF 0Ω 6.8nF = other inner layer
IC IC .
.
CX R2 CX = bottom layer reserverd for
R2 TEM cell RF ground plane
DUT on bottom side Components as close SMA or SMB connector DUT on bottom side Components as close SMA or SMB connector
together as possible on top side together as possible on top side
Direct Power Injection Direct Power Injection

configuration configuration
ZX ZX
R1 6.8 nF R1 6.8 nF
SMA or SMB SMA or SMB
IC-Pin IC-Pin
C1 connector C1 connector
0Ω 0Ω
CX or value for CX or value for
current reduction current reduction
ZX e.g.: Inductance or resistor for supply/ ZX e.g.: Inductance or resistor for supply/
signal line/circuit decoupling signal line/circuit decoupling
CX e.g.: Output mode load capacitor or CX e.g.: Output mode load capacitor or
supply buffer capacitor supply buffer capacitor
DPI network on 2 layer PCB DPI network on multi layer PCB
• The impedance of signal island at the IC pin is not 50 Ω, but can be neglected as it is as small as possible.
Notes:
• This layout recommendation can be configured to perform Conducted Emissions according IEC61967-4.
• The distance of the 50 Ω trace edges to the ground copper edges on the same layer should be minimum twice of
the distance between the 50 Ω trace and the ground plane underneath the trace.
Figure 23, Layout recommendation DPI network
61
A NN E XES
Layout Example of a TEM cell test board

The layout requirements for a TEM cell test board are described in detail in [1] and [2].
GND-Vias
GND
DUT
GND Tin-coated
103,00 mm
GND-Vias are always plated through all layers and all

other Vias are partial plated or buried only.
Figure 24, TEM cell test PCB shape
62
NOT ES
Layout Example for Digital systems built with IC types microcontrollers,

RAMs
In the following figure a required 6 layer stack is shown used for digital systems built with IC
types microcontrollers, RAMs and flashes:
Component-side
1 Component Side 0.063 mm components + wiring
u-Via Insulation 0.250 mm
2 Inner 1 0.053 mm wiring
Insulation 0.200 mm
3 Inner 2 0.035 mm ground plane
Insulation 0.200 mm
4 Inner 3 0.035 mm empty (optional) plane
Insulation 0.200 mm
5 Inner 4 0.053 mm DUT-supplies only
Insulation
u-Via 0.250 mm
6 Solder Side 0.063 mm DUT and groundplane
DUT- or TEM-Side
µ-Via: hole diameter = 100 µm and pad diameter = 300 µm
Small Via: hole diameter = 250 µm and pad diameter = 500 µm
Standard Via: hole diameter = 300 µm and pad diameter = 800 µm
Min. trace width 160 µm and Cu-thickness 35 µm
Figure 25, Recommended layer stack up of a test board for digital systems built of IC
types microcontrollers, RAMs and flashes
Multi method test board
For combined test boards for radiated and conducted tests (conducted emission and DPI) the
conducted measurement points and adaptation networks with RF connectors at port pins and
supply lines should be realized on the component side of the PCB. Every port pin and every
independent power supply that has to be measured needs an adaptation network and a RF
connector (e.g. SMA or SMB). Add the conducted test method networks to this board
according the previous chapter.
63
A NN E XES
Digital system built with IC types Microcontrollers, RAM and Flash: PCB
requirements and some layout hints for combined radiated and conducted
methods test board.
Component side:
To prevent unwanted resonances in the supply system, the wiring recommendation of the different
PCB-layers should be followed. Every supply-island is connected with two SMB-jackets. One jacket
is used for measuring the supply voltage according to the 150 Ohm method in our example
BUVDD2V6 for the external-bus/Flash supply-island and BUVDD1V5 for the core supply-island.
The other jacket which is directly connected with the corresponding supply-island is used for
measuring the impedance of the supply-island and the transfer impedance between the supply-
islands. In our example BVDD2V6 for the external-bus/Flash supply-island and BVDD1V5 for the
core supply-island.
Figure 26, Component side
64
NOT ES
An integrated voltage regulator has to be placed on the test-board too. Separated supply-lines
to the different islands and component units should be used. Only plated-through holes
through all layers and no partial vias shall be used for ground connections. For all other
connections only partial vias are allowed. Bus wiring should be limited on component- and
innerlayer1 only. Any wiring between core decoupling capacitors at the component side should
be prevented.
Figure 27, Detail of component side layer
The supply-islands are connected by a special land to the supply-line at the component side,
which makes it possible to separate the island from the supply line very easily. Such a land is
shown below in a picture detail of the component side layer.
Inner layer 1 (i1):
The core supply-island and the core supply-line from the voltage regulator to the core-island
should be at layer i1 only. Above layer i1 should be no wiring of external address- data- and
bus control-signals
Figure 28, Inner layer 1
65
A NN E XES
Inner layer 2 (i2): (Ground layer)
Inner layer 2 should be a ground layer only without any exceptions. Ground vias are basically
connected with all layers as far as possible.
Inner layer 3:
The external-bus/Flash supply-island can be placed more favorable at the inner layer 3 as at
inner layer 4, because at i4 a little bit of wiring has to be done caused by the use of partial
vias.
66
NOT ES
Inner layer 4:
A minimum of wiring should be under the supply-island of i3. The wiring of the clock out signal
should be between two ground areas in this layer only. USB-Bus traces for communication
purposes are shown in this layer also.
Solder Side (SS):
Only absolute minimum of wiring should be performed at this layer. Only the DUT in our example a
microcontroller should be mounted at this layer.
Figure 32, Solder side
67
A NN E XES
Summary of the placement of components and wiring of the combined TEM cell/conducted
emission-Test board:
Component-side
Components +
Buswiring +
Mainwiring
I1- Buswiring +
Supply-Island for
Microcontroller +
Mainwiring
I2 - Groundplane only
I3 - Supply-Island
external Bus only
I4 - Clockout +
Communication with
Microcontroller
Solder Side-Ground +
Microcontroller
DUT-or TEM-side
Figure 33, Layer stack
68
NOT ES
Annex B
Test network modification
(emission, normative)
Calculation of new start frequency in case of modifying the coupling capacitor of the 150 Ω
measuring network
Base of calculation:
U highpass ,out Z in 1
transfer ratio highpass voltage divider a= = ; limit definition a −3 dB =
U highpass ,in Z out 2
. (A1)
Magnitude of transfer ratio of 150 Ω network, see Figure 34:
U highpass ,out (51Ω 50Ω)

a = = 20 ⋅ log ,
U highpass ,in 1
(120Ω + 51Ω 50Ω) + 2
4π f C
2 2 2
transfer ratio for: f → ∞ : a f →∞ = −15.2 dB (A2)
Equation for limit frequency (highpass -3dB point)
1
f −3dB MHz ≈ (A3)
844 Ω ⋅ C µF
-15
- 3 dB
-18
[|transfer ration|] dB
6.8 nF
1 nF
-21
100 pF
50 pF
120 Ω
Uin XC =
1
2πf
-24
51 Ω 50 Ω Uout
-27
0,1 1 10 100 1000
[frequency] MHz
Figure 34, 150 Ω network, attenuation chart of some example capacitor values
69
A NN E XES
Table of useful capacitor values:
Value of 150 Ω network DC block capacitor Lower limit frequency (-3 dB)
6.8 nF * 174 kHz
1 nF 1.2 MHz
100 pF 12 MHz
68 pF 17 MHz
50 pF 24 MHz
33 pF 36 MHz
*) Note: (default value according IEC standard)
Table 33, Limit frequencies of modified DC block capacitor values in 150 Ω network
70
NOT ES
Annex C
Trace impedance calculation
(informative)
Equations for calculating Micro Stripline impedances (informative)
Source of this annex part: Hall/Hall/McCall, 'High Speed Digital System Design',
issue 2000, ISBN 0-471-36090-2
"These equations should be used only when a field simulator is not available. A field simulator
is required for the most accurate results."
Microstrip
87 ⎛ 5.98 H ⎞
Z0 ≈ ln⎜ ⎟ (B1)
ε r + 1.41 ⎝ 0.8W + T ⎠
W
Valid when 0.1 < < 2.0 and 1 < ε r < 15
H
W
T
H εr
Figure 35, Micro strip line
Note: The distance of the 50 Ω trace edges to the ground copper edges on the same layer
should be minimum twice of the distance H between the 50 Ω trace and the ground
plane underneath the trace.
Please consider furthermore that in case of ground copper edges on the same layer
the impedance is influenced if varnish is on the PCB surface, too.
Symmetric Stripline
60 ⎛ 4H ⎞
Z 0, sym ≈ ln⎜⎜ ⎟ (B2)
ε r ⎝ 0.67π (T + 0.8W ) ⎟⎠
W T
Valid when < 0.35 and < 0.25
H H
W
H T
εr
Figure 36, Symmetric stripline
71
A NN E XES
Offset Stripline
"The impedance for an offset stripline is calculated from the results of the symmetrical strip
line formulas. The reader should note that this formula is an approximation and the accuracy
of the results should be treated as such. For more accurate results, use a filed solver."
Z 0 sym (2 A, W , T , ε r ) ⋅ Z 0 sym (2 B,W , T , ε r )

Z 0offset = 2 (B3)
Z 0 sym (2 A,W , T , ε r ) + Z 0 sym (2 B,W , T , ε r )
B W
T
A εr
Figure 37, Offset Stripline
Note: The distance of the 50 Ω trace edges to the ground copper edges on the same layer
should be minimum of the same distance as the distance H/2 (Figure 36) or B (Figure
37) between the 50 Ω trace and the ground plane underneath/above the trace.
72
NOT ES
Annex D
Modulation definition
(immunity, informative)
Source: According ISO 11452-1, Annex B (informative):
This annex explains the principle of constant Note: The total power is the sum of the
peak test level. power in the carrier component and the
power in the side-frequency component.
The electric filed strength of a continuous
wave signal, ECW , may be written in the form The peak test level conversation may be
written
ECW = E × cos(ωt ) ECWpeak = E AMpeak
where E is the peak value of E CW . The relation between CW power and AM

power is then
The mean power may be calculated
⎡⎛ m 2 ⎞ E ' 2 ⎤
E2 ⎢⎜⎜1 + ⎟× ⎥
PCW = PAM ⎣⎝ 2 ⎟⎠ 2 ⎦
2 = =
The electric field strength of an amplitude PCW E2
modulated signal, EAM , may be written in the 2
form
⎛ m2 ⎞
⎜1 + ⎟
⎛ m 2 ⎞ ⎛ E ' ⎞ ⎜⎝ 2 ⎟⎠
⎜⎜1 + ⎟×⎜ ⎟ =
E AM = E ' × (1 + m × cos ϑt ) cos(ψt ) ⎝ 2 ⎟⎠ ⎜⎝ E ⎟⎠ (1 + m) 2
where the peak value,
E AMpeak = E × (1 + m)
' Therefore
The mean power, 2 + m2

PAM = PCW ×
⎛ m 2 ⎞ E '2 2(1 + m) 2
PAM = ⎜⎜1 + ⎟×
2 ⎟⎠ 2
For m=0.8 (AM 1 KHz 80%) this relation
⎝
gives PAM = 0.407 × PCW
In all these formulae,
m is the modulation index;
other symbols are explained in the
relevant parts of ISO 11452.
73
A NN E XES
Annex E
Example of an IC EMC specification (general, informative)
IC type with CPU, Emission
Test method selection

Coupling point Coupling mechanism with limit
(Class I-III,C,C-BS)
osc. crosstalk
port crosstalk
Configuration
(global/local)
Pin (if available)
IC function
Functional
Operation
crosstalk
Pin Type
module
Mode*
150 Ω
direct
TEM
core
1Ω
Name
No.:
Function
All signals for external (synchronous and asynchronous) memory access

System clock
Regional driver local C1 S2 III
output
Data bus Regional driver local C1 S2 III
Address bus Regional driver local C1 S2 III
ALE signal pin Regional driver local C1 S2 III
All Chip select
(CS)
Read (R) Regional driver local C1 S2 III
Write (W) Regional driver local C1 S2 III
Other Memory
access signals
Digital ground
GNDD1..x Supply global C1 S2 III III
Supplies
Vcc_core1..x Supply global C1 S2 • III III
Vcc_osc Supply global C6 S1 • III III
Vcc_I/O Supply global C1 S3 • III III
Supply global III III
Synchronous serial bus (e.g.SPI, I 2 C)
Communication
Clock out (e.g. Regional driver local C1 S3 • III III
SPI CLK)
Com. Data out
Regional driver local C1 S3 • III III
(e.g. MOSI)
I/O port with highest driver strength
C5-S3 T • III III
Digital I/O port in
Regional drivers local C5-S3 H,L • III III
output mode
C1-S2 H,L • • III III
Line drivers and Line receivers
C5-S3 T • III III
Relay drivers Line drivers global C5-S3 H,L • III III
C1-S2 H,L • • III III
'Wake up' signal Line receivers global C1-S2 IA • • III III
Asynchronous serial bus (e.g. CAN)
C5-S3 T • III III
Symmetrical line
CAN driver global C5-S3 H,L • III
drivers
C1-S2 H,L • • III
Symmetrical line
CAN receiver global C1-S2 IA • • III III
receivers
A = defined active; IA = defined inactive, realised with internal or external pull up or pull down
Table 34, IC EMC specification, IC type with CPU, Emission
74
NOT ES
IC type with CPU, Immunity
Injection point Monitoring Test method

Pin Monitoring pins
Configuration Mode*
Port IC function module
Operation Mode*
Failure criteria
(global/local)
TEM
DPI
Pin Type
Function
Function
Name
Name
No.
No.
C C
AM AM
W W
Regional C1 S2 I/O Port 1 III
Reset local
Input C1 S2 Reset 2 III
PLL configuration pins
CLK out or III
PLL- Regional
local C1 S2 toggling 1 III
freq1..x Input
port III
Oscillator
Xtal1 local CLK out or III
Osc C12 S3 toggling 1
Xtal2 local port III
Supplies
Vcc_core1..
Supply global C1 S2 I/O Port 1 III
x
CLK out or
Vcc_osc Supply global C12 S3 toggling 1 III
port
Vcc_I/O Supply global C5 S3 I/O Port 1 III
Supply global
A = defined active; IA = defined inactive, realised with internal or external pull up or pull down
Table 35, IC EMC specification, IC type with CPU, Immunity
Failure criteria
No. Description Tolerance

1 Toggling port toggling, constant frequency
2 Voltage at pin as specified in data sheet
Table 36, IC EMC specification, IC type with CPU, Failure criteria
75
A NN E XES
Annex F
Calculation of pin specific limits (general, informative)
Fourier transformation of time domain signals
Toggling digital data pins or periodically switching analogue power outputs generate switching
harmonics as a matter of principle defined by the functional necessary and specified signal
waveform.
The resulting harmonics of those wanted signal waveforms can be calculated with Fourier-
transformation. For trapezoidal periodic signals as shown in Figure 38, the envelope of the
resulting amplitude versus frequency spectrum can be subdivided into 3 sections. From the
fundamental frequency of the signal up to the first corner frequency fg1 the spectral response
is parallel with the frequency axis. After the first corner frequency fg1 the amplitudes diminish
by 20dB/decade up to the second corner frequency f g2, from which point the spectrum falls off
at 40dB/decade, as shown in Figure 39. The simplified equations to calculate amplitudes and
corner frequencies of the spectrum are depicted for the sections in Figure 39. AO is defined as
the amplitude of original signal (I or V), ti as the signal pulse width, ts as the switching time, T O
as the period of the fundamental frequency and n as the multiples of the fundamental
frequency.
Figure 38, periodical trapezoidal signal, time domain
Periodical Trapezodial Signal - Frequency Domain

0 dB fg1
0 21
An ≈ A0
An ≈
2 A0ti π n
-10 T0
-20 dB
-20
-30
fg2
[Amplitude] dB
-40
2 1 T0
An ≈ A0
-50 π 2 n 2 ts
-40 dB
-60
-70
-80
-90
0,1 1 1
fg 1 = 1 10 fg 2 = 100 1000
π ti π ts
Frequency
Figure 39, Fourier Analysis of periodical signals (simplified calculation)
76
NOT ES
Notes:
77
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Systems
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60528 Frankfurt am Main
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Joester, Michael Continental Automotive GmbH

Klotz, Dr. Frank Infineon Technologies AG

Pfaff, Dr. Wolfgang Robert BOSCH GmbH

Steinecke, Thomas Infineon Technologies AG

Adam Opel GmbH

This document may be reproduced according to the copyright and liability

Revision: January 2010

Test Board 10. Test board ............................................................................................................................ 49

2. General and objective

to obtain relevant quantitative measuring results

to reduce the number of test methods to a necessary minimum

to strengthen the acceptance of IC EMC test results

to release ICs based on IC level results

International IC EMC standards

[1] IEC 61967-1 Ed 1: 2002, Integrated circuits Measurement of electromagnetic

[2] IEC 61967-2 Ed 1: 2005, Integrated circuits Measurement of electromagnetic

[3] IEC 61967-4 Ed 1: 2002, Integrated circuits Measurement of electromagnetic

IEC 61967-4/A1/Ed 1: 2006, Amendment 1 to IEC 61967-4: Integrated circuits – Measurement

[10] IEC 61967-4-1/TR/Ed 1: APPLICATION GUIDANCE TO IEC 61967-4, Integrated

[5] IEC 62132-1 Ed 1: 2006, Integrated circuits Measurement of electromagnetic

[6]* IEC 62132-2 (47A/774/CD), Integrated circuits Measurement of electromagnetic

[7] IEC 62132-4 Ed. 1: 2006, Integrated circuits Measurement of electromagnetic

Other relevant documents

[9]*** LIN EMC Test Specification, Version V1.0 (01.08.2004)

*) Working draft within IEC SC47A WG9

"Pertaining to the representation of information by means of a physical quantity which

"Pertaining to the representation of information by distinct states or discrete values."

• EMC pin type

• Fixed Function Unit (FFU)

Passive IC function module: No supply system for supply connection

Active IC function module: A dedicated supply IC Function

Note: The supply connection is handled as a supply reference

An integrated circuit (IC) is a set of implemented

is an interface between an IC and its circuit environment.

An active port is initialized to a defined configuration or connected to a →fixed-function

An inactive port is initialized to a defined configuration or connected to a →fixed-function

A port selected for IC EMC tests.

• Printed Circuit Board (PCB):

• Supply pin pairs

Port modules are:

Examples: ISO9141 outputs, LIN outputs or analog

b) Line Receiver Core

board (global pin).

c) Symmetrical Line Driver

drives differential signals leaving the application

Examples: CAN outputs, LVDS outputs

d) Symmetrical Line Receiver

Examples: CAN inputs, LVDS inputs

drives signals not leaving the application board (local pin).

Examples: serial data outputs, operational amplifier outputs

receives signals from the application board (local pin).

Examples: serial data inputs, Input stages of operational amplifiers, Analog-Digital-Converter

g) High Side driver

h) Low Side driver

distributes supply current to at least one IC PLL factor

function module (local or global pin). Supply module Supply module

Core Oscillator Oscillator

input pin of same supply system and minimum one

current output pin. It may contain active elements or analog

like voltage stabilization and/or passive elements

elements etc. or analog

Core module Supply module

120 kHz* 60 kHz 100/120kHz* RBW