The Low Pin Count bus, or LPC bus, is used on IBM-compatible personal computers

to connect low-bandwidth devices to the CPU, such as the boot ROM and the "legac
y" I/O devices (behind a super I/O chip). The "legacy" I/O devices usually inclu
de serial and parallel ports, PS/2 keyboard, PS/2 mouse, floppy disk controller
and ?more recently ?the Trusted Platform Module (TPM).[2]
The physical wires of the LPC bus usually connect to the southbridge chip on a P
C motherboard, which contains the circuit equivalents of the "legacy" onboard pe
ripherals of the IBM PC/AT architecture, such as the two programmable interrupt
controllers, the programmable interval timer, and the two ISA DMA controllers.
Contents [hide]
1 Overview
2 Supported peripherals
3 See also
4 References
5 External links
Overview[edit]
The LPC bus was introduced by Intel in 1998 as a substitute for the Industry Sta
ndard Architecture (ISA) bus. It resembles ISA to software, although physically
it is quite different, replacing the 16-bit-wide, 8.33 MHz ISA bus with a 4-bitwide bus operating at 4 times the clock speed (33.3 MHz).
LPC's main advantage is that it requires only seven signals, and is therefore ea
sy to route on modern motherboards, which are often quite crowded. An integrated
circuit using LPC will need 30 to 72 fewer pins than its ISA equivalent. The cl
ock rate was chosen to match that of PCI in order to further ease integration. A
lso, LPC is intended to be a motherboard-only bus. No connector is defined, and
no LPC peripheral daughterboards are available, except motherboard-specific Trus
ted Platform Modules (TPMs).[2] There is no configuration in terms of device dis
covery. Since only motherboard devices are connected, or specific TPMs, the host
firmware (BIOS, UEFI) "knows" how to set them up and deal with them.
The LPC specification defines seven mandatory signals required for bidirectional
data transfer. Four of these signals carry the multiplexed address and data. Th
e other three ?frame, reset, and clock ?are control signals, the latter two of which
can be shared with the PCIRST# and PCICLK signals.
Six optional signals defined in the specification can be used for interrupt supp
ort, direct memory access, waking the system from a low power ("sleeping") state
and notifying the LPC peripherals that power will soon be removed.
LPC data transfer rates depend on the type of bus access (I/O, Memory, DMA, firm
ware) performed and by the speed of the host and the LPC device. DMA cycles can
transfer up to 6.67 MB/s.[3]
A CPLD or FPGA can implement a LPC host or a LPC peripheral.[4]
The original Xbox game console has an LPC debug port that can be used to force t
he Xbox to boot new code.[5][6]
Intel designed the LPC bus so that the System BIOS could be stored in a single f
lash memory chip directly connected to the LPC bus. Intel also made it possible
to put operating system images and software applications on a single flash memor
y chip directly connected to the LPC bus, as an alternative to a Parallel ATA po
rt.[7]
Supported peripherals[edit]
The LPC bus specification limits what type of peripherals may be connected to it
. It only allows devices that belong to the following classes of devices: super

I/O devices, integrated audio including either AC'97 devices or devices that imp
lemented the Sound Blaster interface, and generic-application memory including n
onvolatile BIOS memory, firmware hubs, and embedded controllers. Furthermore, ea
ch class is restricted on which bus cycles are allowed for each class.[3]
Super I/O devices and audio devices are allowed to consume I/O cycles, accept IS
A-style DMA cycles, and generate bus master cycles. Generic-application memory d
evices like nonvolatile BIOS memory and LPC flash devices were allowed to accept
memory cycles. Firmware hubs were allowed to accept firmware memory cycles. Emb
edded controllers were allowed to accept I/O cycles and could generate bus maste
r cycles. Therefore, some ISA cycles that were deemed not useful to these classe
s were removed. They include host-initiated 2-byte memory cycles and host-initia
ted 2-byte I/O cycles. These removed transfer types could be initiated by the ho
st on ISA buses but not on LPC buses. The host would have to simulate 2-byte cyc
les by splitting them up into two 1-byte cycles. The ISA bus has a similar conce
pt because the original 8-bit ISA bus required 16-bit cycles to be split up. The
refore, the 16-bit ISA bus automatically split 16-bit cycles into 8-bit cycles u
nless the ISA device asserted a signal that told the bus that it could accept th
e requested 16-bit transfer.[8] ISA-style bus mastering has been replaced with a
bus mastering protocol that does not rely on the ISA-style DMA controllers at a
ll in order to remove a limit on the number of peripherals that could perform bu
s mastering. The ISA-style bus cycles that were inherited by LPC are 1-byte host
-initiated I/O bus cycles, 1-byte host-initiated memory cycles, and 1- or 2-byte
host-initiated ISA-style DMA cycles.[3]
However, some non-ISA bus cycles were added. Cycles that were added to improve t
he performance of devices beside firmware hubs include LPC-style 1-, 2-, and 4-b
yte bus master memory cycles; 1-, 2-, and 4-byte bus master I/O cycles; and 32-b
it third party DMA which conforms to all of the restrictions of ISA-style third
party DMA except for the fact that it can do 32-bit transfers. Any device that i
s allowed to accept traditional ISA-style DMA is also allowed to use this 32-bit
ISA-style DMA. The host could initiate 32-bit ISA-style DMA cycles, while perip
herals could initiate bus master cycles. Firmware hubs consumed firmware cycles
that were designed just for firmware hubs so that firmware addresses and normal
memory-mapped I/O addresses could overlap without conflict. Firmware memory read
s could read 1, 2, 4, or 128 bytes at once. Firmware memory writes could write 1
, 2, or 4 bytes at once.[3]