Stochastic Automata Network for Performance

Evaluation of Heterogeneous SoC

Communication
Ulhas Deshmukh1

Vineet Sahula2

1 Research Scholar,
Malaviya National Institute of Technology,Jaipur
2 Associate Professor, Department of ECE
Malaviya National Institute of Technology,Jaipur

26th Norchip Conference,

17-18 November 2008, Tallinn, ESTONIA
Acknowledgments- The Dept. of IT, Ministry of Comm. & IT, Govt. of India under SMDP-VLSI-II project.

Ulhas Deshmukh, Vineet Sahula

SAN based Performance Model for SoC Communication

A single shared bus (SSB) communication

architecture.
PE 1

PE 2

PE N

I/F

I/F

I/F

SINGLE SHARED BUS

I/F
MEM

I/F
Arbiter

Model formulation
All PEs perform concurrent computation
Each PE is modeled as stochastic automaton
Interactions among PEs are modeled as synchronizing and
functional transition
Ulhas Deshmukh, Vineet Sahula

SAN based Performance Model for SoC Communication

The SAN model for a SSB architecture

A
3

(1)

A
3

State 0 CP
State 1 AC
State 2 FW
State 3 RW

(N)

PE1

(2)

PE N

PE 2

Automaton A(i) represents GSMP model of a PEi

States of each automaton are
CP- computing state
AC- accessing state
FW- full waiting state
RW- residual waiting state
Ulhas Deshmukh, Vineet Sahula

SAN based Performance Model for SoC Communication

An automaton A(i) of PEi in SSB

RWi

1i

3i

FWi

Performance metrics

1i

1i

1i

ACi

1i

PUi

2i

CP

BWi
Li

0i

Wi

i
= PAC

i
i
+ PCP
= PAC

i
i
= (PFW
+ PRW
)

i
i
= (FW
2i + RW
3i )/1i

1 if, x j = CP j , j = i + 1, ..., N
0 otherwise

2i = (ej , pe , 1), j = i + 1, ..., N; ej is 1 event of PEj


1 if, x j = AC j , j = 1, 2, ..., N

j
3i = f (x ) =
0 otherwise

1i = f (x j ) =

0i = 0i = 1;

1i = 1 1i

Ulhas Deshmukh, Vineet Sahula

SAN based Performance Model for SoC Communication

Hierarchical bus bridge (HBB) architecture

PE 1

PE 2

PE N

PE 1

I/F

I/F

I/F

I/F

PE 2

Bus I/f
Bridge
Bus I/f

BUS 1

I/F

I/F

MEM 1

Arbiter

PE N
I/F

I/F

BUS 2

I/F

I/F

MEM 2

Arbiter

Concurrent communication on BUS1 & BUS2

Each PE can access MEM1 & MEM2
Consider PE1 mapped to BUS1

MEM1 -local memory, MEM2 -global memory

Ulhas Deshmukh, Vineet Sahula

SAN based Performance Model for SoC Communication

An automaton A(i) of PEi in HBB

1i

1i
lRW

1i

3i

gRW

2i

0i

0i

5i
gFW

lAC

1i

2i
CP

6i

1i

lFW

4i
2i
2i

gAC

2i

States of a PE
CP- computing state
lAC, lFW, lRW- States correspond to local memory MEM 1

gAC, gFW, gRW- Analogous states for global memory

MEM2
Ulhas Deshmukh, Vineet Sahula

SAN based Performance Model for SoC Communication

Results
C2=C3=2 cycles
C2=2,C3=4 cycles
C2=4,C3=2 cycles
C2=C3=4 cycles

0.3
0.2
0.1
0

6
8 10 12 14 16 18 20
Communication time (Cl)

0.5
Queue length (L1)

Bandwidth (BW1)

0.4

C2=C3=2 cycles
C2=2,C3=4 cycles
C2=4,C3=2 cycles
C2=C3=4 cycles

0.4
0.3
0.2
0.1
0

6
8 10 12 14 16 18 20
Communication time (Cl)

Conclusions
Bandwidth is proportional to communication time
Bandwidth negatively influence by communication time of
other PEs
Converse observations obtained for queue length
Ulhas Deshmukh, Vineet Sahula

SAN based Performance Model for SoC Communication

Local bandwidth (BWl22)

0.3
0.25
0.2

Cl22=2 cycles
Cl22=4 cycles
Cl22=2,Cg11=4 cycles

0.15
0.1
0.05
0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Probability of local request (Xl)

Global bandwidth (BWg22)

Results
0.3
0.25
0.2

Cg22=2 cycles
Cg22=4 cycles
Cg22=6 cycles

0.15
0.1
0.05
0

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

Probability of local request (Xl)

Conclusions
Local BW increases with probability of local request &
communication time
Local BW is negatively influenced by global communication
time
Global BW increases with probability of global request &
communication time
Ulhas Deshmukh, Vineet Sahula

SAN based Performance Model for SoC Communication