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length(etch) matching from T point to pin....Allegro PCB-16.2 - Cadence Community

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length(etch) matching from T point to pin....Allegro PCB-16.2

Last post Thu, Jan 7 2010 9:26 AM by MAAC. 4 replies.

Started by MAAC 05 Jan 2010 04:32 AM. Topic has 4 replies and 4021 views

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Tue, Jan 5 2010 4:32 AM

MAAC

length(etch) matching from T point to pin....Allegro PCB-16.2

Reply

Hi,

Joined on Thu, Jul 17 2008

Bangalore, Karnataka
Posts 195
Points 3,620

Is their any option to set the constraints so that i can route the track such that length X= length Y(Refer the
screenshot). The whole thing is a single track n the length has to be matched from T junction( T ) to two different
pins i.e. through length X & length Y

Thnx

LENGTH.JPG
Post Points: 20

Tue, Jan 5 2010 6:55 AM

Dennis Nagle

Re: length(etch) matching from T point to pin....Allegro PCB-16.2

Reply

If it ruly is just matching lengths X & Y, then what you want is to use the Relative Prop Delay constraint in CM. Call
out the specific pin pairs from the T-point to each load pin.

Joined on Mon, Oct 13

2008
Chelmsford, MA
Posts 35
Points 505

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Post Points: 20

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length(etch) matching from T point to pin....Allegro PCB-16.2 - Cadence Community

Wed, Jan 6 2010 12:53 PM
MAAC

Re: length(etch) matching from T point to pin....Allegro PCB-16.2

Reply

but how can i specify the constraints from T junction to the pins. Rel prop delay takes complete track into
consideration

Joined on Thu, Jul 17 2008

Bangalore, Karnataka
Posts 195
Points 3,620

Post Points: 20

Wed, Jan 6 2010 3:24 PM

SueFrederick

Re: length(etch) matching from T point to pin....Allegro PCB-16.2

Reply

From Cadence Online solution 11041370 (http://support.cadence.com/wps/mypoc/cos?

uri=deeplinkmin:ViewSolution;solutionNumber=11041370;searchHash=f08b9b215e4109b3d3f510e615d9067b)

Joined on Mon, Jul 14 2008

HOME, GA
Posts 4
Points 80

One way to accomplish this using Allegro PCB Editor is to extract the net into SigXplorer (SigXp) to create a
topology file (Electrical CSet) with the specific pinpair constraints, update Constraint Manager (CM) with the new
Electrical CSet (ECSet), and finally apply the new ECSet to other nets in CM. Applying the ECSet to the nets will
automatically create the pinpairs.
STEPS:
It is recommended to start with a clean database that does not have any properties or Electrical CSets assigned to
nets and follow these detailed steps:
1. Open CM. In the Electrical domain select the Net > Routing > Relative Probagation Delay worksheet to extract
the net into SigXp.
a. Select Setup > Constraints > Constraint Manager (or click the CM icon)
b. Select the Electrical domain
c. Select/expand the Net > Routing > Relative Propagation Delay (or any
other routing worksheet)
d. Select the net to extract with the left mouse button (LMB)
e. Right mouse button (RMB) and select SigXplorer
2. Create a Topology in SigXp with specific pin pair constraints
a. In SigXp select Set > Constraints
b. Select the Rel Prop Delay (tab)
c. Select the desired pin pair (reference designator.pin number) in the lower left
corner. Notice the From/To in the "Rule Editing" section is populated with
these selections.
d. To match nets within 50 mils of each other, set the following:
- Scope
= Global
- Delta Type = Length
- Delta
=0
- Tol Type = Length
- Tolerance = 25 (half of your requirement, +/-)
- Fill in the "Rule Name" (Match Group name) near the top of the "Rule Editing" section
e. Click "Add" to the right of this list and notice the rule gets added in the
"Existing Rules" section (repeat 2c-2e if necessary)
f. If you wish to add other rules to the ECset, select other tab(s) in the "Set
Topology Constraints" form and fill in appropriately.
g. When finished, select "OK"
3. Update Constraint Manager with the new rule(s)
a. In SigXp, select File > Update Constraint Manager
b. Click YES to 'Do you wish Net "xyz" to reference ElectricalCset "xyz"?'
c. Click "Close" to close the the "Electrical CSet Apply Information" form
Notice the pin pair information is listed twice in the Constraint Manager spreadsheet,
once under the Match Group (MGrp) and once under the net name. The net name will show
the Referenced Electrical CSet assigned to the net. You may need to widen the column to
the right of the "Objects" column to see this information.
4. Apply the new ECSet constraints to other nets in Constraint Manager
a. In the "Referenced Electrical CSet" column just to the right of the "Objects"
column, click on the same row of the net name to assign the new ECset to
and choose the ECset name from the popup menu.
b. To apply the new ECSet to multiple nets at once, hold down the LMB and
drag the mouse down to select other nets
Again, you will notice the pin pairs will show up under the Match Group name near the
top of the spreadsheet form as well as on the individual nets with the Referenced Electrical CSet.
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length(etch) matching from T point to pin....Allegro PCB-16.2 - Cadence Community

Thu, Jan 7 2010 9:26 AM
MAAC

Re: length(etch) matching from T point to pin....Allegro PCB-16.2

Reply

To add few pts..i followed the same steps &

Joined on Thu, Jul 17 2008

Bangalore, Karnataka
Posts 195
Points 3,620

i named MGT1as relative prop delay from T.1 to U15.11 & MGT2 for T.1 to U36.11
then updated to CM & again i created one more Match Group MG11 consisting of MGT1 & MGT2
mentioned the delta:tolerance::10mil:1% (10mils is the relative delay between MGT1 & MGT2)
then i could achieve the relative delay using the delay tune
thnx everyone for the help
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Started by MAAC at 05 Jan 2010 04:32 AM. Topic has 4 replies.

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