DS FT801

Document No.
: FT_000986
FT801 Embedded Video Engine
Datasheet Version 1.0
Clearance No.: FTDI#376
Future Technology Devices International Ltd.
FT801
(Embedded Video Engine)
The FT801 is an easy to use graphic
controller targeted for embedded
applications to generate high-quality
Human Machine Interfaces (HMIs).
It has the following features:
FT801
functionality
includes
graphic
controller, audio processing, and capacitive
touch controller interface.
Compatibility mode allows display code to be

run on FT801 or FT800. Extended mode
enables multi-touch capabilities for FT801.
Support for LCD display in WQVGA

(480x272) and QVGA (320x240) formats
with data enable (DE) support mode and
VSYNC/HSYNC mode
The FT801 calculates for 8-bit colour despite

only providing pins for 6-bit (RGB-6,6,6);
this improves the half tone appearance
Display enable control output to LCD panel
Mono audio channel output with PWM output
Built-in sound synthesizer
Audio wave playback for mono 8-bit linear

PCM, 4-bit ADPCM and -Law coding format
at sampling frequency from 8kHz to 48kHz.
Built-in digital filter reduces the system
design complexity of external filtering
Embedded Video Engine (EVE) with widget

support can offload the system MPU and
provide a variety of graphic features
Built-in graphics operations allow users with

little expertise to create high-quality display
PWM output for backlight dimming control

for LED
Support capacitive touch screen with up to 5

touches detection
Hardware engine can recognize touch tags

and track touch movement. It provides
notification for up to 255 touch tags.
Low power consumption for portable

application, 24mA active (typical) and 250
uA sleep (typical)
No frame buffer RAM required
Advanced object oriented architecture

enables low cost MPU/MCU as system host
using I2C and SPI interfaces
Power mode control allows chip to be put in

power down, sleep and standby states
Supports host interface I/O voltage from

1.8V to 3.3V
Standard serial interface to host MPU/MCU

with SPI up to 30MHz or IC clocking up to
3.4MHz
Internal voltage regulator supplies 1.2V to

the digital core
-40C
to
85C
temperature range
Available in a compact Pb-free, VQFN-48,

7mm X 7mm X 0.9mm package, RoHS
compliant
Enhanced sketch processing
Programmable interrupt controller provides

interrupts to host MPU/MCU
Built-in 12MHz crystal oscillator with PLL

providing 48MHz or 36MHz system clock
Clock switch command for internal or

external clock source. External 12MHz
crystal or clock input can be used for higher
accuracy.
Video RGB parallel output (default RGB data

width of 6-6-6) with 2 bit dithering;
configurable to support resolution up to
512x512 and R/G/B data width of 1 to 6
Programmable timing to adjust HSYNC and
VSYNC
timing,
enabling
interface
to
numerous displays
extended
Copyright 2014 Future Technology Devices International Limited
operating
Document No.: FT_000986

Disclaimer:
Neither the whole nor any part of the information contained in, or the product described in this manual, may be adapted or
reproduced in any material or electronic form without the prior written consent of the copyright holder. This product and its
documentation are supplied on an as-is basis and no warranty as to their suitability for any particular purpose is either made
or implied. Future Technology Devices International Ltd will not accept any claim for damages howsoever arising as a result of
use or failure of this product. Your statutory rights are not affected. This product or any variant of it is not intended for use in
any medical appliance, device or system in which the failure of the product might reasonably be expected to result in persona l
injury. This document provides preliminary information that may be subject to change without notice. No freedom to use
patents or other intellectual property rights is implied by the publication of this document.
Future Technology Devices International Ltd
Unit 1, 2 Seaward Place
Centurion Business Park
Glasgow G41 1HH
United Kingdom
Scotland Registered Company Number: SC136640

Typical Applications
Point of Sales Machines
Power meter
Multi-function Printers
Home appliance devices
Instrumentation
Set-top box
Home Security Systems
Thermostats
Graphic touch pad remote, dial pad
Sprinkler system displays
Tele / Video Conference Systems
Medical Appliances
Phones and Switchboards
GPS / Satnav
Medical Appliances
Vending Machine Control Panels
Blood Pressure displays
Elevator Controls
Heart monitors
and many more
Glucose level displays
Breathalyzers
Gas chromatographs
1.1 Part Numbers

Part Number
Package
FT801Q-x
48 Pin VQFN, pitch 0.5mm, body 7mm x 7mm x 0.9mm
Table 1- Video Controller Part Numbers

Note: Packaging codes for x is:
-R: Taped and Reel, (VQFN in 2500 pieces per reel)
-T: Tray packing, (VQFN in 250 pieces per tray)
For example: FT801Q-R is 2500 VQFN pieces in taped and reel packaging

FT801 Block Diagram
Figure 2-1 FT801 Block Diagram

For a description of each function please refer to Section 4.
Figure 2-2 FT801 System Design Diagram
FT801 with EVE (Embedded Video Engine) technology simplifies the system architecture for advanced
human machine interfaces (HMIs) by providing support for display, audio, and touch as well as an object
oriented architecture approach that extends from display creation to the rendering of the graphics.

Contents
1
Typical Applications ...................................................................... 3

1.1
Part Numbers...................................................................................... 3
FT801 Block Diagram.................................................................... 4
Device Pin Out and Signal Description .......................................... 7

3.1
VQFN-48 Package Pin Out ................................................................... 7
3.2
Pin Description ................................................................................... 8
Function Description................................................................... 13
4.1
Serial Host Interface ......................................................................... 13
4.1.1
SPI Interface ............................................................................................................. 15
4.1.2
IC Interface ............................................................................................................. 15
4.1.3
Serial Data Protocol ................................................................................................... 15
4.1.4
Host Memory Read ..................................................................................................... 15
4.1.5
Host Memory Write .................................................................................................... 16
4.1.6
Host Command .......................................................................................................... 16
4.1.7
Interrupts ................................................................................................................. 17
4.2
System Clock .................................................................................... 18
4.2.1
Clock Source ............................................................................................................. 18
4.2.2
Phase Locked Loop..................................................................................................... 19
4.2.3
Clock Enable ............................................................................................................. 19
4.2.4
Clock Frequency ........................................................................................................ 19
4.3
Graphics Engine ................................................................................ 20
4.3.1
Introduction .............................................................................................................. 20
4.3.2
ROM and RAM Fonts ................................................................................................... 21
4.4
Parallel RGB Interface ...................................................................... 24
4.5
Miscellaneous Control ....................................................................... 26
4.5.1
Backlight Control Pin .................................................................................................. 26
4.5.2
DISP Control Pin ........................................................................................................ 26
4.5.3
General Purpose IO pins ............................................................................................. 26
4.5.4
Pins Drive Current Control .......................................................................................... 26
4.6
Audio Engine..................................................................................... 27
4.6.1
Sound Synthesizer ..................................................................................................... 27
4.6.2
Audio Playback .......................................................................................................... 29
4.7
Touch-Screen Engine ........................................................................ 29
4.7.1
Compatibility mode .................................................................................................... 30
4.7.2
Extended mode ......................................................................................................... 30
4.8
Power Management .......................................................................... 31
4.8.1
Power supply............................................................................................................. 31
4.8.2
Internal Regulator and POR ......................................................................................... 31

4.8.3
FT801 Memory Map .................................................................... 37

5.1
FT801 Registers ................................................................................ 38
Devices Characteristics and Ratings ........................................... 43

6.1
Absolute Maximum Ratings............................................................... 43
6.2
DC Characteristics............................................................................. 44
6.3
AC Characteristics ............................................................................. 46
6.3.1
System clock ............................................................................................................. 46
6.3.2
Host Interface SPI Mode 0 .......................................................................................... 46
6.3.3
Host Interface I2C Mode Timing................................................................................... 47
6.3.4
RGB Video Timing ...................................................................................................... 48
Application Examples ................................................................. 50

7.1

Power Modes ............................................................................................................. 33
Examples of LCD Interface connection .............................................. 50
Package Parameters ................................................................... 51

8.1
VQFN-48 Package Dimensions .......................................................... 51
8.2
Solder Reflow Profile ........................................................................ 52
FTDI Chip Contact Information ................................................... 53

Appendix A References ........................................................................... 55
Appendix B - List of Figures and Tables ..................................................... 55
Appendix C - Revision History .................................................................... 57

Device Pin Out and Signal Description
3.1 VQFN-48 Package Pin Out
Figure 3-1 Pin Configuration VQFN-48 (top view)

3.2 Pin Description
Table 3-1 FT801Q pin description

Pin
No.
Name
Type
Description
AUDIO_L
Audio PWM out, push-pull output, 16mA sink/source

current.
Pad powered from pin VCC.
GND
SPI_SCLK/ I2C_SCL
Ground
In SPI mode: SPI SCLK input.
In I2C mode: SCL input, need external 1k ~ 4.7k
pull up to VCCIO.
Input pad with Schmitt trigger, 3.3V tolerant.
Pad powered from pin VCCIO.
MISO/ I2C_SDA
I/O
In SPI mode: SPI MISO output.

In I2C mode: SDA input/Open Drain Output, need
external1k ~ 4.7k pull up to VCCIO.
Input with Schmitt trigger, 3.3V tolerant, 4/8/12/16mA
sink/source current.
MOSI/ I2C_SA0
In SPI mode: SPI MOSI input.

In I2C mode: Input, bit 0 of I2C device address.
Input pad, 3.3V tolerant.
CS_N/ I2C_SA1
In SPI mode: SPI CS_N input, active low.

Input pad, 3.3V tolerant.
GPIO0/ I2C_SA2
I/O
In SPI mode: General purpose input, output port.

Push-pull, three-state output. 3.3V tolerant,
4/8/12/16mA sink/source current.
GPIO1
I/O
General purpose input, output port.

Push-pull, three-state output. 3.3V tolerant,
4/8/12/16mA sink/source current.

Continued
Pin
No.
Name
Type
VCCIO
Description
I/O power supply, connect a 0.1uF decoupling

capacitor. Support 1.8V, 2.5V or 3.3V.
Note: VCCIO supply to IO pads from pin 3 to 12 only.
10
MODE
Host interface SPI(pull low) or I2C(pull up) mode select

input, 3.3V tolerant
11
INT_N
OD
Host Interrupt, open drain output, active low, pull up to

VCCIO through a 1k ~10k resistor.
12
PD_N
Power down input, active low, 3.3V tolerant, pull up to

VCCIO through 47k resistor and 100nF to ground.
13
X1/ CLK
Crystal oscillator or clock input; Connect to GND if not

used.
3.3V peak input allowed.
14
X2
Crystal oscillator output; leave open if not used.

15
GND
16
VCC
17
VCC1V2
18
VCC
19
CTP_RST_N
Ground
3.3V power supply input.
1.2V regulator output pin. Connect a 4.7uF decoupling
capacitor to GND.
3.3V power supply input.
Connect to reset or wake signal of the CTPM. Output,
open source, external pull-down resistor required.
20
CTP_INT_N
Connect to interrupt or ready pin of the CTPM. Input.

21
CTP_SCL
I/OD
Connect to I2C SCL pin of the CTPM. Plain input, opendrain output.
22
CTP_SDA
I/OD
Connect to I2C SDA pin of the CTPM. Plain input, opendrain output.
23
GND
Ground

Continued
Pin
No.
Name
Type
Description
24
BACKLIGHT
LED Backlight brightness PWM control signal, push-pull

output, 4/8mA sink/source current.
25
DE
LCD Data Enable, push-pull output, 4/8mA sink/source

current.
26
VSYNC
LCD Vertical Sync, push-pull output, 4/8mA sink/source

current.
27
HSYNC
LCD Horizontal Sync, push-pull output, 4/8mA

28
DISP
General purpose output pin for LCD Display Enable,

push-pull output, 4/8mA sink/source current. Control
by writing to Bit 7 of REG_GPIO register.
29
PCLK
LCD Pixel Clock, push-pull output, 4/8mA sink/source

current.
30
B7
Bit 7 of Blue RGB signals, push-pull output, 4/8mA

31
B6

32
B5

33
B4

34
B3

35
B2

36
GND
Ground
10

Continued
Pin
No.
Name
Type
Description
37
G7
Bit 7 of Green RGB signals, push-pull output, 4/8mA

38
G6

39
G5

40
G4

41
G3

42
G2

43
R7
Bit 7 of Red RGB signals, push-pull output, 4/8mA

44
R6

45
R5

46
R4

11

Continued
Pin No.
Name
Type
Description
47
R3

48
R2

EP
GND
Ground. Exposed thermal pad.
Note:
P
: Power or ground
: Input
: Output
OD
: Open drain output
I/O
: Bi-direction Input and Output
12

Function Description
The FT801 is a single chip, embedded graphic controller with the following function blocks:
Serial Host Interface
System Clock
Graphics Engine
Parallel RGB video interface
Audio Engine
Touch-screen support and interface
Power Management
The functions for each block are briefly described in the following subsections.
4.1 Serial Host Interface

The FT801 uses a standard serial interface to communicate with most types of microcontrollers
and microprocessors. The interface mode is configurable by pull down for SPI and pull up for
IC on pin 10 (MODE). Figure 4-1 shows the two alternative mode connections.
Figure 4-1 Host Interface Options
13

Figure 4-2 illustrates a direct connection to a 1.8-3.3V IO MPU/MCU.
1.8-3.3V
3.3V
VIO
MPU/MCU
4.7k
4.7k
VCC
FT801
CS_N
CS_N
MISO
MISO
MOSI
MOSI
SCLK
SCLK
PD_N
PD_N
INT_N
INT_N
GND
GND
Figure 4-2 SPI Interface 1.8-3.3V connection

Figure 4-3 illustrates the FT801 connected to a 5V IO MPU/MCU. The 74LCX125 logic buffer can tolerate
5V signal from the MPU/MCU, and the FT801 input signals are limited to 3.3V.
3.3V
5V
74LCx125
VIO
MPU/MCU
VCC
FT801
CS_N
CS_N
MISO
MISO
MOSI
MOSI
SCLK
SCLK
PD_N
PD_N
INT_N
INT_N
3.3V
GND
4.7K
GND
4.7K
GND
Figure 4-3 SPI Interface 5V connection
14

4.1.1 SPI Interface

The SPI slave interface operates up to 30MHz. Only SPI mode 0 is currently supported. Refer
to section 6.3.2 for detailed timing specification.
The SPI interface is selected when the MODE pin is tied to GND.
4.1.2 IC Interface
The IC slave interface operates up to 3.4MHz, supporting standard-mode, fast-mode, fastmode plus and high-speed mode. Refer to section 6.3.3 for detailed timing specification.
The IC device address is configurable between 20h to 27h depending on the IC_SA[2:0] pin
setting, ie the 7-bit I2C slave address is 0b0100A2A1A0.
The IC interface is selected when the MODE pin is tied to VCCIO.
4.1.3 Serial Data Protocol

The FT801 appears to the host MPU/MCU as a memory-mapped SPI or IC device. The host
communicates with the FT801 using reads and writes to a large (4 megabyte) address space.
Within this address space are dedicated areas for graphics, audio and touch control. Refer to
section 5 for the detailed memory map.
The host reads and writes the FT801 address space using SPI or IC transactions. These
transactions are memory read, memory write and command write. Serial data is sent by the
most significant bit first. For IC transactions, the same byte sequence is encapsulated in the
IC protocol.
For SPI operation, each transaction starts with CS_N goes low, and ends when CS_N goes
high. Theres no limit on data length within one transaction, as long as the memory address is
continuous.
4.1.4 Host Memory Read

For SPI memory read transaction, the host sends two zero bits, followed by the 22-bit address.
This is followed by a dummy byte. After the dummy byte, the FT801 responds to each host
byte with read data bytes.
Table 4-1 Host memory read transaction (SPI)
7
Address [21:16]
Address [15:8]
Write
Address
Address [7:0]
Dummy byte
Byte 0
Read Data
Byte n
15

For I2C memory read transaction, bytes are packed in the I2C protocol as follow:
[start] <DEVICE ADDRESS + write bit>
<00b+Address[21:16]>
<Address[15:8]>
<Address[7:0]>
[restart] <DEVICE ADDRESS + read bit>
<Read data byte 0>
....
<Read data byte n> [stop]
4.1.5 Host Memory Write

For SPI memory write transaction, the host sends a 1 bit and 0 bit, followed by the 22-bit
address. This is followed by the write data.
Table 4-2 Host memory write transaction (SPI)
7
Address [21:16]
Address [15:8]
Write
Address
Address [7:0]
Byte 0
Byte n
Write Data
For I2C memory write transaction, bytes are packed in the I2C protocol as follow:[start] <DEVICE ADDRESS + write bit>
<10b,Address[21:16]>
<Address[15:8]>
<Address[7:0]>
<Write data byte 0>
....
<Write data byte n> [stop]
4.1.6 Host Command

When sending a command, the host transmits a 3 byte command. Table 4-1 lists all the host
command functions.
Note: ACTIVE command is generated by dummy memory read from address 0 when FT801 is
in sleep or standby mode.
For SPI command transaction, the host sends a 0 bit and 1 bit, followed by the 6-bit
command code. This is followed by 2 bytes 00h.
16

Table 4-3 Host command transaction (SPI)

7
Command [5:0]
For I2C command transaction, bytes are packed in the I2C protocol as follows:
[start] <DEVICE ADDRESS + write bit>
<01b,Command[5:0]>
<00h>
<00h> [stop]
Table 4-4 Host Command Table
1st Byte
2nd byte
3rd byte
Command
Description
Switch from Standby/Sleep modes to
active mode. Dummy read from address
0 generates ACTIVE command.
Power Modes
00000000b
00000000b
00000000b
00h
ACTIVE
01000001b
00000000b
00000000b
41h
STANDBY
01000010b
00000000b
00000000b
01010000b
00000000b
00000000b
42h
SLEEP
50h
PWRDOWN
Put FT801 core to standby mode. Clock

gate off, PLL and Oscillator remain on
(default).
Put FT801 core to sleep mode. Clock
gate off, PLL and Oscillator off.
Switch off 1.2V internal regulator. Clock,
PLL and Oscillator off.
Clock Switching
01000100b
00000000b
00000000b
01001000b
00000000b
00000000b
01100010b
00000000b
00000000b
01100001b
00000000b
00000000b
44h
CLKEXT
48h
CLKINT
62h
CLK48M
61h
CLK36M
Select PLL input from Crystal oscillator

or external input clock.
Select PLL input from Internal relaxation
oscillator (default).
Switch PLL output clock to 48MHz
(default).
Switch PLL output clock to 36MHz.
Miscellaneous
01101000b
00000000b
00000000b
68h
CORERST
Send reset pulse to FT801 core. All

registers and state machines will be
reset.
NOTE: Any command code not specified is reserved and should not be used by the software
4.1.7 Interrupts
The interrupt output pin is enabled by REG_INT_EN. When REG_INT_EN is 0, INT_N is tri-state
(pulled to high by external pull-up resistor). When REG_INT_EN is 1, INT_N is driven low when
any of the interrupt flags in REG_INT_FLAGS are high, after masking with REG_INT_MASK.
Writing a 1 in any bit of REG_INT_MASK will enable the correspond interrupt. Each bit in
REG_INT_FLAGS is set by a corresponding interrupt source. REG_INT_FLAGS is readable by
the host at any time, and clears when read.
17

Table 4-5 Interrupt Flags bit assignment

Bit
Interrupt Sources
CONVCOMPLETE
CMDFLAG
CMDEMPTY
PLAYBACK
Conditions
Touch-screen
conversions
completed
Command FIFO
flag
Command FIFO
empty
Audio playback
ended
Bit
Interrupt Sources
SOUND
TAG
Reserved
SWAP
Conditions
Sound effect
ended
Touch-screen tag
value change
Display list swap

occurred
4.2 System Clock
4.2.1 Clock Source

The FT801 can be configured to use any of the three clock sources for system clock:
Internal relaxation oscillator clock
External 12MHz crystal
External 12MHz square wave clock
Figure 4-4, Figure 4-5 and Figure 4-6Error! Reference source not found. show the pin
connections for these clock options.
Figure 4-4 Internal relaxation oscillator connection
18

Figure 4-5 Crystal oscillator connection
Figure 4-6 External clock input
4.2.2 Phase Locked Loop

The internal PLL takes input clock from the oscillator, and generates clocks to all internal
circuits, including graphics engine, audio engine and touch engine.
4.2.3 Clock Enable

Upon power-on the FT801 enters standby mode. The internal relaxation oscillator is selected
for the PLL clock source. The system clock will be enabled when following step is executed:
Host sends an ACTIVE command (dummy read at address 0)
If the application choose to use the external clock source(12MHz crystal or clock), the following steps
shall be executed:
Host sends an ACTIVE command (dummy read at address 0)

Host sends an CLKEXT command
Host writes to REG_PCLK with non-zero value (ie 5)
If SPI is used as host interface, the SPI clock shall not exceed 11MHz before system clock is
enabled. After system clock is properly enabled, the SPI clock is allowed to go up to 30MHz.
4.2.4 Clock Frequency

Upon power-on the internal relaxation oscillator is untrimmed. The frequency range could be
quite wide from chip to chip (refer to table x-y for internal relaxation oscillator specifications).
19

If the application utilises the internal clock without external clock source, it is recommended to
perform clock trimming by software for better performance. For the details of clock trimming
mechanism please refer to application note AN_299_FT800_FT801_Internal_Clock_Trimming
[FTDI Document FT000987].
By default the system clock is 48MHz when the input clock is 12MHz. Host is allowed to switch
the system clock between 48MHz and 36MHz by the host command CLK48MHz and
CLK36MHz respectively. The clock switching is synchronised to VSYNC edge on the fly. This is
to avoid possible graphics glitch during clock switching. As a result, the clock switch will only
take effect if the REG_PCLK is a non-zero value.
4.3 Graphics Engine
4.3.1 Introduction
The graphics engine executes the display list once for every horizontal line. It executes the
primitive objects in the display list and constructs the display line buffer. The horizontal pixel
content in the line buffer is updated if the object is visible at the horizontal line.
Main features of the graphics engine are:
The primitive objects supported by the graphics processor are: lines, points, rectangles,
bitmaps (comprehensive set of formats), text display, plotting bar graph, edge strips,
and line strips, etc.
Operations such as stencil test, alpha blending and masking are useful for creating a
rich set of effects such as shadows, transitions, reveals, fades and wipes.
Anti-aliasing of the primitive objects (except bitmaps) gives a smoothing effect to the
viewer.
Bitmap transformations enable operations such as translate, scale and rotate.
Display pixels are plotted with 1/16th pixel precision.
Four levels of graphics states
Tag buffer detection
The graphics engine also supports customized build-in widgets and functionalities such as jpeg
decode, screen saver, calibration etc. The graphics engine interprets commands from the MPU
host via a 4 Kbyte FIFO in FT801 memory at RAM_CMD. The MPU/MCU writes commands into
the FIFO, and the graphics engine reads and executes the commands. The MPU/MCU updates
register REG_CMD_WRITE to indicate that there are new commands in the FIFO, and the
graphics engine updates REG_CMD_READ after commands have been executed.
Main features supported are:
Drawing of widgets such as buttons, clock, keys, gauges, text displays, progress bars,
sliders, toggle switches, dials, gradients, etc.
JPEG decode (Only baseline is supported)
Inflate functionality (zlib inflate is supported)
Timed interrupt (generate an interrupt to host processor after a specified number of
milliseconds)
In built animated functionalities such as displaying logo, calibration, spinner, screen
saver and sketch
Snapshot feature to capture the current graphics display
For a complete list of graphics engine display commands and widgets

FT800_FT801_Programmer_Guide [FTDI Document FT_000793], Chapter 4.
refer
to
20

4.3.2 ROM and RAM Fonts

The FT801 has built in ROM character bitmaps as font metrics. The graphics engine can use
these metrics when drawing text fonts. There are total 16 ROM fonts, numbered with font
handle 16-31. The user can define and load customized font metrics into RAM_G, which can be
used by display command with handle 0-15.
Each font metric block has a 148 byte font table which defines the parameters of the font and
the pointer of font image. The font table format is shown in Table 4-6.
Table 4-6 Font table format
Address Offset
0
128
132
136
140
144
Size(byte)
128
4
4
4
4
4
Parameter Description
width of each font character, in pixels
font bitmap format, for example L1, L4 or L8
font line stride, in bytes
font width, in pixels
font height, in pixels
pointer to font image data in memory
The ROM fonts are stored in the memory space ROM_FONT. The ROM font table is also stored
in the ROM. The starting address of ROM font table for font index 16 is stored at
ROM_FONT_ADDR, with other font tables follow. The ROM font table and individual character
width (in pixel) are listed in Table 4-7 through Table 4-9. Font index 16, 18 and 20-31 are for basic
ASCII characters (code 0-127), while font index 17 and 19 are for Extended ASCII characters (code 128255). The character width for font index 17 or 19 is fixed at 8 pixels for any of the Extended ASCII
characters.
Table 4-7 ROM font table

24
L1
3
24
29
25
L1
4
30
38
26
L4
6
12
16
FCD3C
FBD7C
FA17C
F7E3C
F3D1C
F201C
27
L4
8
16
20
28
L4
9
18
25
29
L4
11
22
28
30
L4
14
28
36
31
L4
18
36
49
BB23C
23
L1
3
17
22
D2C3C
22
L1
2
14
20
E01BC
21
L1
2
13
17
E7F9C
20
L1
2
10
13
EDC1C
19
L1
1
8
16
FDAFC
FFBFC
18
L1
1
8
16
FE7FC
Image pointer
start address
(hex)
17
L1
1
8
8
FEFFC
16
L1
1
8
8
FF7FC
Font Index
Font format
Line stride
Font width
Font height
Table 4-8 ROM font ASCII character width in pixels
ASCII Character width in pixels
Font Index =>

0
NULL
1
SOH
2
STX
3
ETX
4
EOT
5
ENQ
6
ACK
7
BEL
8
BS
9
HT
10
LF
11
VT
12
FF
13
CR
14
SO
15
SI
16
-
18
-
20
-
21
-
22
-
23
-
24
-
25
-
26
-
27
-
28
-
29
-
30
-
31
21

Font Index =>
16
DLE
17
DC1
18
DC2
19
DC3
20
DC4
21
NAK
22
SYN
23
ETB
24
CAN
25
EM
26
SUB
27
ESC
28
FS
29
GS
30
RS
31
US
32
space
33
!
34
"
35
#
36
$
37
%
38
&
39
'
40
(
41
)
42
*
43
+
44
,
45
46
.
47
/
48
0
49
1
50
2
51
3
52
4
53
5
54
6
55
7
56
8
57
9
58
:
59
;
60
<
61
=
62
>
63
?
64
@
65
A
66
B
67
C
68
D
69
E
70
F
71
G
72
H
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
18
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
20
3
3
4
6
6
9
8
2
4
4
4
6
3
4
3
3
6
6
6
6
6
6
6
6
6
6
3
3
6
5
6
6
11
7
7
8
8
7
6
8
8
21
4
4
5
8
8
12
10
3
5
5
7
9
3
4
3
4
8
8
8
8
8
8
8
8
8
8
3
4
8
9
8
8
13
9
9
10
10
9
8
11
10
22
5
5
6
9
9
14
11
3
6
6
6
10
4
5
4
5
9
9
9
9
9
9
9
9
9
9
4
4
10
10
10
9
17
11
11
12
12
11
10
13
12
23
5
6
5
10
10
16
13
3
6
6
7
10
5
6
5
5
10
10
10
10
10
10
10
10
10
10
5
5
10
11
10
10
18
13
13
14
14
13
12
15
14
24
6
6
8
14
13
22
17
6
8
8
10
14
6
8
6
7
13
13
13
13
13
13
13
13
13
13
6
6
15
15
15
12
25
17
17
18
18
16
14
19
18
25
9
9
12
19
18
29
22
6
11
11
13
19
9
11
9
9
18
18
18
18
18
18
18
18
18
18
9
9
19
19
19
18
34
22
22
24
24
22
20
25
24
26
3
4
5
9
8
10
9
3
5
5
6
8
3
6
4
6
8
8
8
8
8
8
8
8
8
8
4
4
7
8
7
7
13
9
9
9
9
8
8
9
10
27
4
4
6
11
10
12
11
4
6
6
7
10
4
8
5
7
10
10
10
10
10
10
10
10
10
10
4
4
9
10
9
8
15
11
11
11
12
9
9
12
12
28
5
6
8
13
12
15
13
5
7
7
9
12
5
9
6
9
12
12
12
12
12
12
12
12
12
12
5
5
11
12
11
10
19
13
13
13
14
12
12
14
15
29
6
6
9
15
14
18
15
5
8
8
10
14
5
11
6
10
14
14
14
14
14
14
14
14
14
14
6
6
12
14
13
11
21
15
15
15
16
13
13
16
17
30
8
8
11
19
18
23
19
7
11
10
13
18
7
14
8
13
17
17
17
17
17
17
17
17
17
17
8
8
16
17
16
15
28
20
20
20
21
17
17
21
22
31
10
11
15
26
24
31
26
9
14
14
18
24
9
19
11
17
24
24
24
24
24
24
24
24
24
24
11
11
21
24
22
20
38
27
27
27
28
23
23
28
30
22

Font Index =>
73
I
74
J
75
K
76
L
77
M
78
N
79
O
80
P
81
Q
82
R
83
S
84
T
85
U
86
V
87
W
88
X
89
Y
90
Z
91
[
92
\
93
]
94
^
95
_
96
`
97
a
98
b
99
c
100
d
101
e
102
f
103
g
104
h
105
i
106
j
107
k
108
l
109
m
110
n
111
o
112
p
113
q
114
r
115
s
116
t
117
u
118
v
119
w
120
x
121
y
122
z
123
{
124
|
125
}
126
~
127
DEL
16
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
18
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
20
3
5
7
6
9
8
8
7
8
7
7
5
8
7
9
7
7
7
3
3
3
6
6
3
5
6
5
6
5
4
6
6
2
2
5
2
8
6
6
6
6
4
5
4
5
6
8
6
5
5
3
3
3
7
0
21
4
7
9
8
12
10
11
9
11
10
9
9
10
9
13
9
9
9
4
4
4
7
8
5
8
7
7
8
8
4
8
8
3
3
7
3
11
8
8
8
8
5
7
4
7
7
10
7
7
7
5
3
5
8
0
22
4
8
11
9
13
12
13
11
13
12
11
10
12
11
15
11
11
10
5
5
5
8
9
6
9
9
8
9
9
5
9
9
3
4
8
3
14
9
9
9
9
5
8
5
9
8
12
8
8
8
6
4
6
10
0
23
6
10
13
11
16
14
15
13
15
14
13
12
14
13
18
13
13
12
5
5
5
9
11
4
11
11
10
11
10
6
11
10
4
4
9
4
16
10
11
11
11
6
9
6
10
10
14
10
10
9
6
5
6
10
0
24
8
13
18
14
21
18
18
16
18
17
16
16
18
17
22
17
16
15
7
7
7
12
14
7
13
14
12
14
13
8
14
13
6
6
12
6
20
14
13
14
14
9
12
8
14
13
18
12
13
12
8
6
8
14
0
25
9
16
22
18
27
24
25
22
26
24
22
20
24
22
31
22
22
20
9
9
9
16
18
11
18
18
16
18
18
9
18
18
7
7
16
7
27
18
18
18
18
11
16
9
18
16
23
16
16
16
11
9
11
19
0
26
4
8
9
8
12
10
10
9
10
9
9
9
9
12
9
9
8
4
6
4
6
7
4
8
8
7
8
7
5
8
8
4
4
8
4
12
8
8
8
8
5
7
5
8
7
11
7
7
7
5
3
5
10
3
2
27
5
9
11
9
15
12
12
11
12
11
10
10
12
11
15
11
11
10
5
7
5
7
8
5
9
10
9
10
9
6
10
10
4
4
9
4
15
10
10
10
10
6
9
6
10
9
13
9
9
9
6
4
6
12
4
28
6
12
14
12
18
15
14
13
15
13
13
13
14
14
18
13
13
13
6
9
6
9
10
7
12
12
11
12
11
8
12
12
5
5
11
5
18
12
12
12
12
7
11
7
12
11
16
11
11
11
7
5
7
14
5
29
7
13
15
13
21
17
16
15
17
15
15
14
16
15
21
15
15
14
7
10
6
10
11
8
13
14
13
14
13
9
14
14
6
6
13
6
21
14
14
14
14
8
13
8
14
12
18
12
12
12
8
6
8
16
6
30
9
17
20
17
27
22
21
20
22
20
19
19
21
20
27
20
20
19
8
13
8
13
15
10
17
18
16
18
16
11
18
18
8
8
16
8
27
18
18
18
18
11
16
10
18
16
23
16
16
16
11
8
11
21
8
31
12
23
27
23
36
30
29
27
29
27
26
25
28
27
36
27
27
25
11
18
11
18
20
13
23
24
22
24
22
15
24
24
11
11
22
11
37
24
24
24
24
15
22
13
24
21
32
21
21
21
14
10
14
29
10
23

Table 4-9 ROM font Extended ASCII characters
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
Symbol
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
Decimal
Symbol
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
Decimal
Symbol
Decimal
Symbol
Decimal
Symbol
Decimal
Symbol
Decimal
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
Decimal
Symbol
Symbol
Decimal
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
nbsp
Note: Font 17 and 19 are extended ASCII characters, with width fixed at 8 pixels for all characters.
Note: All fonts included in the FT801 ROM are widely available to the market-place for general usage, see
section nine for specific copyright data and links to the corresponding license agreements.
4.4 Parallel RGB Interface

The RGB parallel interface consists of 23 signals - DISP, PCLK, VSYNC, HSYNC, DE, 6 signals
each for R, G and B.
Several registers configure the LCD operation of these signals as follow:
REG_PCLK is the PCLK divisor the default is 0, and disables the PCLK output.
PCLK frequency = System Clock frequency / REG_PCLK
PCLK_POL define the clock polarity, =0 for positive active clock edge, and 1 for negative clock
edge.
REG_CSPREAD controls the transition of RGB signals with respect to PCLK active clock edge.
When REG_CSPREAD=0, R[7:2],G[7:2] and B[7:2] signals change following the active edge of
PCLK. When REG_CSPREAD=1, R[7:2] changes a PCLK clock early and B[7:2] a PCLK clock
later, which helps reduce the switching noise.
REG_DITHER enables colour dither; the default is enabled. This option improves the half-tone
appearance on displays. Internally, the graphics engine computes the colour values at an 8 bit
precision; however, the LCD colour at a lower precision is sufficient. The FT801 output is only 6
bits per colour in 6:6:6 formats and a 2X2 dither matrix allow the truncated bits to contribute
to the final colour values.
REG_OUTBITS gives the bit width of each colour channel, the default is 6, 6, 6 bits for each
RGB colour. A lower value means fewer bits are output for each channel allowing dithering on
lower precision LCD displays.
REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route
different LCD panel arrangements. Bit 0 of the register causes the order of bits in each colour
channel to be reversed. Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels
24

to be swapped. Setting Bit 3 allows rotation to be enabled. If Bit 3 is set, then (R,G,B) is
rotated right if bit 2 is one, or left if bit 2 is zero.
Table 4-10 REG_SWIZZLE RGB Pins Mapping
REG_SWIZZLE
b3 b2 b1 b0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
X
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
R7, R6, R5,

R4, R3, R2
R[7:2]
R[2:7]
B[7:2]
B[2:7]
G[7:2]
G[2:7]
G[7:2]
G[2:7]
B[7:2]
B[2:7]
R[7:2]
R[2:7]
PINS
G7, G6, G5,
G4, G3, G2
G[7:2]
G[2:7]
G[7:2]
G[2:7]
B[7:2]
B[2:7]
R[7:2]
R[2:7]
R[7:2]
R[2:7]
B[7:2]
B[2:7]
B7, B6, B5, B4,

B3, B2
B[7:2]
B[2:7]
R[7:2]
R[2:7]
R[7:2]
R[2:7]
B[7:2]
B[2:7]
G[7:2]
G[2:7]
G[7:2]
G[2:7]
Power on Default
25

4.5 Miscellaneous Control
4.5.1 Backlight Control Pin

The backlight control pin is a pulse width modulated (PWM) signal controlled by two registers:
REG_PWM_HZ and REG_PWM_DUTY. REG_PWM_HZ specifies the PWM output frequency, the
range is 250-10000 Hz. REG_PWM_DUTY specifies the duty cycle; the range is 0-128. A value
of 0 means that the PWM is completely off and 128 means completely on.
4.5.2 DISP Control Pin

The DISP pin is a general purpose output that can be used to enable or as a reset control to LCD display
panel. The pin is controlled by writing to Bit 7 of REG_GPIO register.
4.5.3 General Purpose IO pins

The GPIO1 and GPIO0 pins are default inputs. Write '1' to Bit 1 and 0 of REG_GPIO_DIR to change to
output pins respectively. In IC mode the GPIO0 is used as SA2 and is not available as GPIO.
GPIO1 and GPIO0 are read from or write to bit 1 and 0 of REG_GPIO register. GPIO1 is recommended to
be used as shutdown control for audio power amplifier.
4.5.4 Pins Drive Current Control

The output drive current of output pins can be changed as per the following table by writing to bit[6:2] of
REG_GPIO register:
Table 4-11 Output drive current selection

REG_GPIO
Bit[6:5]
Bit[4]
Bit[3:2]
Value
00b#
01b
10b
11b
0b#
1b
00b#
01b
10b
11b
Drive
Current
4mA
8mA
12mA
16mA
4mA
8mA
4mA
8mA
12mA
16mA
Pins
GPIO1
PCLK
MISO
GPIO0
DISP
INT_N
VSYNC
HSYNC
DE
R7..R2
G7..G2
B7..B2
BACKLIGHT
Note: #Default value
26

4.6 Audio Engine

FT801 provides mono audio output through a PWM output pin, AUDIO_L. It outputs the two
audio sources, the sound synthesizer and audio file playback.
4.6.1 Sound Synthesizer

A sound processor, AUDIO ENGINE, generates the sound effects from a small ROM library of
waves table. To play a sound effect listed in Table 4.3, load the REG_SOUND register with a
code value and write 1 to the REG_PLAY register. The REG_PLAY register reads 1 while the
effect is playing and returns a 0 when the effects end. Some sound effects play continuously
until it is interrupted or commanded to play the next sound effect. To interrupt an effect, write
a new value to REG_SOUND and REG_PLAY registers; e.g. write 0 (Silence) to REG_SOUND
and 1 to PEG_PLAY to stop the sound effect.
The sound volume is controlled by register REG_VOL_SOUND. The 16-bit REG_SOUND register
takes an 8-bit sound in the low byte. For some sounds, marked "pitch adjust" in the table
below, the high 8 bits contain a MIDI note value. For these sounds, note value of zero
indicates middle C. For other sounds the high byte of REG_SOUND is ignored.
Table 4-12 Sound Effect
Value
Effect
Conti
nuous
Y
00h
Silence
Y
01h
square wave
Y
02h
sine wave
Y
03h
sawtooth wave
Y
04h
triangle wave
Y
05h
Beeping
Y
06h
Alarm
Y
07h
Warble
Y
08h
Carousel
N
10h
1 short pip
N
11h
2 short pips
N
12h
3 short pips
N
13h
4 short pips
N
14h
5 short pips
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
6 short pips
7 short pips
8 short pips
9 short pips
10 short pips
11 short pips
12 short pips
13 short pips
14 short pips
15 short pips
16 short pips
23h
2Ch
30h
31h
DTMF #
DTMF *
DTMF 0
DTMF 1
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Pitch
adjust
N
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Value
Effect
32h
33h
34h
35h
36h
37h
38h
39h
40h
41h
42h
43h
44h
DTMF 2
DTMF 3
DTMF 4
DTMF 5
DTMF 6
DTMF 7
DTMF 8
DTMF 9
harp
xylophone
tuba
glockenspiel
organ
45h
trumpet
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
46h
47h
48h
49h
50h
51h
52h
53h
54h
55h
56h
piano
chimes
music box
bell
click
switch
cowbell
notch
hihat
kickdrum
pop
N
N
N
N
57h
58h
60h
61h
clack
chack
mute
unmute
Conti
nuous
Y
Y
Y
Y
Y
Y
Y
Y
N
N
N
N
N
N
Pitch
adjust
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
Y
Y
Y
Y
N
N
N
N
N
N
N
N
N
N
N
N
N
N
27

Table 4-13 MIDI

MIDI
ANSI
note
note
21
A0
22
A#0
23
B0
24
C1
25
C#1
26
D1
27
D#1
28
E1
29
F1
30
F#1
31
G1
32
G#1
33
A1
34
A#1
35
B1
36
C2
37
C#2
38
D2
39
D#2
40
E2
41
F2
42
F#2
43
G2
44
G#2
45
A2
46
A#2
47
B2
48
C3
49
C#3
50
D3
51
D#3
52
E3
53
F3
54
F#3
55
G3
56
G#3
57
A3
58
A#3
59
B3
60
C4
61
C#4
62
D4
63
D#4
64
E4
Note Effect
Freq
(Hz)
27.5
29.1
30.9
32.7
34.6
36.7
38.9
41.2
43.7
46.2
49.0
51.9
55.0
58.3
61.7
65.4
69.3
73.4
77.8
82.4
87.3
92.5
98.0
103.8
110.0
116.5
123.5
130.8
138.6
146.8
155.6
164.8
174.6
185.0
196.0
207.7
220.0
233.1
246.9
261.6
277.2
293.7
311.1
329.6
MIDI
note
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
ANSI
note
F4
F#4
G4
G#4
A4
A#4
B4
C5
C#5
D5
D#5
E5
F5
F#5
G5
G#5
A5
A#5
B5
C6
C#6
D6
D#6
E6
F6
F#6
G6
G#6
A6
A#6
B6
C7
C#7
D7
D#7
E7
F7
F#7
G7
G#7
A7
A#7
B7
C8
Freq (Hz)
349.2
370.0
392.0
415.3
440.0
466.2
493.9
523.3
554.4
587.3
622.3
659.3
698.5
740.0
784.0
830.6
880.0
932.3
987.8
1046.5
1108.7
1174.7
1244.5
1318.5
1396.9
1480.0
1568.0
1661.2
1760.0
1864.7
1975.5
2093.0
2217.5
2349.3
2489.0
2637.0
2793.8
2960.0
3136.0
3322.4
3520.0
3729.3
3951.1
4186.0
28

4.6.2 Audio Playback

The FT801 can play back recorded sound through its audio output. To do this, load the original
sound data into the FT801s RAM, and set registers to start the playback.
The registers controlling audio playback are:
REG_PLAYBACK_START:
the start address of the audio data
REG_PLAYBACK_LENGTH:
the length of the audio data, in bytes
REG_PLAYBACK_FREQ:
the playback sampling frequency, in Hz
REG_PLAYBACK_FORMAT:
the playback format, one of LINEAR SAMPLES, uLAW

SAMPLES, or ADPCM SAMPLES
REG_PLAYBACK_LOOP:
if zero, sample is played once. If one, sample is repeated

indefinitely
REG_PLAYBACK_PLAY:
a write to this location triggers the start of audio playback,

regardless of writing 0 or 1. Read back 1 when playback
is ongoing, and 0 when playback finishes
REG_VOL_PB:
playback volume, 0-255
The mono audio format supported is 8-bits PCM, 8-bits uLAW and 4-bits IMA-ADPCM. For
ADPCM_SAMPLES, each sample is 4 bits, so two samples are packed per byte, first sample is in
bits 0-3 and the second is in bits 4-7.
The current audio playback read pointer can be queried by reading
the
REG_PLAYBACK_READPTR. Using a large sample buffer, looping, and this read pointer, the
host MPU/MCU can supply a continuous stream of audio.
4.7 Touch-Screen Engine

The Capacitive Touch Screen Engine (CTSE) of FT801 communicates with external capacitive
touch panel module (CTPM) through I2C interface. The CTPM will assert its interrupt line when
there is a touch detected. Upon detecting CTP_INT_N line active, the FT801 will read the touch
data through I2C. Up to 5 touches can be reported and stored in FT801 registers. FT801
currently supports CTPM with FT5x06 or IQS5xx drive chip.
3.3V
FT801
4.7K
4.7K
CTP_SCL
SCL
CTP_SDA
SDA
CTP_INT_N
INTN
CTP_RST_N
RSTN
Capacitive Touch
Panel Module
10K
GND
Figure 4-7 Touch screen connection
29

The host controls the CTSE operation mode by writing the REG_CTOUCH_MODE.
Table 4-14 Touch Controller Operating Mode
REG_CTOUCH_MODE
Mode
Description
OFF
Acquisition stopped
ONE-SHOT
Perform acquisition once every time MPU write '1' to

REG_CTOUCH_MODE.
Reserved
Reserved
CONTINUOUS
Perform acquisition continuously at the reporting rate of the

connected CTPM.
The FT801 CTSE supports compatibility mode and extended mode. By default the CTSE runs in
compatibility mode where the touch system provides an interface very similar to the FT800s.
In this mode the same application code can run on FT800 and FT801 without alteration. In
extended mode, the touch register meanings are modified, and a second set of registers are
exposed. These allow multi-touch detection.
4.7.1 Compatibility mode

The CTSE reads the X and Y coordinates from CTPM and writes to register
REG_CTOUCH_RAW_XY. If the touch screen is not being pressed, both registers read 65535
(FFFFh).
These touch values are transformed into screen coordinates using the matrix in registers
REG_CTOUCH_TRANSFORM_A-F. The post-transform coordinates are available in register
REG_CTOUCH_SCREEN_XY. If the touch screen is not being pressed, both registers read 32768 (8000h). The values for REG_CTOUCH_TRANSFORM_A-F may be computed using an
on-screen calibration process.
If the screen is being touched, the screen coordinates are looked up in the screen's tag buffer,
delivering a final 8-bit tag value, in REG_TOUCH_TAG. Because the tag lookup takes a full
frame, and touch coordinates change continuously, the original (x; y) used for the tag lookup
is also available in REG_TOUCH_TAG_XY.
4.7.2 Extended mode

Setting REG_CTOUCH_EXTENDED to 1b0 enables extended mode. In extended mode a new
set of readout registers are available, allowing gesture and up to five touches to be read.
There are two classes of registers: control registers and status registers. Control registers are
written by MCU. Status registers can be read out by MCU and the FT801s hardware tag
system.
The
five
touch
coordinates
are
packed
in
REG_CTOUCH_TOUCH1_XY,
REG_CTOUCH4_X and REG_CTOUCH4_Y.
Coordinates stored in these registers are signed 16-bit values, so have range -32768 to 32767.
The no-touch condition is indicated by x=y= -32768. These coordinates are already
transformed into screen coordinates based on the raw data read from CTPM, using the matrix
in registers REG_CTOUCH_TRANSFORM_A-F. To obtain raw (x,y) coordinates read from CTPM,
the user sets the REG_CTOUCH_TRANSFORM_A-F registers to the identity matrix.
30

The FT801 tag mechanism is implemented by hardware, and can only query a single (x,y)
location. REG_TOUCH_TAG always reports the first touch, that is, the (x,y) from
REG_CTOUCH_TOUCH0_XY.
4.8 Power Management

4.8.1 Power supply
The FT801 may be operated with a single supply of 3.3V apply to VCC and VCCIO pins. For
operation with host MPU/MCU at lower supply, connect the VCCIO to MPU power to match the
interface power.
Table 4-15 Power supply
Symbol
Typical
Description
VCCIO
1.8V, or 2.5V, or 3.3V
Supply for Host interface digital I/O

pad only, LCD RGB interface supply
from VCC.
VCC
3.3V
Supply for chip
4.8.2 Internal Regulator and POR

The 1.2V internal regulator provides power to the core circuit. The regulator is disabled when
device is in POWERDOWN state. Power down is activated either by the SCU command write or
by holding down the PD_N pin for at least 5mS to allow the 1.2V decoupling capacitor to
discharge fully. The regulator is enabled only by releasing the PD_N pin. A 47k resistor is
recommended to pull the PD_N pin up to VCCIO, together with a 100nF capacitor to ground in
order to delay the 1.2V regulator powering up after the VCC and VCCIO are stable.
The 1.2V internal regulator requires a compensation capacitor to be stable. A typical design
puts a 4.7uF capacitor with ESR >0.5 is required between VCC1V2 to GND pins. Do not
connect any load to this pin.
The 1.2V regulator will generate Power-On-Reset (POR) pulse when the output voltage rises
above the POR threshold. The POR will reset all the core digital circuits.
It is possible to use PD_N pin as an asynchronous hardware reset input. Drive PD_N low for at
least 5ms and then drive it high will reset the FT801 chip.
31

VCCIO
VCC
1.2V
R
47k
Cin
10uF
GND
VCC1V2
FT801
Ccomp
4.7uF
GND
GND
PD_N
GND
100nF
VCC
GND
Figure 4-8 1.2V regulator
32

4.8.3 Power Modes

When supply to VCCIO and VCC is applied, internal 1.2V regulator is powered by VCC. An
internal POR pulse will be generated during the regulator power up until it is stable. After the
initial power up, the FT801 will stay in STANDBY state. When needed, host can set FT801 to
ACTIVE state by performing a dummy read to address 0. The graphics engine, the audio
engine and the touch engine are only functional in ACTIVE state. To save power host can send
command to put FT801 into any of the low power mode: STANDBY, SLEEP and POWERDOWN.
In addition, host is allowed to put FT801 in POWERDOWN mode by drive PD_N pin to low,
regardless what current state it is in. Refer to Figure 4-9 for the power state transitions.
Toggle PD_N from high

to low
VCC/VCCIO
Power ON
Toggle PD_N from low

to high
POWERDOWN
STANDBY
Dummy Read 0
Write command POWERDOWN
Toggle PD_N from high to low or
Toggle PD_N from high

to low
Write command
STANDBY
Dummy Read 0
SLEEP
ACTIVE
Write command SLEEP
Figure 4-9 Power State Transition
33

4.8.3.1 ACTIVE state

In ACTIVE state, the FT801 is in normal operation. The crystal oscillator and PLL are
functioning. The system clock applied to the FT801 core engines is enabled.
4.8.3.2 STANDBY state

In STANDBY state, the crystal oscillator and PLL remain functioning; the system clock
applied to the FT801 core engines is disabled. All register contents are retained.
4.8.3.3 SLEEP state

In SLEEP state, the crystal oscillator, PLL and system clock applied to the FT801 core
engines are disabled. All register contents are retained.
4.8.3.4 POWERDOWN state

In POWERDOWN state, the internal 1.2V regulator supplying the core digital logic, the
crystal oscillator, the PLL and the system clock applied to the FT801 core is disabled. All
register contents are lost and reset to default when the chip is next switched on.
4.8.3.5 Wake up to ACTIVE from other power states

Wake up from POWERDOWN state requires the host to pull the PD_N pin down and
release, a low to high transition enables the 1.2V regulator. POR generated when 1.2V
is stable and FT801 will switch to STANDBY mode after internal oscillator and PLL are up
(maximum 20ms from PD_N rising edge). The clock enable sequence mentioned in
section 4.2.3 shall be executed to proper enable the system clock.
From SLEEP state, host MPU reads at memory address 0 to wake the FT801 into
ACTIVE state. Host needs to wait for at least 20ms before accessing any registers or
commands. This is to guarantee the crystal oscillator and PLL are up and stable.
From STANDBY state, host MPU reads at memory address 0 to wake the FT801 into ACTIVE state.
Host can immediately access any register or command.
34

4.8.3.6 Pin Status at Different Power States

The FT801 pin status depends on the power state of the chip. See the following table
for more details. At power transition from ACTIVE to STANDBY or ACTIVE to SLEEP, all
pins retain their previous status. The software needs to set AUDIO_L, BACKLIGHT and
PCLK to a known state before issuing power transition commands.
Table 4-16 Pin Status
Pin Name
Reset State
Reset State
(VCC / VCCIO ON) Default
Output Drive Strength
Active/Standb
y/Sleep state
(VCC / VCCIO
ON)
Powerdown
state (VCC ON /
VCC1.2 OFF)
(VCC / VCCIO
ON)
AUDIO_L
Tristate Output
(hi-Z)
16mA
Output
Retain previous
state
SPI_SCLK/
I2C_SCL
Input (floating)
MISO/I2C
_SDA
Tristate Output
(hi-Z)
MOSI/I2C
_SA0
Hybrid Mode
(VCC OFF /
VCCIO ON)
Input
Input (floating)
Input/Output
Tristate Output
(hi-Z)
Input (floating)
Input
Input (floating)
CS_N/I2C
_SA1
Input (floating)
Input
Input (floating)
GPIO0/I2C
_SA2
Input (floating)
Input/Output
Tristate Output
(hi-Z)
GPIO1
Tristate Output
(hi-Z)
Input/Output
Tristate Output
(hi-Z)
MODE
Input
Input
Input (floating)
INT_N
Open Drain
Output (hi-Z)
Open Drain
Output
Tristate Output
(hi-Z)
PD_N
Input
Input
Input (floating)
X1/CLK
Input (floating)
Crystal
Oscillator
Input CLK
Input
Note: If
applicable,
external clock on
X1/CLK pin
should be
removed
X2
Output (hi-Z)
Crystal
Oscillator
Output
4mA
4mA
4mA
35

Continued
Pin Name
Reset State
(VCC/VCCIO ON)
CTP_RST_N
Reset State
(VCC/VCCIO ON)
Default Output
Drive
Active/Standby/
Sleep state
(VCC/VCCIO ON)
Powerdown state
(VCC ON/VCC1.2
OFF)
Tristate Output
(hi-Z)
Output
Retain Previous
State
CTP_INT_N
Tristate Output
(hi-Z)
Input
Retain Previous
State
CTP_SCL
Tristate Output
(hi-Z)
Input/Output
Retain Previous
State
CTP_SDA
Tristate Output
(hi-Z)
Input/Output
Retain Previous
State
BACKLIGHT
Output
4mA
Output
Retain Previous
State
DE
Output
4mA
Output
Output Low
VSYNC
Output
4mA
Output
Output Low
HSYNC
Output
4mA
Output
Output Low
DISP
Output
4mA
Output
Output Low
PCLK
Output
4mA
Output
Output Low
R(7:2), G(7:2),
B(7:2)
Output
4mA
Output
Output Low
Hybrid Mode
(VCC OFF/VCCIO
ON)
36

FT801 Memory Map
All memory and registers in the FT801 core are memory mapped in 22-bits address space with
2-bits SPI/I2C command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space,
0'b01 reserved for Host Commands and 0'b11 undefined. The following are the memory space
defined.
Table 5-1 FT801 Memory Map
Start
Address
End
Address
Size
00 0000h
03 FFFFh
256 kB
0C 0000h
0C 0003h
4B
NAME
Description
RAM_G
Main graphics RAM
ROM_CHIPID
FT801 chip identification and revision

information:
Byte [0:1] Chip ID: 0801
Byte [2:3] Version ID: 0100
0B B23Ch
0F FFFBh
275 kB
ROM_FONT
Font table and bitmap
0F FFFCh
0F FFFFh
4B
ROM_FONT_ADDR
Font table pointer address
10 0000h
10 1FFFh
8 kB
RAM_DL
Display List RAM
10 2000h
10 23FFh
1 kB
RAM_PAL
Palette RAM
10 2400h
10 257Fh
380 B
REG_*
Registers
10 8000 h
10 8FFFh
4 kB
RAM_CMD
Command buffer
1C 2000 h
1C 27FFh
2 kB
RAM_SCREENSHOT
Screenshot readout buffer
Note 1: The addresses beyond this table are reserved and shall not be read or written unless otherwise
specified.
Note 2: The ROM_CHIPID utilizes a part of shadow address from ROM_FONT address space.
37

5.1 FT801 Registers

Table 5.1 shows the complete list of the FT801 registers. Refer to FT80x Programmer
Guide (FTDI Doc FT_000793) Chapter 2 for details of the register function.
Table 5-2 Overview of FT801 Registers
Address
102400h
Register Name
REG_ID
Bit
s
Acc
ess
Reset
value
Description
r/o
7Ch
Identification register, always reads as

7Ch
102404h
REG_FRAMES
32
r/o
00000000h
Frame counter, since reset
102408h
REG_CLOCK
32
r/o
00000000h
Clock cycles, since reset
10240Ch
REG_FREQUENCY
27
r/w
2DC6C00h
102410h
REG_SCREENSHOT_EN
r/w
00h
102414h
REG_SCREENSHOT_Y
r/w
000h
102418h
REG_
SCREENSHOT_START
r/w
0h
Screenshot start trigger
10241Ch
REG_CPURESET
r/w
0h
Graphics, audio and touch engines

reset control
102420h
REG_TAP_CRC
32
r/o
102424h
REG_TAP_MASK
32
r/w
FFFFFFFFh
102428h
REG_HCYCLE
10
r/w
224h
Horizontal total cycle count
10242Ch
REG_HOFFSET
10
r/w
02Bh
Horizontal display start offset
102430h
REG_HSIZE
10
r/w
1E0h
Horizontal display pixel count
102434h
REG_HSYNC0
10
r/w
000h
Horizontal sync fall offset
102438h
REG_HSYNC1
10
r/w
029h
Horizontal sync rise offset
10243Ch
REG_VCYCLE
10
r/w
124h
Vertical total cycle count
102440h
REG_VOFFSET
10
r/w
00Ch
Vertical display start offset
102444h
REG_VSIZE
10
r/w
110h
Vertical display line count
102448h
REG_VSYNC0
10
r/w
000h
Vertical sync fall offset
10244Ch
REG_VSYNC1
10
r/w
00Ah
Vertical sync rise offset
102450h
REG_DLSWAP
r/w
0h
Display list swap control
102454h
REG_ROTATE
r/w
0h
Screen 180 degree rotate
102458h
REG_OUTBITS
r/w
1B6h
Main clock frequency

Set to enable screenshot mode
Y line number for screenshot
Live video tap crc. Frame CRC is

computed every DL SWAP.
Live video tap mask
Output bit resolution, 3x3x3 bits
38

Address
Register Name
Bit
s
Acc
ess
Reset
value
Description
10245Ch
REG_DITHER
r/w
1h
Output dither enable
102460h
REG_SWIZZLE
r/w
00h
102464h
REG_CSPREAD
r/w
1h
Output clock spreading enable
102468h
REG_PCLK_POL
r/w
0h
PCLK polarity:
Output RGB signal swizzle
0 = output on PCLK rising edge,

1 = output on PCLK falling edge
10246Ch
REG_PCLK
r/w
00h
PCLK frequency divider, 0 = disable
102470h
REG_TAG_X
r/w
000h
Tag query X coordinate
102474h
REG_TAG_Y
r/w
000h
Tag query Y coordinate
102478h
REG_TAG
r/o
00h
Tag query result
10247Ch
REG_VOL_PB
r/w
FFh
Volume for playback
102480h
REG_VOL_SOUND
r/w
FFh
Volume for synthesizer sound
102484h
REG_SOUND
16
r/w
0000h
102488h
REG_PLAY
r/w
0h
10248Ch
REG_GPIO_DIR
r/w
80h
Sound effect select

Start effect playback
GPIO pin direction,
0 = input , 1 = output
102490h
REG_GPIO
r/w
00h
GPIO pin value (bit 0,1,7);

output pin drive strength(bit 2-6)
102494h
Reserved
Reserved
102498h
REG_INT_FLAGS
r/o
00h
10249Ch
REG_INT_EN
r/w
0h
Global interrupt enable
1024A0h
REG_INT_MASK
r/w
FFh
Interrupt enable mask
1024A4h
REG_PLAYBACK_START
20
r/w
00000h
Audio playback RAM start address
1024A8h
REG_PLAYBACK_LENGTH
20
r/w
00000h
Audio playback sample length (bytes)
1024ACh
REG_PLAYBACK_READPT
R
20
r/o
1024B0h
REG_PLAYBACK_FREQ
16
r/w
1F40h
1024B4h
REG_PLAYBACK_FORMAT
r/w
0h
Audio playback format
1024B8h
REG_PLAYBACK_LOOP
r/w
0h
Audio playback loop enable
1024BCh
REG_PLAYBACK_PLAY
r/o
0h
Start audio playback
Interrupt flags, clear by read
Audio playback current read pointer
Audio playback sampling frequency

(Hz)
39

Address
Register Name
1024C0h
REG_PWM_HZ
1024C4h
REG_PWM_DUTY
1024C8h
Bit
s
Acc
ess
Reset
value
Description
14
r/w
00FAh
BACKLIGHT PWM output frequency

(Hz)
r/w
80h
BACKLIGHT PWM output duty cycle

0=0%, 128=100%
REG_MACRO_0
32
r/w
00000000h
Display list macro command 0
1024CCh
REG_MACRO_1
32
r/w
00000000h
Display list macro command 1
1024D0h
1024D4h
Reserved
1024D8h
REG_SCREENSHOT_BUS
Y
1024E0h
Reserved
1024E4h
REG_CMD_READ
12
r/w
000h
Command buffer read pointer
1024E8h
REG_CMD_WRITE
12
r/w
000h
Command buffer write pointer
1024ECh
REG_CMD_DL
13
r/w
0000h
1024F0h
REG_TOUCH_MODE
r/w
3h
Touch-screen sampling mode
1024F4h
REG_CTOUCH_EXTENDE
D
r/w
1h
Set capacitive touch operation mode:
64
Reserved
r/o
Screenshot ready flags
Reserved
Command display list offset
0: extended mode (multi-touch)

1: FT800 compatibility mode (single
touch).
1024F8h
REG_CTOUCH_REG
16
r/w
1770h
CTPM configure register write

Bit [7:0]: configure register address
Bit [15:8]: configure register value
1024FCh
102504h
Reserved
102508h
REG_CTOUCH_
32
Reserved
r/o
Compatibility mode: touch-screen raw

(x-MSB16; y-LSB16)
RAW_XY
Extended mode: touch-screen screen

data for touch 1 (x-MSB16; y-LSB16)
REG_CTOUCH_TOUCH1_
XY
10250Ch
REG_CTOUCH_TOUCH4_
Y
16
r/o

Y data for touch 4
102510h
REG_TOUCH_
32
r/o
Compatibility mode: touch-screen

screen (x-MSB16; y-LSB16)
SCREEN_XY

REG_CTOUCH_TOUCH0_
XY
102514h
REG_TOUCH_
32
r/o
Touch-screen screen (x-MSB16; y-
40

Address
Register Name
Bit
s
Acc
ess
Reset
value
Description
TAG_XY
102518h
REG_TOUCH_TAG
10251Ch
LSB16) used for tag lookup

8
r/o
REG_CTOUCH_TRANSFO
RM_A
32
r/w
00010000h
Touch-screen transform coefficient

(s15.16)
102520h
REG_CTOUCH_TRANSFO
RM_B
32
r/w
00000000h

(s15.16)
102524h
REG_CTOUCH_TRANSFO
RM_C
32
r/w
00000000h

(s15.16)
102528h
REG_CTOUCH_TRANSFO
RM_D
32
r/w
00000000h

(s15.16)
10252Ch
REG_CTOUCH_TRANSFO
RM_E
32
r/w
00010000h

(s15.16)
102530h
REG_CTOUCH_TRANSFO
RM_F
32
r/w
00000000h

(s15.16)
102534h
Reserved
102538h
REG_CTOUCH_TOUCH4_
X
10253Ch
102550h
Reserved
102554h
Touch-screen tag result
Reserved
r/o
Extended mode: touch-screen screen X

data for touch 4
Reserved
REG_SCREENSHOT_REA
D
r/w
102558h
102568h
Reserved
10256Ch
REG_TRIM
r/w
102570h
Reserved
Reserved
102574h
REG_CTOUCH_DIRECT_X
Y
r/o
Compatibility mode: Touch screen

direct (x-MSB16; y-LSB16)
conversions
16
32
0h
0h
REG_CTOUCH_DIRECT_Z
1Z2
32
r/o
REG_TRACKER
Internal relaxation clock trimming
Compatibility mode: Touch screen

direct (z1-MSB16; z2-LSB16)
conversions
REG_CTOUCH_TOUCH3_
XY
109000h
Reserved

REG_CTOUCH_TOUCH2_
XY
102578h
Set to enable readout of the

screenshot of the selected Y line
32
r/w
00000000h
Track register (Track value MSB16;

Tag value - LSB8)
41

Note: All register addresses are 4-byte aligned. The value in Bits column refers to the number of valid
bits from bit 0 unless otherwise specified; other bits are reserved.
42

Devices Characteristics and Ratings
6.1 Absolute Maximum Ratings

The absolute maximum ratings for the FT801 device are as follows. These are in accordance
with the Absolute Maximum Rating System (IEC 60134). Exceeding these may cause
permanent damage to the device.
Table 6-1 Absolute Maximum Ratings
Parameter
Value
Unit
Storage Temperature
-65 to +150
Floor Life (Out of Bag) At Factory Ambient
168
Hours
(30C / 60% Relative Humidity)
(IPC/JEDEC J-STD-033A MSL Level 3

Compliant)*
Ambient Temperature (Power Applied)
-40 to +85
VCC Supply Voltage
0 to +4
VCCIO Supply Voltage
0 to +4
DC Input Voltage
-0.5 to + (VCCIO + 0.3)
* If the devices are stored out of the packaging, beyond this time limit, the devices should be
baked before use. The devices should be ramped up to a temperature of +125C and baked
for up to 17 hours.
43

6.2 DC Characteristics
Table 6-2 Operating Voltage and Current
(Ambient Temperature = -40C to +85C)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
VCCIO
VCCIO operating
supply voltage
1.62
1.80
1.98
Normal Operation
2.25
2.50
2.75
2.97
3.30
3.63
VCC
VCC operating supply

voltage
2.97
3.30
3.63
Normal Operation
Icc1
Power Down current
1.0
Power down mode
Icc2
Sleep current
250
Sleep Mode
Icc3
Standby current
1.5
mA
Standby Mode
Icc4
Operating current
24
mA
Normal Operation
VCC1V2
Regulator Output
voltage
1.20
Normal Operation
Table 6-3 Digital I/O Pin Characteristics (VCC/VCCIO = +3.3V, Standard Drive Level)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Voh
Output Voltage High
2.4
Ioh=4mA
Vol
Output Voltage Low
0.4
Iol=4mA
Vih
Input High Voltage
2.0
Vil
Input Low Voltage
0.8
Vth
Schmitt Hysteresis
Voltage
0.3
0.45
0.5
Iin
Input leakage current
-10
10
uA
Ioz
Tri-state output
leakage current
-10
10
uA
Vin = VCCIO or 0
Vin = VCCIO or 0
44

Table 6-4 Digital I/O Pin Characteristics (VCCIO = +2.5V, Standard Drive Level)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Voh
Output Voltage High
VCCIO0.4
Ioh=4mA
Vol
Output Voltage Low
0.4
Iol=4mA
Vih
Input High Voltage
0.7 X
VCCIO
Vil
Input Low Voltage
0.3 X
VCCIO
Vth
Schmitt Hysteresis
Voltage
0.28
0.39
0.5
Iin
-10
10
uA
Ioz
Tri-state output
leakage current
-10
10
uA
Vin = VCCIO or 0
Vin = VCCIO or 0
Table 6-5 Digital I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level)
Parameter
Description
Minimum
Typical
Maximum
Units
Conditions
Voh
Output Voltage High
VCCIO0.4
Ioh=4mA
Vol
Output Voltage Low
0.4
Iol=4mA
Vih
Input High Voltage
0.7 X
VCCIO
Vil
Input Low Voltage
0.3 X
VCCIO
Vth
Schmitt Hysteresis
Voltage
0.25
0.35
0.5
-10
10
uA
-10
10
uA
Iin
Ioz
Tri-state output
leakage current
Vin = VCCIO or 0
Vin = VCCIO or 0
45

6.3 AC Characteristics
6.3.1 System clock
Table 6-6 System clock characteristics (Ambient Temperature = -40C to +85C)
Value
Parameter
Units
Minimum
Typical
Maximum
4.46
6.7
12.11
MHz
12
MHz
-2.5
+2.5
-3
+3
12.000
MHz
10
pF
Frequency
12.000
MHz
Duty cycle
45
50
55
3.3
Vp-p
Internal Relaxation Clock

Untrimmed frequency range
Trimmed frequency
Frequency tuning accuracy
Frequency variation over voltage and
temperature
Crystal
Frequency
X1/X2
Capacitance
External clock input
Input voltage on
X1/CLKIN
6.3.2 Host Interface SPI Mode 0
Figure 6-1 SPI Interface Timing
46

Table 6-7 SPI Interface Timing Specification

VCC(I/O)=1.8V
VCC(I/O)=2.5V
VCC(I/O)=3.3V
Min
Max
Min
Max
Min
Max
Parameter
Description
Units
Tsclk
SPI clock period
60
40
33
ns
Tsclkl
SPI clock low

duration
25
16
13
ns
Tsclkh
SPI clock high

duration
25
16
13
ns
Tsac
SPI access time
16
16
16
ns
Tisu
Input Setup
12
11
11
ns
Tih
Input Hold
ns
Tzo
Output enable delay
30
20
16
ns
Toz
Output disable delay
30
20
16
ns
Tod
Output data delay
24
15
12
ns
Tcsnh
CSN hold time
ns
6.3.3 Host Interface I2C Mode Timing

Table 6-8 I2C Interface Timing
StandardParameter
Fast-mode
Fast-plus
High speed
mode
mode
mode
Description
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Fscl
I2C SCL clock

frequency
100
400
1000
3400
kHz
Tscll
clock low period
4.7
1.3
0.5
0.16
Tsclh
clock high period
4.0
0.6
0.26
0.06
Tsu
Data setup time
250
100
50
10
ns
Thd
Data hold time
70
ns
Tr
Rise time
1000
300
120
10
40
ns
Tf
Fall time
300
300
120
10
40
ns
47

6.3.4 RGB Video Timing

Table 6-9 RGB Video timing characteristics
VCC=3.3V
Parameter
Description
Tpclk
Units
Min
Typ
Max
Pixel Clock period
78
104
ns
Tpclkdc
Pixel Clock duty cycle
40
60
Thc
Hsync to Clock
30
ns
Thwh
HSYNC width
41
Tpclk
10
Th
525
Tpclk
(REG_HSYNC1-REG_HSYNC0)
Tvwh
VSYNC width
(REG_VSYNC1-REG_VSYNC0)
Th
HSYNC Cycle
(REG_HCYCLE)
Tvsu
VSYNC setup
30
ns
Tvhd
VSYNC hold
10
ns
Thsu
HSYNC setup
30
ns
Thhd
HSYNC hold
10
ns
Tdsu
DATA setup
20
ns
Tdhd
DATA hold
10
ns
Tesu
DE setup
30
ns
Tehd
DE hold
10
ns
48

Figure 6-2 RGB Video Signal Timing
49

Application Examples
7.1 Examples of LCD Interface connection
Figure 7-1 FT801 Reference Design Schematic

50

Package Parameters
The FT801 is available in VQFN-48 package. The solder reflow profile for all packages is described in
following sections.
8.1 VQFN-48 Package Dimensions
Figure 8-1 VQFN-48 Package Dimensions
51

8.2 Solder Reflow Profile

The FT801 is supplied in a Pb free VQFN-48 package. The recommended solder reflow profile for the
package is shown in Figure 8-2.
Temperature, T (Degrees C)
tp
Tp
Critical Zone: when

T is in the range
TL to Tp
Ramp Up
TL
tL
TS Max
Ramp
Down
TS Min
tS
Preheat
25
T = 25 C to TP
Time, t (seconds)
Figure 8-2 FT801 Solder Reflow Profile

The recommended values for the solder reflow profile are detailed in Table 8-1. Values are shown for
both a completely Pb free solder process (i.e. the FT801 is used with Pb free solder), and for a non-Pb
free solder process (i.e. the FT801 is used with non-Pb free solder).
Table 8-1 Reflow Profile Parameter Values
Profile Feature
Average Ramp Up Rate (Ts to Tp)
Pb Free Solder Process
Non-Pb Free Solder Process
3C / second Max.
3C / Second Max.
Preheat
- Temperature Min (Ts Min.)
- Temperature Max (Ts Max.)
- Time (ts Min to ts Max)
150C
100C
200C
150C
60 to 120 seconds
60 to 120 seconds
217C
183C 60 to 150 seconds
Time Maintained Above Critical Temperature

TL:
- Temperature (TL)
60 to 150 seconds
- Time (tL)
Peak Temperature (Tp)
260C
240C
Time within 5C of actual Peak Temperature
20 to 40 seconds
20 to 40 seconds
6C / second Max.
6C / second Max.
8 minutes Max.
6 minutes Max.
(tp)
Ramp Down Rate
Time for T= 25C to Peak Temperature, Tp
52

FTDI Chip Contact Information
Head Office Glasgow, UK

Unit 1, 2 Seaward Place, Centurion Business Park
Glasgow G41 1HH
United Kingdom
Tel: +44 (0) 141 429 2777
Fax: +44 (0) 141 429 2758
E-mail (Sales)
E-mail (Support)
E-mail (General Enquiries)
sales1@ftdichip.com
support1@ftdichip.com
admin1@ftdichip.com
Branch Office Tigard, Oregon, USA

7130 SW Fir Loop
Tigard, OR 97223
USA
Tel: +1 (503) 547 0988
Fax: +1 (503) 547 0987
E-Mail (Sales)
E-Mail (Support)
E-Mail (General Enquiries)
us.sales@ftdichip.com
us.support@ftdichip.com
us.admin@ftdichip.com
Branch Office Shanghai, China

Branch Office Taipei, Taiwan
2F, No. 516, Sec. 1, NeiHu Road
Taipei 114
Taiwan, R.O.C.
Tel: +886 (0) 2 8797 1330
Fax: +886 (0) 2 8751 9737
E-mail (Sales)
E-mail (Support)
tw.sales1@ftdichip.com
tw.support1@ftdichip.com
tw.admin1@ftdichip.com
Room 1103, No. 666 West Huaihai Road,

Changning District
Shanghai, 200052
China
Tel: +86 21 62351596
Fax: +86 21 62351595
E-mail (Sales)
E-mail (Support)
cn.sales@ftdichip.com
cn.support@ftdichip.com
cn.admin@ftdichip.com
Web Site
http://www.ftdichip.com
Copyright and License Information for ROM fonts:

Copyright 1984-1989, 1994 Adobe Systems Incorporated.
Copyright 1988, 1994 Digital Equipment Corporation.
Adobe is a trademark of Adobe Systems Incorporated which may be

registered in certain jurisdictions.
Permission to use these trademarks is hereby granted only in
association with the images described in this file.
Copyright 2013 FTDI Chip Ltd.

Licensed under the Apache License, Version 2.0 (the License);
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an AS IS BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
53

System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology Devices
International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level performance
requirements. All application-related information in this document (including application descriptions, suggested FTDI devices and other
materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this information is subject to customer
confirmation, and FTDI disclaims all liability for system designs and for any applications assistance provided by FTDI. Use of FTDI
devices in life support and/or safety applications is entirely at the users risk, and the user agrees to defend, indemnify and hold
harmless FTDI from any and all damages, claims, suits or expense resulting from such use. This document is subject to change without
notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Neither the whole
nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material
or electronic form without the prior written consent of the copyright holder. Future Technology Devices International Ltd, Un it 1, 2
Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640
54

Appendix A References
Useful Application Notes
Appendix B - List of Figures and Tables

List of Figures
Figure 2-1 FT801 Block Diagram ..................................................................................................... 4
Figure 2-2 FT801 System Design Diagram ....................................................................................... 4
Figure 4-1 Host Interface Options ................................................................................................. 13
Figure 4-2 SPI Interface 1.8-3.3V connection ................................................................................. 14
Figure 4-3 SPI Interface 5V connection .......................................................................................... 14
Figure 4-4 Internal relaxation oscillator connection ......................................................................... 18
Figure 4-5 Crystal oscillator connection ......................................................................................... 19
Figure 4-6 External clock input ..................................................................................................... 19
Figure 4-7 Touch screen connection .............................................................................................. 29
Figure 4-8 1.2V regulator ............................................................................................................ 32
Figure 4-9 Power State Transition ................................................................................................. 33
Figure 6-1 SPI Interface Timing .................................................................................................... 46
Figure 6-2 RGB Video Signal Timing .............................................................................................. 49
Figure 7-1 FT801 Reference Design Schematic ............................................................................... 50
Figure 8-1 VQFN-48 Package Dimensions ...................................................................................... 51
Figure 8-2 FT801 Solder Reflow Profile .......................................................................................... 52
55

List of Tables
Table 3-1 FT801Q pin description.................................................................................................... 8
Table 4-1 Host memory read transaction (SPI) ............................................................................... 15
Table 4-2 Host memory write transaction (SPI) .............................................................................. 16
Table 4-3 Host command transaction (SPI) .................................................................................... 17
Table 4-4 Host Command Table .................................................................................................... 17
Table 4-5 Interrupt Flags bit assignment ....................................................................................... 18
Table 4-6 Font table format ......................................................................................................... 21
Table 4-7 ROM font table ............................................................................................................. 21
Table 4-8 ROM font ASCII character width in pixels ......................................................................... 21
Table 4-9 ROM font Extended ASCII characters .............................................................................. 24
Table 4-10 REG_SWIZZLE RGB Pins Mapping ................................................................................. 25
Table 4-11 Output drive current selection ...................................................................................... 26
Table 4-12 Sound Effect .............................................................................................................. 27
Table 4-13 MIDI Note Effect ......................................................................................................... 28
Table 4-14 Touch Controller Operating Mode .................................................................................. 30
Table 4-15 Power supply ............................................................................................................. 31
Table 4-16 Pin Status .................................................................................................................. 35
Table 5-1 FT801 Memory Map ...................................................................................................... 37
Table 5-2 Overview of FT801 Registers .......................................................................................... 38
Table 6-1 Absolute Maximum Ratings ............................................................................................ 43
Table 6-2 Operating Voltage and Current ....................................................................................... 44
Table 6-3 Digital I/O Pin Characteristics (VCC/VCCIO = +3.3V, Standard Drive Level) ......................... 44
Table 6-4 Digital I/O Pin Characteristics (VCCIO = +2.5V, Standard Drive Level) ................................ 45
Table 6-5 Digital I/O Pin Characteristics (VCCIO = +1.8V, Standard Drive Level) ................................ 45
Table 6-6 System clock characteristics (Ambient Temperature = -40C to +85C) .............................. 46
Table 6-7 SPI Interface Timing Specification .................................................................................. 47
Table 6-8 I2C Interface Timing ..................................................................................................... 47
Table 6-9 RGB Video timing characteristics .................................................................................... 48
Table 8-1 Reflow Profile Parameter Values ..................................................................................... 52
56

Appendix C - Revision History

Document Title:
FT801 Embedded Video Engine Datasheet
Document Reference No.:
FT_000986
Clearance No.:
FTDI#376
Product Page:
http://www.ftdichip.com/EVE.htm
Document Feedback:
DS_FT801
Version 1.0
Initial Draft Release
2014-03-17
Version 1.0
Initial Release
2014-07-14
57

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Future Technology Devices International Ltd.

Compatibility mode allows display code to be

Support for LCD display in WQVGA

The FT801 calculates for 8-bit colour despite

Display enable control output to LCD panel

Mono audio channel output with PWM output

Built-in sound synthesizer

Audio wave playback for mono 8-bit linear

Embedded Video Engine (EVE) with widget

Built-in graphics operations allow users with

PWM output for backlight dimming control

Support capacitive touch screen with up to 5

Hardware engine can recognize touch tags

Low power consumption for portable

No frame buffer RAM required

Advanced object oriented architecture

Power mode control allows chip to be put in

Supports host interface I/O voltage from

Standard serial interface to host MPU/MCU

Internal voltage regulator supplies 1.2V to

Available in a compact Pb-free, VQFN-48,

Enhanced sketch processing

Programmable interrupt controller provides

Built-in 12MHz crystal oscillator with PLL

Clock switch command for internal or

Video RGB parallel output (default RGB data

Copyright 2014 Future Technology Devices International Limited

Document No.: FT_000986

Copyright 2014 Future Technology Devices International Limited

Document No.: FT_000986

Point of Sales Machines

Home appliance devices

Home Security Systems

Graphic touch pad remote, dial pad

Sprinkler system displays

Tele / Video Conference Systems

Phones and Switchboards

Vending Machine Control Panels

Blood Pressure displays

and many more

Glucose level displays

1.1 Part Numbers

48 Pin VQFN, pitch 0.5mm, body 7mm x 7mm x 0.9mm

Table 1- Video Controller Part Numbers

Copyright 2014 Future Technology Devices International Limited

Document No.: FT_000986

FT801 Block Diagram

Figure 2-1 FT801 Block Diagram

Figure 2-2 FT801 System Design Diagram

Copyright 2014 Future Technology Devices International Limited

Document No.: FT_000986

Typical Applications ...................................................................... 3

FT801 Block Diagram.................................................................... 4

Device Pin Out and Signal Description .......................................... 7

VQFN-48 Package Pin Out ................................................................... 7

Pin Description ................................................................................... 8

Serial Host Interface ......................................................................... 13

SPI Interface ............................................................................................................. 15

Serial Data Protocol ................................................................................................... 15

Host Memory Read ..................................................................................................... 15

Host Memory Write .................................................................................................... 16

Host Command .......................................................................................................... 16