Logic Gates

Digital Logic and

Software Principles

History and development

The binary number system was refined by Gottfried Wilhelm Leibniz
(published in 1705) and he also established that by using the binary system, the principles
of arithmetic and logic could be combined. In an 1886 letter, Charles Sanders Peirce
described how logical operations could be carried out by electrical switching circuits.[7]
Eventually, vacuum tubes replaced relays for logic operations. Lee De Forest's modification,
in 1907, of the Fleming valve can be used as AND logic gate. Ludwig Wittgenstein
introduced a version of the 16-row truth table as proposition 5.101 of Tractatus LogicoPhilosophicus (1921). Walther Bothe, inventor of the coincidence circuit, got part of the
1954 Nobel Prize in physics, for the first modern electronic AND gate in 1924. Konrad
Zuse designed and built electromechanical logic gates for his computer Z1 (from 193538).
Claude E. Shannon introduced the use of Boolean algebra in the analysis and design of
switching circuits in 1937. Active research is taking place in molecular logic gates.

Logic
Formal logic is a branch of mathematics
that deals with true and false values
instead of numbers.

In 1840s, George Boole developed

many Logic ideas.

A logic gate performs a logical operation

on one or more logic inputs and produces a
single logic output.

Introduction
A logic gate is an idealized or physical device implementing a
Boolean function; that is, it performs a logical operation on one or
more logical inputs, and produces a single logical output. Depending
on the context, the term may refer to an ideal logic gate, one
that has for instance zero rise time and unlimited fan-out
, or it may refer to a non-ideal physical device. Logic gates are
primarily implemented using diodes or transistors acting as
electronic switches, but can also be constructed using
electromagnetic relays (relay logic), fluidic logic, pneumatic logic,
optics, molecules, or even mechanical elements. With
amplification, logic gates can be cascaded in the same way that
Boolean functions can be composed, allowing the construction of
a physical model of all of Boolean logic, and therefore, all of the
algorithms and mathematics that can be described with Boolean
logic.

Logic Signals
There are a number of different systems for representing binary
information in physical systems.
A voltage signal with zero (0) corresponding to 0 volts and one (1)
corresponding to five or three volts.
A sinusoidal signal with zero corresponding to some frequency,
and one corresponding to some other frequency.
A current signal with zero corresponding to 4 milliamps and one
corresponding to 20 milliamps.
And one last way is to use switches, OPEN for "0" and CLOSED for
"1".
( And there are more ways !)

AND gate
e.g. I get up if it is 8-00 a.m. AND it is a weekday he said if A = 8-00 a.m. B = weekday
and Y = get up then he said you can write:

Y A B
where the dot represents logical AND.
He went on to say that if 1 represents TRUE
and 0 represents FALSE
then the function can be defined in a truth table.

Truth Table
The truth table has an entry for each possible combination of inputs.
For n inputs there will be 2n entries 2 inputs = 4 entries.

We can have more than two inputs in which

case the only time we would have a 1 out is when
all the inputs are true.

Logic Gates

Symbol
The symbol adopted for the AND function ( gate) is shown below
American (MIL-STD-806)
British (IEC 617:12)

A
B

A
Y
B

Logic Gates

&

OR gate
e.g. I turn on my headlights if it is dark OR it is raining
if A = dark B = raining and Y = headlights on then:

Y A B
where the + sign represents logical OR.

Logic Gates

We can have more than two

inputs in which case the only
time we would have a 0 out is
when all the inputs are false.

American (MIL-STD-806)

British (IEC 617:12)

A
Y
B

Logic Gates

NOT gate
e.g. I turn on the heating if it is NOT hot
if A = hot and Y = Heating on then:

Y A

where the bar represents logical NOT.

We can only have one input and the output is always the opposite sign.

Logic Gates

American (MIL-STD-806)
British (IEC 617:12)

Exclusive OR EXOR gate

Logic Gates

Y A B

where the sign represents logical EXOR.

Note that the normal OR includes the case where we have both inputs true. The EXOR does not
include this case.
For more than two inputs the gate is defined as:
The output is TRUE if we have an odd number of inputs TRUE

The symbol adopted for the EXO

shown below
American (MIL-STD-806)
Logic Gates

Not AND NAND gate

Y A B

We can have more

than two inputs in
which case the only
time we would have a 0
out is when all the
inputs are true.

where the dot and

bar represents
logical NAND.
American (MIL-STD-806)

A
B

British (IEC 617:12)

A
Y

B
Logic Gates
Logic Gates

&

Not OR NOR gate

Y A B

We can have more

than two inputs in
which case the only
time we would have a 1
out is when all the
inputs are false.

where the + sign

and bar represents
logical NAND.
American (MIL-STD-806)

A
B

British (IEC 617:12)

Y
B
Logic Gates
Logic Gates

Universal Gates
NAND and NOR gates are referred to as
universal gates as the three basic gates can
be constructed using either one of the two.
This therefore implies that all logic circuits can
be constructed using either of the gates.
The notes show this process for NAND only but
it can be shown for NOR also.

Logic Gates

NOT using NANDs only

The Truth Table is for a NAND gate
If we tie the inputs of a NAND together then we
limit the possible input combinations to two, 1 1 and
0 0. These are shown on the table now if the input is
0 the output is 1 and vice versa
a NOT gate

Logic Gates
Logic Gates

AND using NANDs only

As a NAND is simply an AND followed by a NOT
gate (inverter) we can simply use a NAND
followed by NOT.
A
Y
B

Note more than one NAND gate to

produce the desired AND gate.
Logic Gates
Logic Gates

OR using NANDs only

A

B A B

This is our desired OR gate

Logic Gates

OR using NANDs only

A

B A B

If we now add NOT A and NOT B

into our table

OR using NANDs only

Logic Gates

B A B A

A B

If these are now ANDed together

OR using NANDs only

Logic Gates

B A B

A B

A B

Finally if we invert our result we see that the 3rd and 7th column are
identical. This means that if we invert the inputs then NAND then
we will end up with the OR function.

OR using NANDs only

A
Logic Gates

Let us examine the way in which logic gates can be used to

realise logic circuits:
Example

Logic Gates

A drill (D) is to operate if we are in automatic (A) and the system (S)
is running or if we are in manual (M) and a button (B) is pressed or
if an override (O) input is not operated.
The boolean (logic) expression for this can be written in the
following way:

D A S M B O

This can be constructed in the following way:

A
S
M

Logic Gates

Logic Gates

At this point let us examine different logic integrated circuits (I.C.s) families which
can be used to construct logic circuits.
Logic Families
Transistor-Transistor Logic (TTL) is a class of digital circuits built from bipolar
junction transistors (BJT), and resistors. It is called transistor-transistor logic
because both the logic gating function (e.g. AND) and the amplifying function are
performed by transistors (contrast this with RTL and DTL).
Transistor Transistor Logic TTL prefix 74 e.g. 7400Quad 2-input NAND

More Specifically

MM74XXX00P

MM Manufacturers codes
e.g.
SN Texas Instruments
CD
Harris Semiconductors
DM
Fairchild Semiconductors
M SGS-Thomson Microelectronics
Logic Gates

MC

Motorola
Transistor Transistor Logic TTL

XXX variants
e.g.
L
Low power
S Schottky high speed
LS
Low power Schottky
ALS
Advanced low power Schottky

Voltage range Speed

Power

LS +5V 5% 10nS
2 mW
ALS +5V 5% 7nS 1 mW
Transistor Transistor Logic TTL
Prefix 54 not 74 is used for higher specifications
( normally military )

Temperature Voltage supply

Logic Gates

range

tolerance

Commercial 74
0 - 70C 5 %
families
Military 54 families -55 - +125C 10 %
Transistor Transistor Logic TTL
Most TTL families
An input is recognised as 1 if the input is >2V
An input is recognised as 0 if the input is < 0.8V
Noise immunity is the difference = 1.2V
A low output has a maximum output of 0.2V
A high output has a minimum output of 3.3V
Available TTL Gate Packages
Quad 2-input gates
Logic Gates

7400 quad 2-input NAND

7403 quad 2-input NAND with open collector outputs

7408
7409

quad 2-input AND

quad 2-input AND with open collector outputs

7432 quad 2-input OR
7486 quad 2-input EX-OR
74132 quad 2-input NAND with Schmitt trigger inputs
7402 quad 2-input NOR
Triple 3-input gates

7410
7411
7412

triple 3-input NAND

triple 3-input AND

triple 3-input NAND with open collector outputs

7427 triple 3-input NOR
Dual 4-input gates

7420 dual 4-input NAND

7421 dual 4-input AND
Logic Gates

Others
7430 8- input NAND gate
Hex NOT gates

7404 hex NOT

7405 hex NOT with open collector outputs

7414 hex NOT with Schmitt trigger inputs

Complementary Metal Oxide Semiconductor Logic CMOS
Number sequence originally from 4000 upwards but not the same as TTL
Characteristics
Delay 50nS Power 1 W Voltage 3-18V
Input
Logic 1 is recognised above 2/3 Supply
Logic 0 is recognised below 1/3 Supply
Output
The minimum for logic 1 is Supply 0.01V
The maximum for logic 0 0.01V
Logic Gates

Available CMOS Gate Packages

Quad 2-input gates
4001 quad 2-input NOR
4011 quad 2-input NAND

4070 quad 2-input EX-OR

4071 quad 2-input OR
4077 quad 2-input EX-NOR
4081 quad 2-input AND
4093 quad 2-input NAND with Schmitt trigger inputs

CMOS Gate Packages

Triple 3-input gates
4023 triple 3-input NAND
Logic Gates

4025 triple 3-input NOR 4073

triple 3-input AND
4075 triple 3-input OR
Dual 4-input gates
4002 dual 4-input NOR
4012 dual 4-input NAND
4072 dual 4-input OR
4082 dual 4-input AND
4069 hex NOT (inverting buffer)

Developments in TTL and CMOS

Often there are different pin-outs in the two family
types.
Logic Gates

CMOS chips are available which are the same numbers

due to the popularity of TTL.
74HC

High speed CMOS operating 2V to 6V

74HCT

High speed CMOS with TTL compatible

supplies

74ACT

Advanced CMOS with TTL compatible levels

and pin-outs

74AC

Advanced CMOS with CMOS compatible

levels and TTL pin-outs

Logic Problem.
Logic Gates

Getting back to our example, we can see that we

would require:
2 x 2-input AND
7408 (4 x 2-input AND)
4081 (4 x 2-input AND )
1 x inverter (NOT) 7404 (6 x inverter)
4069 (6 x inverter )
1 x 3-input OR Not available?
4075 (3 x 3-input OR )
This is a total of 3 chips and we end up not using
9 gates within the packages.
Logic Gates

8 x 2-input NAND 2 x 7400

Logic Gates

1 x 3-input NAND 1 x 7410

again 3 chips.

BUT
By observation we can see that NANDs 2 and 3
simply invert 1s output then invert it again.
This means that they cancel each other out
and can be removed.
This is also true for NANDs 5 and 6 and
NANDs 8 and 9, leaving us with

Logic Gates

This requires:
2 x 2-input NAND 1 x 7400
1 x 3-input NAND 1 x 7410
With a little understanding of logic gates we
can reduce the requirements to only one chip
by using the fact that:
Logic Gates

So we need:
3 x 3-input NANDs1 x 7410

Note.
Conversions from AND, OR, NOT to NAND only
rarely produce a less complex circuit but
normally the complexity is similar. The
advantage lies in the fact that NAND chips
Logic Gates

are readily available and are inexpensive due

to the number sold and that any gates left
over can be used in other circuits as all
circuits use the same gate types.

Logic Circuits TTL and CMOS

Logic Gates

Transistor Transistor Logic (TTL) NAND Gate.

R1

a
b
c

R2

R4
Q3

Q1

Q2

D
Q4

R3

Complementary Metal Oxide Semiconductor CMOS NOR

Logic Gates

gate

Vs+
Input A

Q1

Input B
Q2

Output
Q4
Q3

Logic Gates

Logic Gates

This resource was created by the University of Wales Newport and released as an open educational resource
through the Open Engineering Resources project of the HE Academy Engineering Subject Centre. The Open
Engineering Resources project was funded by HEFCE and part of the JISC/HE Academy UKOER programme.

2009 University of Wales Newport

This work is licensed under a Creative Commons Attribution 2.0 License.

The JISC logo is licensed under the terms of the Creative Commons Attribution-Non-Commercial-No Derivative Works 2.0 UK:
England & Wales Licence. All reproductions must comply with the terms of that licence.
The HEA logo is owned by the Higher Education Academy Limited may be freely distributed and copied for educational purposes
only, provided that appropriate acknowledgement is given to the Higher Education Academy as the copyright holder and original
publisher.
The name and logo of University of Wales Newport is a trade mark and all rights in it are reserved. The name and logo should not
be reproduced without the express authorisation of the University.

Logic Gates