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3.
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Physical Design (PD) Interview Questions - Floorplanning ~ VLSI Basics And Interview Questions
A.
4.
A.
Die/Block Area
I/Os Placed
Macros placed
Power Pre-routing
Aspect ratio, Core utilization, Row/Core Ratio, Width and Height are the
floorplaning control parameters. For more information please visit Floorplaning Control
Parameters
6.
A.
7.
A.
Physical Design (PD) Interview Questions - Floorplanning ~ VLSI Basics And Interview Questions
8.
A.
9.
macro placement?
A. please visit Macro Placement post
10. What is blockage? What are the different types of blockages? How these
blockages are used in physical
design?
A. please visit Blockages and Halos Post
11. What is Halo? How it is useful?
Please visit Blockages and Halos Post
A.
12. What are the fly/flight lines? How these fly/flight lines are useful during
macroplacement ?
A. Please visit Macro Placement post
13.
First we have to decide about the power domains, and add the power rings for
Physical Design (PD) Interview Questions - Floorplanning ~ VLSI Basics And Interview Questions
A. Core utilization percentage indicates the amount of core area used for cell
placement. The number is
calculated as a ratio of the total cell area (for hard
macros and standard cells or soft macro cells) to the
core area. A core utilization
of 0.8, for example, means that 80% of the core area is used for cell placement and
20 percent is available for routing.
17. When core utilization area increased to 90%, macros got placed
outside core area so does it mean that increase in core utilization
area decreases width and height?
A. If you go on with 90% then there may be a problem of congestion and routing
problem. It means that you cant do routing within this area. Sometimes you can fit
within 90% utilization but while go on for timing
optimization like upsize and
adding buffers will lead to increase in size. So in this case you cant do anything so
we need to come back to floorplan again. So to be on safer side we are fixing to 70
to 80% utilization.
18. Why do we remove all placed standard cells, and then write out
floorplan in DEF format. What's use of DEF file?
A. DEF deals only with floorplan size. So to get the abstract of the floorplan, we are
doing like this. Saving and loading this file we can get this abstract again. We dont
need to redo floorplan.
Physical Design (PD) Interview Questions - Floorplanning ~ VLSI Basics And Interview Questions
Physical Design (PD) Interview Questions - Floorplanning ~ VLSI Basics And Interview Questions
Physical Design (PD) Interview Questions - Floorplanning ~ VLSI Basics And Interview Questions
Physical Design (PD) Interview Questions - Floorplanning ~ VLSI Basics And Interview Questions
Physical Design (PD) Interview Questions - Floorplanning ~ VLSI Basics And Interview Questions
Pin/pad location
Location and area of the soft macros and its pin locations
Note:- For block level Die size and Pin placement comes from TOP
Fly-line analysis is required before placing the macros
While fixing the location of the pin or pad always consider the surrounding
environment with which the
block or chip is interacting. This avoids routing
congestion and also benefits in effective circuit timing
Provide sufficient number of power/ground pads on each side of the chip for
effective power distribution.
In deciding the number of power/ground pads, Power report and IR-drop in the
design should also be
considered.
Orientation of these macros forms an important part of floorplaning.
Create standard cell placement blockage (Hard Blockage) at the corner of the
macro because this part
is more sensitive to routing congestion.
Using the proper aspect ratio (Width /Height) of the chip
for placing block-level pins:
First determine the correct layer for the pins
Spread out the pins to reduce congestion.
Avoid placing pins in corners where routing access is limited
Physical Design (PD) Interview Questions - Floorplanning ~ VLSI Basics And Interview Questions
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KHADAR BASHA
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