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Term Paper EEL (201):

Clock And Data Recovery Circuits
Kumar Nikhil, 4th Year Undergraduate, Mechanical Engineering Department, IIT Delhi

AbstractIn this term paper an analysis of the CDR circuit for

PLL transmission has been done. Some basic steps for design of
CDRs like transmission and phase detection have been discussed
here and also the most commonly used circuitry was analyzed by
me and the inferences hence drawn from the research.

II. TRANSMISSION
Two Types of transmitted data: Two main types of transmitted data are:--First, NRZ type (Non return to zero type)

I. INTRODUCTION

igh speed I/O is used to increase the bandwidth between

chips in a computer or network. The clock and data
recovery (CDR) module is responsible for reconstructing the
original transmitted bit-stream at the receiver. Serial data
transmission in forms of optical signals or waves leads to
distortion of the data

--Second, RZ type (Return to zero type)

Bandwidth data for NRZ data is less than that of RZ data.

Maximum bandwidth for NRZ data is 2Tb where Tb is inverse
of the bit rate (rb) or smallest time between two rising and
falling data.
Input Signal transmitted and what is received at the receiver

In many systems, data is transmitted or retrieved without any

additional timing reference. For example, in optical
communications, a stream of data flows over a single fiber
with no accompanying clock, but the receiver is required to
process this data synchronously. Therefore, the clock or
timing information must be recovered from the data at the
receiver

III. EDGE DETECTION

NRZ
EDGES
Edge Detection for NRZ data

Edge Detection can be done in several ways few of which

are given below:

Data

1) Making use of delay:

Din

Recovered Clock
Data and recovered clock

Mostly all clock recovery circuits employ some form of a

PLL. Following are the steps and some basic concept that
during my research of the topic I understood.

Dout

In line 2 we need to add a delay delta by any way we want.

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V. CODE DISPARITY

2) Differentiator and full wave rectifier:

3) Using flip flops: A Double Edge triggered flip flop can be

used for edge detection. Circuitry involved is shown in the
following diagram.

In an unbalanced code the disparity is can be without limits

but in balanced code since we put a bound to disparity it has a
maxima, which it cannot cross.

VI. PHASE DETECTION

I would be discussing only Linear Phase Detectors because
of the fact that I didnt understand the other types. Following
is a circuit diagram for Hogge Detector, which is the most
widely, used circuitry for the process. This type of detector is
also called Self Correcting Detector.

XVCO

A Hogges Phase Detector

Xvco
Above two are circuits for edge detection by using D flip flops
(double edge triggered).

The diagram above labels all the ports but we give input
data at D and recovered is Dout, which is fed back to reference.
Line from Q0 to D1 is A and that from Q1 is B. Output of the
first XOR gate is up and that of the second XOR gate is down.

IV. PHASE LOCKED CLOCK RECOVERY CIRCUIT

Phase locked clock recovery circuit

If the input data is periodic with certain frequency then the

edge detector doubles the frequency and locks the PLL at that
value. Now, if the output transitions are absent then the output
of the multiplier is zero and VCO control voltage begins to
decay causing the oscillator to deviate. To minimize the
deviation LPF >>> Maximum allowable time between two
transitions.

Output of different terminals

Above data is the response of the detector for a linear data

input. For above example clock rising edge is at the data
center.

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VII. ACCOUNTING FOR JITTER

Steps to account for Jitters in clock:1.) Measure the Jitters around the clock by using following
function

2.) Multiply these components with the Filter Mask.

3.) RMS total noise voltage over band.
4.) Convert RMS noise voltage to RMS jitter.
Above diagram shows the transfer characteristics and
following is the discussion of the same for Hogges Detector
Hogges Detector has linear gain characteristics and small
jitter generation due to phase detection. Phase detection gain is
.5 for 11001100 data transition density. It has a static phase
offset due to mismatch.
The Hogges Detector subtracts two pulses, each originating
from an XOR gate. A charge pump does the subtraction
indirectly. The XOR gate on the right generates a reference
pulse that is exactly half a bit time in width. The XOR gate on
the left generates a pulse whose width depends on the phase
error between the edges of Data and the edges of Drt. When
the phase difference between Data and Drt (and hence Clock)
is half a bit, the two pulses cancel each other thus generating
no change in the PD output. The linearity results from the net
pulse width at the output being linearly proportional to the
phase difference between the center of Data and the edges of
Clock. The saw-tooth shape of the transfer function is due to
phase being a modulo-2 quantity. Phase detector gain (KPD)
is defined as the slope of the transfer function where the phase
error is close to zero. The phase detector gain is typically 1
and is unitless. This Hogges PD allows the use of Linear
Systems Theory. But due to the use of Flip Flops and Gates
the rate for operations of this PD is limited to some best
possible case (I did not get any reference anywhere to that).
In general Phase Detectors produce a DC component
proportional to the deviation of sampling point from the center
of the bit cell. Binary Sized phase detectors are also called
bang bang detectors (not presented here).

VIII. FILTER MASK USED FOR JITTER CORRECTION

Above discussed Jitter Correction method needs a fliter mask.
The circuitry for the same is

Difficulties with filters are:

1. Temperature and frequency variation causing difficulty
in delay time calculation.
2. Difficulty in building of High Q filters.

IX. FILTER MASK USED FOR JITTER CORRECTION

After discussing the basic modules of the Clock Recovery
Circuits, following are the circuitry for few methods to
draw the outputs

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REFERENCES: 1. Information on Clock and Data Recovery Circuits

Hewlett-Packard Company Palo Alto, California
2. Doctorate report submitted to Department of
Electrical Engineering and committee of Graduate
studies on Estimation of Clock and Data Recovery
systems.
3. Lecture on Clock and Data Recovery Systems by
P.E. Allen (course :- ECE 64400)
4. IEEE paper on A Digital Clock and Data
Recovery Architecture for Multi-Gigabit/s Binary
Links by Jeff Sonntag and John Stonick.
5. Wikipedia page on Clock And Data Recovery
Systems.

Vco collected is the required data recovered from the

received signal. Vco collected can be of various types but due
to space constraints I cannot discuss them all here.

X. CONCLUSION
Receiver end of communication needs a clock as well as a
jitter free data stream. CDR circuits thus come in handy. Basic
modules for steps like edge detection, phase detection are
explained and their technical aspects discussed. Circuitry for
all the steps involved in design of CDR is explained.
Discussion above is only for Linear Input Data. Transmission
of the data is also discussed very briefly. Due to the restriction
and limitation of space this was the best thing I could have
come up.

6. Mostly Images Drawn by me but few taken from

random sources from Google Images because of the
complexity.