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EE6326 Analog Integrated Circuit Design – Fall 2005 UTD J.

Liu

EE 6326 - Analog Integrated Circuit Design

Prerequisite: EE4340

Instructor: Dr. Jin Liu, ECSN 4.506, (972) 883-4393, jinliu@utdallas.edu, www.utdallas.edu/~jinliu

Lecture: Mondays and Wednesdays, 7:00pm – 8:15pm, ECSN 2.112

Office Hours: Mondays and Wednesdays, 4:30pm – 5:30pm

Required Textbook: Design of Analog CMOS Integrated Circuits, by Behzad Razavi, McGraw-Hill, 2001.
ISBN: 0-07-238032-2.

Recommended books: Operational Amplifiers – Theory and Design, Johan H. Huijsing, Kluwer. ISBN:
0792372840
CMOS Analog Circuit Design, Phillip E. Allen and Douglas R. Holberg, Oxford University Press, 2nd edition,
2002. ISBN: 0-19-511644-5
Analog Design for CMOS VLSI Systems, Franco Maloberti, Kluwer Academic Publishers, 2001. ISBN: 0-
7923-7550-5.

Objective: To introduce the principles of analog integrated circuit design and to provide the circuit level
analog IC design knowledge required in the analog IC design industry and research.

Course Grading Policy: The final grade will be determined using the following scheme:
Homework x 20% + Project x 10% + Midterm Exam x 30% + Final Exam x 40%.
All grades become final one week after they are returned in class. The schedule of the exams is shown in
next page.

Exams: All the exams are closed book with one page of notes allowed for Midterm Exam and two pages for
Final Exam.

Homework and Project: Homework will be assigned on a bi-weekly basis and be collected at the beginning
of the class on the due date except the first homework. No late homework. The homework solution will be
posted on the professor’s webpage, with password protection. Some of the homework requires the use of
cadence/analog artist design tools; tutorial will be given at the beginning of the semester. In order to use
Cadence tools at UTD, a UTD UNIX account is required. It is OK to use Cadence tools at your workplace if
preferred. The project will be the design of an operational amplifier.

Attendance and Email Announcement: You are responsible for all course materials, announcements, and
notes, etc. made during our regular class meeting time and from the class email group.

Academic Honesty: It is the responsibility of the instructor to encourage an environment where you can
learn and your accomplishments will be rewarded fairly. Any behavior that compromises the University’s
rules of academic honesty will be reported to the Dean of Students. The penalty of academic dishonesty
ranges from receiving F grade in this class to being expelled from the university.

Library Reserve: The required textbook and the recommended books are on reserve at the library, with
check out time of two hours.

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EE6326 Analog Integrated Circuit Design – Fall 2005 UTD J. Liu

Coverage of Topics:

Class Date Topic Reading


1 8/22 Introduction and review of IC Technology Ch. 1 and Allen ch. 2
2 8/24 MOSFET models - large signal Ch. 2
3 8/29 MOSFET models – parasitic capacitors and small signal Ch. 2
4 8/31 Single stage amplifiers – CS Ch. 2
x 9/5 Labor Day
5 9/7 Single stage amplifiers – CS SD Ch. 3
6 9/12 Cadence Tutorial (TA) Ch. 3
7 9/14 Cadence Tutorial (TA) Ch. 3
8 9/19 Single stage amplifiers – CD (Makeup class 8/28 2:30 pm) Ch. 3
9 9/21 Single stage amplifiers – CG (Makeup class 8/28 2:30 pm) Ch. 3
10 9/26 Cascode amplifiers Ch. 3
11 9/28 Differential amplifiers Ch. 4
12 10/3 Differential amplifiers Ch. 4
13 10/5 Current sources/sinks and current mirrors Ch. 5
14 10/10 Current mirrors Ch. 5
15 10/12 Frequency response Ch. 6
16 10/17 Midterm Exam
17 10/19 Frequency response Ch. 6
18 10/24 Noise Ch. 7
19 10/26 Op amp design parameters Ch. 9
20 10/31 One-stage op amps Ch. 9
21 11/2 Two-stage op amps Ch. 9
22 11/7 Gain Boosting and CMFB Ch. 9
23 11/9 CMFB Ch. 9
24 11/14 Test and characterization of op amps Allen and Notes
25 11/16 Stability and Frequency Compensation Ch. 10
26 11/21 Stability and Frequency Compensation Ch. 10
27 11/23 Voltage and current references Ch. 11
28 11/28 Voltage and current references Ch. 11
12/5 Final Exam, 7:00pm – 9:45pm

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EE6326 Analog Integrated Circuit Design – Fall 2005 UTD J. Liu

HW#1 (20 points, due on 8/31/204)

A yahoo email group will be created, please send an email to UTDEE6326-subscribe@yahoogroups.com,


from the email address you would like to receive emails related to this class. Please put your name as the
title of the email; the email address that you send the email from will be eventually added to the group.

Then, you will receive an email asking for your confirmation. There are two options listed in the email to
join the group. Ignore the first option; use the second one by just replying the email and put your name in
the body of message. The first option requires you to sign in with a yahoo ID; the second option allows you
to use any email address you would like to use.

Finally, you will receive two emails welcoming you to the group; at this stage, you are done!

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