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Instructor
• Andrew Cilia
Department of Electrical Engineering
University of Texas at Dallas
Email: acilia@utdallas.edu
URL: http://www.utdallas.edu/~acilia
Room: ECSN 3.516
Teaching Assistants
Course Objective
EE3120 is a companion laboratory to EE 3320 (Digital Circuits). It involves design,
assembly and test of combinational and sequential logic circuits. Logic designs will be
done using computer-aided design (CAD) tools and implemented using Field-
Programmable Gate Arrays (FPGAs). In this laboratory digital circuits will be designed
and implemented using the Foundation Series Tools and FPGAs from Xilinx, Inc.
Laboratory assignments will be posted on WebCT. Please print and bring to the lab a
copy of the assignment each week.
In-lab. performance (i.e., completing lab, answering laboratory related questions, etc.)
will be graded with the following procedure. TAs will ask pertinent questions to
individual members of a team at random during each lab. Each student will receive up to
10 points for each lab session.
Laboratory Report
• In this laboratory you will work in teams of two. However, the lab. reports will be
written individually.
• Please do not copy lab. reports! You will only cheat yourself, if you do. Please
read the UT Dallas policy on scholastic dishonesty at:
http://www.utdallas.edu/student/slife/dishonesty.html
• For the rest of the report please follow the instructions given in
individual laboratory assignments.
Reports Due Dates
Pre-lab reports are due by the end of the first corresponding lab. Reports are due one
week after completion of the corresponding lab. A late pre-lab or lab report will receive a
30% penalty. Reports that are turned in one week after the deadline will not be accepted
and will not count toward the final grade.