Professional Documents
Culture Documents
Systems
Anantha Chandrakasan
Department Head, EECS
slower is better
ULP
Electronics
Vibration-to-Electric Energy
Self-powered Wireless
Corrosion Monitoring
Sensors
Piezoelectric
Micro-Power
Generators
Power Converter
RECTIFIER
ARBITER
BUCK
BOOST
IMEC
Thermo-Electric Devices
Tellurex
Micro-pelt
1 delays
5mm
comparators
Buck
control
2 delays
Power FETs
Harveste
r
5mmcontrols
Technology
0.35m CMOS
Input Voltages
20 - 150mV Thermal
0.2 - 0.75V Solar
1.5 5V Piezoelectric
Output Voltages
1.8V Regulated
1.8 - 3.3V Storage
Passives
1 Inductor (22H)
5 capacitors
Thermal: Seebeck
50mV/K, T=1.7K
Solar: 1500lux,
15cm2
Piezoelectric:
PZT 3in2, 1g
10
Relec
2
PEP ,max
VEP 1
=
2 Rin
(40 mV) 2
=
= 1.6nW
1M
12
12
Endoelectronics chip:
EP harvester architecture
VEP
*
VIN
Maximum
Extractable
Power:
1.1 to 6.25nW
13
Leakage Power
from Input: 20pW
Leakage Power
from Output: 223pW
14
Leakage Power
from Input: 20pW
Leakage Power
from Output: <1pW
15
Pico-Powered Transmitter!
High-Vt PMOS gating:
Up to 4000X lower
leakage than with no
gating
16
System Measurements
17
Directions in Ultra-low-Power
Processing for IoT Systems
Use of hardware accelerators
Use of non-volatile processing for variable
energy
Ultra-low-voltage operations using
parallelism
Activity driven processing
Light-weight machine learning for data
reduction
18
Clock
...
...
ADC
SCLK1 InterSCLK2
face
GPIO
PMU
Mem. Interface
IFCLK
Median
FIR
JTAG
MISC
TIM
ER
MDB[15:0]
Timers
Real
Time
Clock
Serial
Ports
FIR
GPIO
MAB[19:0]
CPU
64kb
SRAM 1
Multiplier
FFT
CORDIC
SER
IAL
COR
DIC
MEDIAN
C CORE
JT
AG
MU
LT
FFT
3mm
DMA
C Core
128kb SRAM
RTC
SW Debug
Support
EXTCLK
64kb
SRAM 2
Joyce Kwong
[ESSCIRC 10]
19
Non-Volatile Processor
Desired
operation:
Replace all flip-flops with
Non-volatile D Flip-Flop
(NVDFF)
FIR filter test-case:
Embed nonvolatile
memory
elements into
registers
[M. Qazi, ISSCC 2013]
20
Filter
<<
clip
>>
Computational Photography
Glare Reduction
HDR Imaging
-1 EV
Tonemapped HDR
output
0 EV
+1 EV
Before Filtering
Flash
LLE output
No-Flash
Low-light Enhancement
23
After Filtering
23
Image
Pre-Processing
Bilateral Filter
Grid
Assignment
Grid
Assignment
Convolution
Engine
Output
Image
Image
Post-Processing
Grid
Interpolation
Bilateral Grid
Input
Image
Bilateral Filter
Convolution
Engine
Bilateral Grid
Grid
Interpolation
Computational Photography
S
=
32,
R
=
16
Rithe, R., P. Raina, N. Ickes, S. V. Tenneti, A. P. Chandrakasan, "Reconfigurable Processor for Energy-Efficient
Computational Photography," IEEE Journal of Solid-State Circuits, vol. 48, no. 11, pp. 2908-2919, Nov. 2013.
25
26
measurement
result:
2x
change
in
energy
per
opera5on
is
observed
due
to
transient
eects
27
VDD
I=0
VDD
VDD
30
31
32
32x32
Matrix Transpose
32
Electrical
onset
Process
TSMC 0.18 mm
1P6M CMOS
Area
5.0 x 5.0 mm
Supply
Voltage
1.8V (AFE)
1.0V (DBE, ADC)
Channel
1 to 8
Scalable
Input Dyn.
Range
30-59 dB
(4 step)
AFE Power
66mW
Bandwidth
30Hz / 100Hz
ADC
Fully Differential
SAR ADC
Classifier
Type
Latency
10b, 4-32KS/s
Support Vector
Machine
< 2s
Accuracy
Efficiency
Clinical
onset
Epileptic Seizure
Onset Detection
[Jerald Yoo, ISSCC 2012]
84.4%
2.03mJ
/Classification
33
Opportunities
Implement new
crypto primitives
like FHE to enable
secure systems
System solutions to
provide complete
security for IoT
applications
34
ECG = 0.6%
768
512
256
0
Output Code
Output Code
= <code>/range
Accel = 6.7%
1024
Range
1000
2000
3000
Sample Number
ECG Signal, 1 kS/s
512
0
0
36
Conventional SA
LSB-First SA
37
Measurement Results
600
Output
500
Code
400
10 Mean Magnitude = 1.2
Output Code
Rate of Change 0
(LSB/sample)
-10
15
Comparator
DAC
300 m
Switches
Logic
400 m
Bitcycles 10
per Sample 5
0
10
Power
(nW) 5
Mean = 3.7
0
0
0.5
1.5
Time (s)
2.5
Yaul, F. M., A. P. Chandrakasan, "A 10b 0.6nW SAR ADC with Data-Dependent Energy Savings
Using LSB-First Successive Approximation," IEEE International Solid State Circuits Conference
(ISSCC), Feb 2014.
38
Voltage (V)
Voltage (V)
Si etch pit
1
0.5
0
-2
Resonant
Buffer
2.4GHz
ULP-TX
Oscillator Enable
50
MUX
FBAR Oscillators
10dBm
PA
4 s
2
Time (s)
qOscillator consumes
150W from 0.7V supply
qFast startup-time
minimizes
energy overhead
[A. Paidimarri, VLSI Symp. 12]
39
Transmitter Testchip
65nm CMOS
0.7V (RF), 1V (Switch)
3
Startup Time
4s
Data Rate
MUX
and Resonant
Buffers Buffer
Load
OSC
Num. Chan.
OSC
PA
1mm
Supply
OSC
Technology
2mm
1Mb/s
Phase Noise
POUT
17.0dBm to 2.5dBm
440pJ/b at 12.5dBm
530pJ/b at 11.0dBm
550pJ/b at 10.0dBm
40
41
Fully-Implantable Solution
External microphone,
processor, coil
Limitations
Usage in shower/water
sports
Aesthetics and social stigma
M. Yip, R.Jin, H. Nakajima, K. Stankovic, and A. P. Chandrakasan,
A Fully-Implantable Cochlear Implant SoC with Piezoelectric MiddleEar Sensor and Energy-Efficient Stimulation in 0.18m HVCMOS, ISSCC 2014
LDV
Microphone
Speaker Discrete
prototype
Temporal
bone
holder
Micromanipulator
42
Piezoelectric
sensor
Prototype Implementation
43
Wirelessly charge
Charge in 2 minutes for
low-power portables by
typical day use
high-power portables
44
Summary
n Energy efficiency achieved through :
Ultra-low-voltage operation
Hardwired architectures
Exploiting application attributes (e.g., datadriven processing)
Digital control of energy processing
Optimizing for short duty cycles
n Next generation sub-Hz optimized electronics
will enable new energy harvesting applications