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M.J Yusoff, 2N.F Nik Ismail, Member IEEE, 3 Ismail Musirin, Member IEEE, 4N. Hashim, Member
IEEE, 5 D. Johari
I.
INTRODUCTION
Power input
vs
Controller
vo
Measurements
Reference
1) Circuit Operation
Figure 1.2 shows the DC-DC Buck Converter circuit
topology. The circuit operation can be divided into two
modes. First mode (mode 1) begins when controlled switch
(e.g MOSFET) is switch on by pulse width modulation
(PWM), the input current, which rises, flows through filter
inductor, L filter capacitor, C and load resistor, R [5].
During mode 1, the diode reversed biased and resulted from
Load
io
Control signals
is
Power
Processor
142
The 4th International Power Engineering and Optimization Conf. (PEOCO2010), Shah Alam, Selangor, MALAYSIA: 23-24 June 2010
MV (t )
(2.1)
P K e(t)
p
Setpoint
Error
IKie(W)dW
Process
Out
de
D Kddt(t)
Figure 2.1: A block diagram of PID controller
Figure 1.3(a): Mode 1
B.
v L (t )
iL.
diL
dt
T
1
v L (t ).dt
L 0
(1.1)
II.
A.
METHODOLOGY
1) Fuzzifier
A fuzzyfication interface which converts input data
into suitable linguistic values.
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The 4th International Power Engineering and Optimization Conf. (PEOCO2010), Shah Alam, Selangor, MALAYSIA: 23-24 June 2010
4) Defuzzifier
A defuzzyfication interface which yields a
nonfuzzy control action from an inferred fuzzy
control action.
The inputs of the fuzzy logic controller are the error e
and the change of error ce, which are defined in equation 2.2
as:
e Vo Vref
ce
ek ek 1
(2.2)
dk
d k 1 K .Gd k
(2.3)
e
ce
Fuzzifier
d
dt
Defuzzifier
Data Base
Vo
DC/DC
Converter
dk
Vref
Figure 2.2: Basic configuration of FLC
Figure 2.5: Membership function of input variable change of error
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The 4th International Power Engineering and Optimization Conf. (PEOCO2010), Shah Alam, Selangor, MALAYSIA: 23-24 June 2010
TABLE 2.1: The rule base with 25 rules
TABLE 3.2: Fuzzy logic controller for Buck Converters Parameters
ERROR
CHANGE
ERROR
NB
NS
ZO
PS
PB
NB
NS
ZO
PS
PB
PS
NS
ZO
PS
PB
PS
ZO
ZO
PS
PB
PS
ZO
NS
PS
PB
PS
ZO
NS
NB
PB
PS
ZO
NS
NB
NS
Vin (V)
Vref (V)
Vpeak (V)
OS (%)
Tr (ms)
Ts (ms)
24
14
14.005
0.00664
9.02
9.58
24
13
13.01
0.00769
8.43
9.73
24
12
12.011
0.00167
7.75
9.19
24
11
11.003
0.00636
7.87
8.75
24
10
10.021
0.01996
7.83
8.94
III.
Vref (V)
Vpeak (V)
OS (%)
Tr (ms)
Ts (ms)
24
14
23.505
79.94
1.112
86.1
24
13
21.739
79.87
1.119
85.1
24
12
19.93
79.78
1.117
78.2
24
11
18.124
79.69
1.115
77.1
24
10
16.362
79.6
1.113
73.2
Vref (V)
Vpeak (V)
OS (%)
Tr (ms)
Ts(ms)
24
14
14.081
0.128
13.8
15.9
24
13
13.084
0.069
13.5
15.3
24
12
12.089
0.066
12.4
14.6
24
11
11.08
0.208
11.8
14.9
24
10
10.089
0.02
11.5
14.8
Vin (V)
Figure 3.1: Output waveform of open loops buck converter for 14Vref
Vo,PID
(V)
14.063
Vo,O/L
(V)
13.063
Vin (V)
Vref (V)
D (%)
Vo, FLC(V)
24
14
58.33
14.004
24
13
54.17
13.009
13.075
12.086
24
12
50
12.011
12.076
11.086
24
11
45.83
11.002
11.057
10.086
24
10
41.67
10.019
10.087
9.11
TABLE 3.4 (b): The comparison of voltage deviation (Vd) in open loop,
fuzzy control and PID control for Buck converter
Table 3.2 and Table 3.3 show the results from simulation
test on FLC and PID control, respectively. The comparison
of waveforms obtained from both control topologies are
shown in Figure 3.2 to Figure 3.3 with reference voltage
(Vref), 14V to 13V, respectively.
Vin (V)
Vref (V)
Vd,fuzzy (V)
Vd,PID (V)
24
14
0.0044
0.063
Vd,O/L (V)
0.937
24
13
0.009
0.075
0.914
24
12
0.011
0.076
0.914
24
11
0.0023
0.057
0.914
24
10
0.019
0.087
0.89
The 4th International Power Engineering and Optimization Conf. (PEOCO2010), Shah Alam, Selangor, MALAYSIA: 23-24 June 2010
Figure 3.9: Rise time, Trise (ms) vs reference voltage, Vref of plotted graph
for FLC and PIDC
Figure 3.7: Peak voltage, Vpeak vs reference voltage, Vref plotted graph
for FLC and PID
Figure 3.12: Deviation voltage, Vd vs reference voltage, Vref of plotted
graph for open loop, FLC and PIDC of buck converter.
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The 4th International Power Engineering and Optimization Conf. (PEOCO2010), Shah Alam, Selangor, MALAYSIA: 23-24 June 2010
Figure 3.13: The output voltage for fuzzy logic control on buck converter
with step reference applied.
Figure 3.14: The output voltage for PID control on buck converter with step
reference applied.
TABLE 3.5: The tabulated results for fuzzy logic control with step
reference voltage applied.
TABLE 3.5(a)
Vp,2nd (V)
Vo,2nd (V)
Vin (V)
Vref,step
24
14-13.5
14.009
14.002
0.049
24
13-12.5
13.013
13.005
0.062
24
12-11.5
12.012
12.002
0.083
24
11-10.5
11.007
11.001
0.055
24
10-9.5
10.027
10.012
0.149
Vin (V)
Vref,step
24
14-13.5
1.9
3.82
24
13-12.5
2.3
12.525
24
12-11.5
2.7
11.521
24
11-10.5
3.8
10.518
24
10-9.5
3.3
3.9
9.517
TABLE 3.5(b)
Tr,2nd (ms) Ts,2nd (ms)
OS,2nd (%)
Vpdrop,step (V)
13.583
TABLE 3.6: The tabulated results for PID control with step reference
voltage applied.
TABLE 3.6(a)
Vp,2nd (V)
Vo,2nd (V)
Vin (V)
Vref,step
24
14-13.5
14.074
14.063
0.078
24
13-12.5
13.071
13.062
0.069
24
12-11.5
12.07
12.053
0.141
24
11-10.5
11.069
11.059
0.091
24
10-9.5
10.088
10.075
0.129
Vin (V)
Vref,step
24
14-13.5
13
13.6
24
13-12.5
6.3
9.8
12.614
24
12-11.5
9.5
12.2
11.613
24
11-10.5
10.8
12.5
10.596
24
10-9.5
6.5
11.1
9.638
TABLE 3.6(b)
Tr,2nd (ms) Ts,2nd (ms)
IV.
CONCLUSION
OS,2nd (%)
Vpdrop,step (V)
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The 4th International Power Engineering and Optimization Conf. (PEOCO2010), Shah Alam, Selangor, MALAYSIA: 23-24 June 2010
V.ACKNOWLEDGEMENT
The author would like to express a gratitude especially to
Mr. Nik Fasdi Nik Ismail and his team members, for the
support, belief, patience, fairness and for the feedback. The
author would like to thank him for the opportunities and
knowledge that he has given to the author over the year.
VI. REFERENCES
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
VII. BIOGRAPHIES
Muhammad Jamhuri Yusoff obntained
Bachelor of Electrical Engineering (Hons)
from Universiti Teknologi MARA in 2010.
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