Linkping Studies in Science and Technology

Dissertation No. 944

MODELING AND IMPLEMENTATION OF

CURRENT-STEERING DIGITAL-TO-ANALOG
CONVERTERS
K Ola Andersson

Department of Electrical Engineering

Linkpings universitet, SE-581-83 Linkping, Sweden
Linkping, May 2005

Modeling and Implementation of Current-Steering

Digital-to-Analog Converters

Copyright 2005 K Ola Andersson

Department of Electrical Engineering

Linkpings universitet
SE-581 83 Linkping
Sweden
ISBN 91-85297-96-8

ISSN 0345-7524

Printed in Sweden by UniTryck, Linkping, 2005

Abstract
Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs), are interface circuits between the analog and digital domains.
They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This work covers different aspects related to
modeling, error correction, and implementation of DACs for communication
applications where the requirements on the circuits in terms of speed and linearity are hard. The DAC architecture considered in this work is the current-steering
DAC, which is the most commonly used architecture for high-speed applications.
Transistor-level simulation of complex circuits using accurate transistor models
require long simulation times. A transistor-level model of a DAC used in a system simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations require
multiple simulation runs with different parameter values making transistor-level
models unsuitable. Therefore, there is a need for behavioral-level models with
reasonably short simulation times. Behavioral-level models can also be used to
find the requirements on different building blocks on high abstraction levels,
enabling the use of efficient top-down design methodologies. Models of different
nonideal properties in current-steering DACs are used and developed in this
work.
Static errors typically dominates the low-frequency behavior of the DAC. One of
the limiting factors for the static linearity of a current-steering DAC is mismatch
between current sources. A well-known model of this problem is used extensively in this work for evaluation of different ideas and techniques for linearity
enhancement. The high-frequency behavior of the DAC is typically dominated by
dynamic errors. Models of two types of dynamic errors are developed in this

work. These are the dynamic errors caused by parasitic capacitance in wires and
transistors and glitches caused by asymmetry in the settling behavior of a current
source.
The encoding used for the digital control word in a current steering DAC has a
large influence on the circuit performance, e.g., in terms static linearity and
glitches. In this work, two DAC architectures are developed. These are denoted
the decomposed and partially decomposed architectures and utilize encoding
strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures are compared with the wellknown binary-weighted and segmented architectures using behavioral-level simulations.
It can be hard to meet a DAC design specification using a straightforward implementation. Techniques for compensation of errors that can be applied to improve
the DAC linearity are studied. The well-known dynamic element matching
(DEM) techniques are used for transforming spurious tones caused by matching
errors into white or shaped noise. An overview of these techniques are given in
this work and a DEM technique for the decomposed DAC architecture is developed. In modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the signal band. A
technique based on this principle is developed for spectral shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop. Two examples of utilization of the technique are given.
Four different current-steering DACs implemented in CMOS technology are
developed to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms for evaluation of
different techniques for linearity improvement. For example, a 14-bit DEM DAC
is implemented and measurement results are compared with simulation results. A
good agreement between measured and simulated results is obtained. Moreover,
a configurable 12-bit DAC capable of operating with different degrees of segmentation and decomposition is implemented to evaluate the proposed decomposed architecture. Measurement results agree with results from behavioral-level
simulations and indicate that the decomposed architecture is a viable alternative
to the commonly used segmented architecture.

ii

Acknowledgments
First of all, I would like to thank my supervisor, Prof. Mark Vesterbacka for his
guidance and enthusiasm. I would also like to thank all my colleagues at Electronics Systems, Linkping University, for contributing to a pleasant working
environment. Special thanks go to Lic. Eng. Robert Hgglund, Lic. Eng. Henrik
Ohlsson, and Ph.D. Oscar Gustafsson for interesting discussions on research and
life in general.
My former colleagues at Ericsson Microelectronics also deserve my gratitude.
Specifically, I would like to thank Ph.D. J. Jacob Wikner, M.Sc. Niklas U.
Andersson, and Ph.D. Mikael Karlsson Rudberg. I also thank Ph.D. Gunnar
Bjrklund and M.Sc. Magnus Hgglund for supporting my work during the years
I spent doing research at Ericsson Microelectronics.
Finally, I thank my wonderful family, especially my wife Helena and my daughter Elin, for always believing in me and supporting me.
The work was supported by the Microelectronics Research Center (MERC) at
Ericsson Microelectronics and the Center for Industrial Information Technology
(CENIIT) at Linkping University.

iii

iv

Contents
Chapter 1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1 Digital-to-Analog Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.1 Sampling and Reconstruction . . . . . . . . . . . . . . . . . . . . . . . 1
1.1.2 Pulse-Amplitude Modulation . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.3 Ideal Reconstruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.1.4 Reconstruction with Square Pulses . . . . . . . . . . . . . . . . . . 3
1.1.5 The Ideal DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Telecommunication Applications . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.1 Digital Subscriber Line Applications . . . . . . . . . . . . . . . . . 6
1.2.2 The Analog Front End . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2.3 Effects of Nonideal Transmission . . . . . . . . . . . . . . . . . . . 8
1.2.4 DACs for DSL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3 Performance Metrics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.3.1 Metrics in the Code Domain . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.2 Metrics in the Frequency Domain . . . . . . . . . . . . . . . . . . 13
1.4 Converter Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
1.4.1 Nyquist-Rate and Oversampled Converters . . . . . . . . . . . 17
1.4.2 Current-Steering DACs . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.4.3 Charge-Redistribution DACs . . . . . . . . . . . . . . . . . . . . . . 20
1.4.4 R-2R Ladder DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.5 Resistor-String DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.4.6 DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.5 CMOS Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

1.5.1 Large-Signal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

1.5.2 Small-Signal Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.5.3 Parasitics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.5.4 Device Matching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
1.5.5 CMOS Transistors in Current-Steering DACs . . . . . . . . . 33
1.6 Outline of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.6.1 Chapter 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.6.2 Chapter 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
1.6.3 Chapter 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
1.6.4 Chapter 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.7 Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.7.1 Journal Publications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.7.2 Conference Publications . . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.7.3 Theses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.7.4 Patents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Chapter 2
Modeling of Current-Steering DACs . . . . . . . . . . . . . 45
2.1 Evaluation of Performance Metrics for Static Errors . . . . . . 46
2.2 Modeling of Matching Errors . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.2.1 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
2.2.2 Modeling of Random Matching Errors . . . . . . . . . . . . . . 48
2.2.3 Modeling of Linearly Graded Matching Errors . . . . . . . . 51
2.3 Modeling of Finite Output Impedance . . . . . . . . . . . . . . . . . . 56
2.3.1 Finite Output Resistance . . . . . . . . . . . . . . . . . . . . . . . . . 56
2.3.2 Finite Output Impedance . . . . . . . . . . . . . . . . . . . . . . . . . 58
2.4 Modeling of Glitches due to Rise/Fall Asymmetry . . . . . . . . . 68
2.4.1 Preliminaries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
2.4.2 Model Derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
2.4.3 Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
2.4.4 Glitches in the Differential Output . . . . . . . . . . . . . . . . . . 91

Chapter 3
Digital Encoding in Current-Steering DACs . . . . . . . 93
3.1 Binary-Weighted DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
3.2 Segmented DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
vi

3.3 Decomposed DACs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

3.3.1 1-Layer Decomposition . . . . . . . . . . . . . . . . . . . . . . . . . . 96
3.3.2 Multi-Layer Decomposition . . . . . . . . . . . . . . . . . . . . . . . 98
3.3.3 Properties of Decomposed DACs . . . . . . . . . . . . . . . . . . . 99
3.4 Partially Decomposed DACs . . . . . . . . . . . . . . . . . . . . . . . . . 100
3.5 Other Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
3.6 Comparison of Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
3.6.1 Influence of Matching Errors . . . . . . . . . . . . . . . . . . . . . 105
3.6.2 Influence of Glitches . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
3.6.3 Simulation Result Summary . . . . . . . . . . . . . . . . . . . . . . 114
3.7 Encoder Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
3.7.1 Decomposition Encoder Implementation . . . . . . . . . . . . 114
3.7.2 Binary-to-Thermometer Encoder Implementation . . . . . 115

Chapter 4
Correction and Compensation of Errors . . . . . . . . . 117
4.1 Dynamic Element Matching . . . . . . . . . . . . . . . . . . . . . . . . . . 117
4.1.1 Generalized DEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
4.1.2 DEM Utilizing Switching Trees . . . . . . . . . . . . . . . . . . . 120
4.1.3 Mismatch-Shaping DEM . . . . . . . . . . . . . . . . . . . . . . . . 122
4.1.4 DEM in Decomposed DACs . . . . . . . . . . . . . . . . . . . . . 123
4.2 Distributed Biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
4.3 Modulation of Expected Errors . . . . . . . . . . . . . . . . . . . . . . . 129
4.3.1 Basic Idea . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
4.3.2 Spectral Shaping of Output Impedance Related Errors . 131
4.3.3 Yield Enhancement of Binary-Weighted DACs . . . . . . 132

Chapter 5
Test-Chip Implementations . . . . . . . . . . . . . . . . . . . . 139
5.1 Design and Measurement Strategies . . . . . . . . . . . . . . . . . . . 139
5.1.1 Design Strategies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
5.1.2 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
5.2 A 14-bit Segmented DAC in 0.35 m CMOS . . . . . . . . . . . . 144
5.2.1 Chip Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
5.2.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
5.3 A 14-bit PRDEM DAC in 0.35 m CMOS . . . . . . . . . . . . . . 147
5.3.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
vii

5.3.2 Simulations and Comparison with Measurements . . . . . 148

5.4 A 14-bit Dual DAC in 0.25 m CMOS . . . . . . . . . . . . . . . . . 152
5.4.1 Architecture and Implementation . . . . . . . . . . . . . . . . . . 152
5.4.2 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
5.5 A 12-bit Configurable DAC in 0.35 m CMOS . . . . . . . . . . 155
5.5.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
5.5.2 Pcell-Based Design Approach . . . . . . . . . . . . . . . . . . . . 156
5.5.3 Simulation Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
5.5.4 Measurement Results . . . . . . . . . . . . . . . . . . . . . . . . . . . 166

Chapter 6
Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171

References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

viii

1 Introduction
Data converters, i.e., analog-to-digital converters (ADCs) and digital-to-analog
converters (DACs), are interface circuits between the analog and digital domains.
They are used in, e.g., digital audio applications, data communication applications, and other types of applications where conversion between analog and digital signal representation is required. This thesis covers different aspects related to
modeling, error correction, and implementation of DACs for communication
applications. This chapter is an introduction to the thesis providing relevant background information and an overview of the thesis and the authors contributions
to the different areas.

1.1 Digital-to-Analog Conversion

An overview of fundamental theories for digital-to-analog conversion is provided
in this section. The concepts of sampling and reconstruction are discussed in
Sec. 1.1.1, and reconstruction using pulse-amplitude modulation is overviewed in
Sec. 1.1.2. Ideal reconstruction using sinc pulses and reconstruction using square
pulses are presented in Sec. 1.1.3 and Sec. 1.1.4, respectively, followed by a discussion on the ideal DAC in Sec. 1.1.5.
1.1.1 Sampling and Reconstruction
Let t denote time and let z(t) denote an analog signal, which is uniformly sampled to a discrete-time signal x(n) according to
x(n) = z(nT ) ,

(1.1)

Introduction

where n is the sequence index and T is the sample period. If z(t) is band limited,
having no spectral content above a frequency f 0 , and the sampling frequency
f s = 1 T has the property
fs > 2 f0,

(1.2)

then the analog signal z(t) can be reconstructed from the discrete-time signal
x(n) according to the sampling theorem [1].
1.1.2 Pulse-Amplitude Modulation
The reconstruction of a signal can be performed using pulse-amplitude modulation (PAM), in which case the reconstructed signal y(t) is given by

y(t) =

x(n) p(t nT ) ,

(1.3)

n =

where p(t) is a pulse. A model system for constructing y(t) is shown in Fig. 1.1.
An intermediate signal y 0(t) given by

y 0(t) =

x(n)(t nT ) = z(t)

n =

(t nT )

(1.4)

n =

is constructed, where (t) is the unit impulse. Let denote angular frequency
and let Z () and Y 0() denote the Fourier transforms of z(t) and y 0(t) , respectively. Y 0() can be expressed as [2]
1
Y 0() = --T

k =

2
Z ( k ------) = f s
T

Z ( k2 f s) .

(1.5)

k =

Further, y 0(t) is filtered with a filter having the impulse response p(t) , resulting
in the reconstructed output y(t) . Hence, the Fourier transform of y(t) is

Y () = P()Y 0() = P() f s

k =

Z ( k2 f s) ,

(1.6)

where P() is the Fourier transform of p(t) . Different choices of the pulse p(t)
are discussed in the following sections.

Digital-to-Analog Conversion

PAM
d(t), T

x(n)

x(n)
Figure 1.1

y0(t)

PAM
p(t), T

P(w)

y(t)

y(t)

Model system for signal reconstruction.

1.1.3 Ideal Reconstruction

In ideal reconstruction, y(t) = z(t) . Hence,

Y () = P() f s

k =

Z ( k2 f s) = Z () .

(1.7)

This is obtained if the filter in Fig. 1.1 is an ideal low-pass filter with bandwidth
f s 2 , i.e.,
T for < f
s .
P() =
0
otherwise

(1.8)

The shape of the pulse p(t) for ideal reconstruction can be found by performing
an inverse Fourier transform on (1.8), resulting in [2]
sin ( f s t )
p(t) = ----------------------- = sinc( f s t) .
f st

(1.9)

1.1.4 Reconstruction with Square Pulses

Because the sinc pulse, sinc( f s t) , has infinite extension in time, it is not practically possible to use the sinc pulse for signal reconstruction. Therefore, other
pulse shapes are used in practice. The most commonly used pulse shape is the
square pulse
T
1 for T
--- t < --p(t) =
2 ,
2
0 otherwise

(1.10)

resulting in a piecewise constant reconstructed signal

Introduction

--- t < nT + T
--- .
y(t) = x(n) for nT T
2
2

(1.11)

The Fourier transform of the square pulse is

P() = T sinc ------------ .

2 f s

(1.12)

For frequencies close to f s 2 , the reconstructed signal is attenuated approximately 3.9 dB compared with the ideally reconstructed signal [3]. Further, the
spectral images of Z () that are present in Y 0() (corresponding to the terms in
(1.5) where k 0 ) are not completely eliminated. Therefore, a DAC that performs signal reconstruction using square pulses usually requires additional filtering of the output to remove unwanted high-frequency signal components. The
filter performing this task is usually denoted reconstruction filter or image-rejection filter. The effects of using sinc and square pulses for signal reconstruction
are illustrated in the frequency domain in Fig. 1.2.
1.1.5 The Ideal DAC
In analogy with the discussion on ideal reconstruction in Sec. 1.1.3, it would be
natural to define an ideal DAC as a device that performs the mapping

y(t) =

x(n)sinc( f s ( t nT )) .

(1.13)

However, since this is not practically possible, we define an ideal DAC as a

device that performs PAM with a square pulse, yielding a piecewise constant output as in (1.11). In this work, we consider the DAC input to be a sequence of integers, whereas the output is represented with a voltage or a current. Therefore, a
scaling factor K is required in the mapping between the digital and the analog
domains. We also allow an offset m added to the analog signal. Hence, the ideal
DAC performs the mapping
--- t < nT + T
--- .
y(t) = K x(n) + m for nT T
2
2

(1.14)

The input to the DAC is digital and, hence, it is quantized. Therefore, even for an
ideal DAC, the output is subject to a quantization error. The quantization error
q(n) , sometimes referred to as quantization noise, can often be accurately modeled with a white-noise signal having rectangular distribution. In the case of truncation,
4

Digital-to-Analog Conversion

|Z(2f)|

0
4

1
0
1
Normalized frequency (f/fs)

(a)

|Y (2f)|

TA

0
4

1
0
1
Normalized frequency (f/fs)
(b)

|Y(2f)|

0
4

1
0
1
Normalized frequency (f/fs)
(c)

|Y(2f)|

0
4

1
0
1
Normalized frequency (f/fs)
(d)

Figure 1.2

Illustration of the effects of using different pulses for reconstruction on the signal spectrum. Z () and Y 0() are shown in (a) and (b), respectively, and
Y () using sinc and square pulses for reconstruction are shown in (c) and (d),
respectively.

Introduction

q(n) Re(0, ) ,

(1.15)

where is the quantization step. The power of the quantization noise is given by
its variance, which for the quantization-noise model in (1.15) is

2
2
x
x----2------ .
dx --- dx =
Var(q(n)) =

12
0

(1.16)

1.2 Telecommunication Applications

In this work, we focus on DACs for high-speed telecommunication applications,
specifically wireline applications. Examples of such applications are the different
digital subscriber line (DSL) applications. In this section, we give a brief overview of these applications, present the analog front end, illustrate the effects of
nonideal transmission, and discuss the DAC requirements for DSL.
1.2.1 Digital Subscriber Line Applications
Due to the increasing demand for low-cost and high bit-rate internet connections,
it is desirable to use existing infrastructures for wideband data communication.
One example of such existing infrastructures is the twisted-pair copper wires
originally intended for the plain old telephone service (POTS), which uses a signal bandwidth of approximately 3.4 kHz [4]. The different DSL technologies,
sometimes referred to with a common name as xDSL, utilize these copper wires
to provide data transmission with high bit rates compared with analog modems.
The signal bandwidths for DSL are considerably higher than the 3.4 kHz used in
POTS, making the design of DSL circuits a challenging task. Some examples of
DSL technologies are asymmetric DSL (ADSL), very high bit-rate DSL (VDSL),
high bit-rate DSL (HDSL) and single-pair high-speed DSL (SHDSL)
[4, 5, 6, 7, 8]. Some properties of these technologies are listed in Table 1.1. The
achievable data rates for each technology depend on the quality (e.g., attenuation
and noise levels) of the copper wires [4].
In ADSL, the information is transmitted using a discrete multi-tone (DMT) signal. The frequency bands used in frequency division multiplexing (FDM) ADSL
[4] are shown in Fig. 1.3. The frequency range up to 4 kHz is reserved for POTS
transmission. Data is transmitted upstream, i.e., from the customer premises
equipment (CPE) to the central office (CO), in the frequency band between 30
and 138 kHz. The frequency band between 138 kHz and 1.104 MHz is used for
data transmission in the reverse direction, i.e., downstream. A guard band, where
no information is transmitted, is present between the POTS band and the ADSL

Telecommunication Applications

Technology

maximum bit rate

required bandwidth

ADSL

8 Mbit/s
(downstream)
900 kbit/s
(upstream)

1.104 MHz

VDSL

52 Mbit/s
(downstream)
26 Mbit/s
(symmetric)

17.664 MHz

HDSL

1.5 Mbit/s
(per wire pair)

400 kHz

SHDSL

2.3 Mbit/s

385 kHz

Table 1.1

Characteristics of some DSL technologies.

upstream band to ensure low interference between POTS and ADSL transmission. Another type of ADSL is the echo-canceled hybrid (ECH) ADSL [4], in
which the downstream band overlaps the upstream band to increase the downstream data rate compared with FDM ADSL. ECH ADSL requires the use of
echo cancellation to separate received data from transmitted data [4].

Figure 1.3

30

138
Frequency [kHz]

ADSL downstream

guard band

POTS
0

ADSL upstream

Frequency bands in FDM ADSL

1104

Frequency bands used in FDM ADSL.

As can be seen from Fig. 1.3, the maximum signal bandwidth in ADSL is
approximately 1 MHz. For DMT VDSL, the standard allows bandwidths up to
approximately 18 MHz [5], i.e., roughly an order of magnitude higher than for
ADSL.

Introduction

No specific application is targeted in this work. Instead, the bandwidths required

in ADSL and VDSL are used as guidelines for typical bandwidth requirements in
wideband communication applications.
1.2.2 The Analog Front End
The analog front end (AFE) in a DSL transceiver is the interface between the digital signal processing (DSP) blocks and the telephone line, as shown in Fig. 1.4.
In the transmit path, there are a DAC, one or more analog filters for spectral
image rejection, and a line driver. In the receive path, there are a receive amplifier, one or more anti-aliasing filters ensuring that the signal is band limited
before sampling, and an ADC. The illustration in Fig. 1.4 is a simplified view of
an AFE. For example, circuits for echo cancellation and the line transformer have
been omitted in order not to obscure the view. Oversampling (see Sec. 1.4.1) is
often used to relax the circuit requirements. This requires the use of interpolation
filters for increasing the sampling frequency in the transmit path, and decimation
filters for decreasing the sampling frequency in the receive path. The DSP blocks
contain, e.g., an inverse fast Fourier transform (IFFT) circuit for modulation of
the transmitted data and a fast Fourier transform (FFT) circuit for demodulation
of the received data.

DAC

image-rejection
filter

ADC

anti-aliasing
filter

line driver
communication channel

DSP blocks

AFE

receive amplifier
Figure 1.4

Typical AFE for DSL applications.

1.2.3 Effects of Nonideal Transmission

A brief overview of the effects of nonideal transmission is given in this section.
The discussion is limited to the effects on DMT signals utilizing quadrature
amplitude modulation (QAM). This type of signal is commonly used in DSL
applications [4, 5].
In the time domain, a DMT signal, x(t) , can be expressed as

Telecommunication Applications

x(t) =

k ak cos ( k0 t ) + bk sin ( k0 t ) .

(1.17)

The different amplitudes ( a k and b k ) are determined by the transmitted data. To

each carrier, there is an associated QAM constellation [4]. A 16 QAM constellation, representing four data bits, is illustrated in Fig. 1.5(a). Every point in the
constellation corresponds to a unique combination of the four data bits. The
amplitudes a k and b k are the coordinates of the point in the constellation, as
indicated on the axes in Fig. 1.5(a).
During transmission, the signal is subject to both nonlinear and linear distortion,
e.g., due to nonlinearities in the transmitter and attenuation in the transmission
medium. Moreover, noise is added to the signal due to thermal activity and external interferers. The effects caused by these sources of nonideal transmission are
illustrated in Fig. 1.5(b)-(d), using a discrete-time signal
7

x(n) =

ak cos ( k0 n ) + bk sin ( k0 n ) for n = 0, 1, , 15 ,

(1.18)

k=1

where 0 = 8 . To each tone, there is an associated 16 QAM constellation, as

plotted in Fig. 1.5(a). A set of 100 random combinations of data points from the
constellations corresponding to all k 4 is generated. Each of these stochastic
outcomes is combined with all data points in the constellation corresponding to
k = 4 , resulting in a total of 1600 different test signals. How the constellation
corresponding to k = 4 is affected by linear distortion, nonlinear distortion, and
noise is illustrated in Fig. 1.5(b), (c), and (d), respectively. Fig. 1.5(b) shows how
the constellation is influenced when the signal is filtered through a simple finitelength impulse response (FIR) filter
y(n) = 0.5x(n) + 0.1x(n 1) .

(1.19)

The constellation is scaled and rotated. However, there is a one-to-one mapping

between the original and distorted constellation, so the original constellation can
be restored from the distorted constellation if this mapping is known. Hence,
error-free transmission is possible if the signal is only subject to linear distortion.
The case is different if the distortion is nonlinear. The data points resulting from
the nonlinear mapping
y(n) = x(n) + 0.02x 3(n)

(1.20)

Introduction

are plotted in Fig. 1.5(c). For this case, there is no one-to-one mapping between
the original and the distorted constellation. Instead, due to intermodulation distortion, the location of the points are dependent on the data transmitted on the
other tones. For more severe nonlinearities, the regions in which the points can
appear start to overlap, which in turn results in bit errors in the transmission. The
situation is similar when noise is present. The constellation resulting from addition of a white Gaussian noise sequence, (n) N(0, 0.1) , is plotted in
Fig. 1.5(d).
Original constellation

Linearly distorted constellation

0.25

0.25
bk

0.75

bk

0.75

0.25

0.25

0.75

0.75
0.75 0.25 0.25 0.75
ak

0.75 0.25 0.25 0.75

ak

(a)

(b)

Nonlinearly distorted constellation

0.25

0.25
bk

0.75

bk

0.75

0.25

0.25

0.75

0.75
0.75 0.25 0.25 0.75
ak
(c)

Figure 1.5

10

Constellation with added noise

0.75 0.25 0.25 0.75

ak
(d)

(a) 16 QAM constellation, (b) linearly distorted constellation, (c) nonlinearly

distorted constellation, and (d) constellation with added noise.

Performance Metrics

The nonlinearities and the noise set limits on the feasible size of the constellation,
i.e., how many data bits that can be allocated to each carrier [4]. Therefore, it is
important that the components in the transmitters and the receiver have good
noise and linearity properties, which is a motivation for having the linearity properties of DACs as one of the main focuses in this work.
1.2.4 DACs for DSL
A brief overview on how to choose a proper number of bits for a DAC in a DSL
transmitter is given in this section. More detailed descriptions are given in
[4, 6, 9]. As discussed in Sec. 1.2.3, the amount of noise added to the signal in
the channel limits the feasible constellation sizes. Hence, the achievable data rate
in a DSL system is a function of the signal-to-noise ratios for the sub channels
and the desired maximum error probability. For example, the maximum allowed
number of bits that are mapped onto a carrier in ADSL is 15, resulting in a
32 768 QAM constellation [9]. In order to accommodate 15 bits with an error
probability of 10 7 in a sub channel, the required signal-to-noise ratio in that sub
channel is approximately 53 dB [6]. Assuming that this value is obtained, the
output step-size, , corresponding to one LSB, is chosen small enough so that
the quantization noise does not degrade the overall SNR too much. The output
swing, S , of the DAC is chosen in order to obtain a low probability of clipping
[4, 6]. Finally, the number of bits, N , is given by
N =

log 2(--S-) .

(1.21)

Carrying out this analysis for an ADSL transmitter typically results in 12-14 bits,
depending on if echo cancellation is used or not [4].

1.3 Performance Metrics

Some performance metrics are required to characterize the performance of a
DAC. In Sec. 1.3.1, some commonly used code-domain performance metrics are
presented. These metrics can only characterize the DACs static (settled) behavior. In telecommunication and other high-speed applications, the DAC performance is usually limited by the dynamic behavior. In that case, the DAC is better
characterized by frequency-domain metrics [10], which are presented in
Sec. 1.3.2.

11

Introduction

1.3.1 Metrics in the Code Domain

The integral nonlinearity (INL) and the differential nonlinearity (DNL) are performance metrics in the code domain that describe the static linearity of a DAC.
The static transfer characteristic of a nonideal 4-bit DAC, i.e., the settled output
level as a function of the input code, is plotted in Fig. 1.6. Also included in
Fig. 1.6 is a straight line representing the nominal DAC transfer characteristic
y nom(x) = Kx + y offset .

(1.22)

The gain K and the offset y offset are chosen such that y nom(x) is a best-fit (least
squares) straight line with respect to the actual transfer characteristic. Sometimes, alternative choices for the nominal characteristic are used [11], e.g., using
the endpoints of the characteristic to define a straight line according to
y(2 N 1) y(0)- and y
K = ------------------------------------offset = y(0) .
2N 1

(1.23)

However, in this work we exclusively use the nominal characteristic given by the
least-squares method. This is further discussed in Sec. 2.1.

Output level (y)

Static transfer characteristics, nonideal DAC

15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input code (x)
Figure 1.6

Transfer characteristic of nonideal 4-bit DAC plotted together with best-fit nominal transfer characteristic.

Integral Nonlinearity
The INL of a DAC is defined as
y(x) y nom(x)
INL(x) = --------------------------------K

12

(1.24)

Performance Metrics

and measures the deviation from the nominal transfer characteristic. If

INL(x) < 0.5 for all x , the DAC is guaranteed to be monotone, i.e.,
y(x 1) > y(x 2) if and only if x 1 > x 2 . The INL for the nonideal 4-bit DAC with the
characteristic in Fig. 1.6 is plotted in Fig. 1.7.

INL

INL curve, nonideal DAC

0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input code (x)
Figure 1.7

INL curve for the nonideal 4-bit DAC.

Differential Nonlinearity
The DNL of a DAC is defined as
y(x) y(x 1)- 1
DNL(x) = --------------------------------K

(1.25)

and measures the deviation from the nominal step size at the DAC output in the
transition from x 1 to x at the input. Combining (1.22)-(1.25) yields
DNL(x) = INL(x) INL(x 1) .

(1.26)

If DNL(x) < 1 for all x , the DAC is guaranteed to be monotone. The DNL for
the nonideal 4-bit DAC is plotted in Fig. 1.8. In some literature, the unit LSB is
associated with the INL and DNL metrics. In this work, however, these metrics
are considered unitless.
1.3.2 Metrics in the Frequency Domain
The metrics presented in Sec. 1.3.1 are useful for characterizing the static linearity of DACs. However, in high-speed applications, the dynamic properties of a
DAC tend to limit the performance. Hence, the static metrics are insufficient for
these types of applications. Therefore, communication DACs are often characterized in the frequency domain rather than in the code domain [10].
13

Introduction

DNL

DNL curve, nonideal DAC

0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Input code (x)
Figure 1.8

DNL curve for the nonideal 4-bit DAC.

Sinusoidal test signals are often used for DAC characterization. A typical power
spectral density (PSD) plot of the output from a DAC with a single-tone input is
shown in Fig. 1.9. The largest peak in Fig. 1.9 represents the signal, whereas the
spectral content at other frequencies are unwanted signal impurities. These signal
impurities are usually divided into noise and distortion, even if it can be difficult
to make a clear distinction between the two. Noise is independent of the signal,
whereas distortion is signal dependent [12]. In the frequency domain, noise is
often characterized by a smooth spectral density, whereas (nonlinear) distortion
is visible as distinctive peaks in the output spectrum. There are, however, gray
zones present in the analysis. For example, quantization errors are clearly signal
dependent, but are often considered as sources of noise.
Single-tone output spectrum, nonideal DAC
0

PSD [dB]

20
40

SFDR

60
80
100
120
0

0.1

0.2
0.3
0.4
Normalized frequency (f/f )
s

Figure 1.9

14

Single-tone output spectrum for a nonideal 14-bit DAC.

0.5

Performance Metrics

Signal-to-Noise Ratio
The signal-to-noise ratio (SNR) is used to characterize how well the signal can be
distinguished from the noise. SNR is defined as
P signal
-,
SNR = --------------P noise

(1.27)

where P signal is the signal power and P noise is the noise power.
Signal-to-Noise-and-Distortion Ratio
If a large amount of distortion is present in the output, the signal quality is better
characterized with the signal-to-noise-and-distortion ratio (SNDR, in some literature abbreviated SINAD). SNDR is defined as
P signal
SNDR = ---------------,
P nd

(1.28)

where P nd is the total power for the noise and the distortion.
Effective Number of Bits
If a full-scale sinusoid is applied at the input of an ideal N -bit DAC, for which
the only errors are caused by quantization, the SNDR is approximately [11]
SNDR 6.02N + 1.76 dB .

(1.29)

Using (1.29) as a starting point, the effective number of bits (ENOB) for a nonideal DAC is defined as
SNDR 1.76- .
ENOB = ------------------------------6.02

(1.30)

Spurious-Free Dynamic Range

Nonlinearities in the DAC give rise to harmonic distortion. The spurious-free
dynamic range (SFDR) measures the linearity of a DAC according to
P signal
-,
SFDR = --------------P ls

(1.31)

where P ls is the power of the largest spurious tone at the DAC output. The SFDR
is indicated in Fig. 1.9.

15

Introduction

Multi-Tone Power Ratio

Nonlinear systems, as opposed to linear systems, cannot be fully characterized by
their response to single-tone signals [13]. Therefore, the single-tone performance
metrics described above are insufficient if the DAC is used in a multi-carrier
application. The multi-tone power ratio (MTPR) measures the linearity of a DAC
when subject to a multi-tone input. A multi-tone signal
x(n) =

k ck sin ( k0 n + k )

(1.32)

for k belonging to some interval , is used as an input. and 0 are chosen

such that the signal becomes a relevant test signal for a given application. The
amplitudes c k are chosen equal for all k but one, for which the amplitude is set
to zero. Intermodulation caused by the DAC nonlinearities give rise to a spurious
tone at the frequency for which the amplitude was set to zero. The MTPR is
defined as the power ratio between one of the wanted tones and this spurious
tone, as indicated in the multi-tone spectrum in Fig. 1.10.
Multi-tone output spectrum, nonideal DAC
0

PSD [dB]

20
MTPR

40
60
80
100
0

0.1

0.2
0.3
0.4
Normalized frequency (f/f )

0.5

Figure 1.10

Multi-tone output spectrum for a nonideal 14-bit DAC.

In a single-tone test, the only relevant parameters are the amplitude and the frequency of the test tone. In an MTPR test, however, the degrees of freedom are
higher. Besides the amplitude, the resulting MTPR is depending on which tone
that has zero amplitude, and also the mutual phase differences between the other
tones. Hence, it is easier to set up and interpret the result from a single-tone test.
Therefore, the single-tone performance metrics are often used, even if they give
insufficient information. In this work, multi-tone tests are used to some extent,
but not as much as single-tone tests.

16

Converter Architectures

1.4 Converter Architectures

An overview of some different DAC architectures is given in this section. The
differences between Nyquist-rate and oversampled DACs are outlined in
Sec. 1.4.1. The current-steering, charge-redistribution, R-2R ladder, and resistorstring DAC architectures are discussed in Sec. 1.4.2-Sec. 1.4.5. Common to these
architectures is that they perform a memory-less mapping from the digital input
to the analog output. They are commonly referred to as flash or parallel converters [14], since the conversion of an input sample is performed during one clock
cycle. In DACs, outlined in Sec. 1.4.6, noise-shaping techniques are used
together with oversampling to allow the signal to be reconstructed with a flash
DAC having fewer input bits than the input signal. Due to the noise shaping, most
of the quantization noise caused by the additional quantization appears outside of
the signal band and can, hence, be filtered out.
1.4.1 Nyquist-Rate and Oversampled Converters
According to the sampling theorem, it is required that
fs > 2 f0,

(1.33)

where f 0 is the bandwidth of the signal. A data converter with f s just a small
fraction larger than 2 f 0 is commonly referred to as a Nyquist-rate converter
[9, 11], whereas a data converter with f s considerably larger than 2 f 0 is
referred to as an oversampled converter [9, 11]. The oversampling ratio (OSR) is
defined as
fs
OSR = --------.
2f0

(1.34)

There are several reasons for using oversampling. If the number of bits in a converter is large, the quantization noise is approximately white. Hence, the PSD of
the quantization noise is approximately constant, i.e.,
2 f
PSD Q( f ) ------ -----s .
12 2

(1.35)

From (1.35), it is evident that the total noise power within the signal band
( f f 0 ) is decreased if f s is increased. Hence, an oversampled converter has
less quantization noise power within the signal band than a Nyquist-rate converter with the same .

17

Introduction

Another reason for using oversampling is that it simplifies the design of the (analog) anti-aliasing filters for ADCs and image-rejection filters for DACs. The
unfiltered output spectra for a Nyquist-rate DAC and a DAC with OSR = 2 are
shown in Fig. 1.11(a) and (b), respectively (the desired spectrum is plotted in
Fig. 1.2(a)). The spectral images that appear around multiples of f s are better
separated for the oversampled converter, since its sampling frequency is higher
than that of the Nyquist-rate DAC. Further, the output of the oversampled converter is less distorted by the sinc weighting within the signal band, and the spectral images are better attenuated by the sinc weighting. Hence, requirements on
the filters for attenuation of the spectral images is lower for the oversampled converter than for the Nyquist-rate converter. The relaxed filter requirements a
allows for larger design margin and/or a reduced filter order compared with the
Nyquist-rate case.
1.4.2 Current-Steering DACs
The current-steering DAC, which is based on the switched-current technique
[15], is suitable for high-speed applications [9, 14, 16] and, therefore, the most
frequently used DAC architecture in wideband communication applications. A
differential current-steering DAC is shown in Fig. 1.12. It consists of a number of
weighted current sources, a number of switches, and two load resistors. Bit b l of
a digital control word controls a switch that steer the current from the l:th current
source to one of the two load resistors. With ideal switches and current sources,
the positive output current is
I+ =

l bl I l

(1.36)

and the negative output current is

I =

l bl I l = l I l l bl I l ,

(1.37)

where b l denotes the complement of b l . The differential output current is

I diff = I + I = 2

l bl I l l I l .

(1.38)

There are also positive, negative, and differential output voltages, which are the
corresponding currents multiplied with the load resistance R L . In an ideal current-steering DAC, each current I l is given by
I l = w l I unit ,

18

(1.39)

Converter Architectures

Output spectrum, Nyquistrate DAC

|Y(2f)|

0
8f0

6f0

4f0

2f0

0
Frequency

2f

4f0

6f0

8f0

4f0

6f0

8f0

(a)
Output spectrum, OSR = 2

|Y(2f)|

0
8f0

6f0

4f0

2f0

0
Frequency

2f

(b)
Figure 1.11

Output spectra from (a) Nyquist-rate DAC and (b) oversampled DAC.

where w l is the integer weight of the current source and I unit is the unit current.
If the digital control word represents the DAC input x , i.e.,
x =

l bl wl ,

(1.40)

19

Introduction
VDD
Il1

Il

Il+1

bl1

bl

bl+1

I+

V+

V
RL

Figure 1.12

RL

Differential current-steering DAC architecture.

we have that

l bl I l =

xI unit .

(1.41)

The performance of a current-steering DAC is influenced by how the input is

encoded to form the digital control word, and, hence, the choice of the weights
w l . For matching purposes, a current source with weight w l is usually implemented with w l unit current sources connected in parallel. Commonly used
architectures are the binary-weighted architecture [9], for which
wl = 2 l ,

(1.42)

the thermometer-coded architecture [9], for which

w l = 1 for every l ,

(1.43)

and a hybrid between the binary-weighted and the thermometer-coded architectures known as the segmented architecture [9, 17].
1.4.3 Charge-Redistribution DACs
The charge-redistribution DAC architecture, which is based on the switchedcapacitor technique [18], is illustrated in Fig. 1.13. The charge-redistribution
DAC, in contrast to the current-steering DAC, requires an operational amplifier

20

Converter Architectures

for proper operation. This operational amplifier limits the speed of the circuit,
making the charge-redistribution DAC less suited for wideband applications than
the current-steering DAC. The charges in Fig. 1.13 are given by
Q l = V ref b l C l

(1.44)

and
Q L = V out C L .

(1.45)

The total charge, Q tot , on all capacitor plates connected to the negative input of
the operational amplifier is constant over time. Q tot is given by
Q tot = Q L +

l Ql ,

(1.46)

which, together with (1.44) and (1.45), yields

Q tot
V out = --------- V ref
CL

l
-.
l bl -----CL

(1.47)

In an ideal charge-redistribution DAC, each capacitance C l is given by

C l = w l C unit ,

(1.48)

where w l is the integer weight of the capacitor and C unit is the unit capacitance.
If the digital control word represents the input x as in (1.40), then
QL
CL
Vout
Cl1
bl1

Ql1

Cl
bl

Ql

Cl+1

Ql+1

bl+1

Vref
Figure 1.13

Charge-redistribution DAC architecture.

21

Introduction

C unit
Q tot
-x .
- V ref ----------V out = --------Cl
CL

(1.49)

It should be noted that the circuit diagram in Fig. 1.13 only illustrates the basic
principle behind charge-redistribution conversion. Since Q tot cannot be changed,
one must settle with the value that results from the fabrication of the circuit. This
value will be different for different circuits, and the offset voltage for the DAC
cannot be controlled. Therefore, in an actual implementation of a charge-redistribution DAC, a more elaborate circuit structure than that in Fig. 1.13 must be used
where, e.g., part of the clock cycle is used for offset-voltage compensation [11].
1.4.4 R-2R Ladder DACs
R-2R ladder networks can be utilized in different ways to perform digital-to-analog conversion [9, 11, 19]. An R-2R ladder DAC with current references is illustrated in Fig. 1.14. The current I L flowing through the load resistor is
I ref
I L = -------------2N 1

N1

bl 2l ,

(1.50)

l=0

and, hence,
R L I ref
V out = -------------2N 1

N1

bl 2 l .

(1.51)

l=0

Hence, the R-2R ladder DAC in Fig. 1.14 is a binary-weighted DAC. A benefit of
this R-2R ladder DAC, compared with a binary-weighted current-steering DAC,
is that equal currents flow through all switches and, hence, it is easier to obtain
good mutual matching between the individual switches. Drawbacks of the R-2R
ladder architecture are that it requires high-precision linear resistors and that the
use of an operational amplifier may limit the speed of the circuit.
1.4.5 Resistor-String DACs
In a resistor-string DAC [9, 11], the 2 N different output voltage levels required in
an N -bit DAC are created with voltage division in a resistor string, as illustrated
in Fig. 1.15. The encoder maps the N -bit input x onto a control word where a
single bit is activated. The switch controlled by this bit connects the corresponding node in the resistor string to the positive input of the operational amplifier
that acts as a buffer. For large N , the numbers of switches and resistors are large.
In such cases, it is possible to use multi-stage resistor-string DACs [11, 19].

22

Converter Architectures
VDD
Iref
b0

Iref
b1

b3

Figure 1.14

Iref

Iref
bN2

Iref
bN1

2R

2R

IL

RL

Vout

2R

R-2R ladder DAC architecture.

x
encoder

Vref+
R
R

Vout
R
R
R
Vref
Figure 1.15

Resistor-string DAC architecture.

1.4.6 DACs
DACs utilizing modulation [20] are different from the previously presented
converter architectures in that oversampling is used in conjunction with preprocessing of the input in order to allow the input to be represented internally with

23

Introduction

fewer bits. The quantization noise added by the extra quantization step is shaped
with a feedback filter so that most of its power appears outside of the signal band.
A general modulator is shown in Fig. 1.16(a). This system is nonlinear and,
consequently, difficult to analyze. The quantizer is often modeled with the addition of an error signal, e(n) , as shown in Fig. 1.16(b), in order to get a linear system that is simpler to analyze. In the frequency domain, the output Y (z) can be
expressed in terms of the input X (z) and the quantization error E(z) as
Y (z) = STF(z)X (z) + NTF(z)E(z) ,

(1.52)

where STF is the signal transfer function and NTF is the noise transfer function.
It is desired that STF is an allpass or a lowpass filter and that NTF is a highpass
filter.
The shaping of the quantization noise is illustrated in Fig. 1.16(c) and (d) for a
first-order modulator with a 1-bit quantizer and OSR = 128 . For this first order
modulator, we have
STF(z) = 1

(1.53)

and
NTF(z) = 1 z 1 .

(1.54)

The spectrum of the 8-bit input is shown in Fig. 1.16(c), and the corresponding 1bit output is shown in Fig. 1.16(d). The main benefit of using a modulator
with a 1-bit output is that the output can be reconstructed with a DAC having
only two quantization levels. Even if these quantization levels differ from those
intended by the designer due to process variations, the INL and DNL will be 0 for
all codes. Hence, the static linearity of the 1-bit DAC is perfect. Using a firstorder modulator with a 1-bit quantizer requires a high OSR that often cannot be
afforded in high-speed communication applications. In order to reduce the OSR,
the use of multi-bit quantizers and/or higher-order modulators are required.

1.5 CMOS Technology

Complementary metal-oxide-semiconductor (CMOS) processes are popular for
implementing integrated circuits. This is mainly due to low cost, but also because
they enable the implementation of digital circuits with low power consumption.
The word complementary refers to the fact that both NMOS and PMOS transistors are available. An NMOS transistor consists of heavily N-doped drain and
source regions implanted in lightly P-doped silicon. The drain and source regions
are separated with a gate region. The gate of the transistor consists of a sheet of

24

CMOS Technology
x(n)

linear
feedback

y(n)

x(n)

filter

Modulator output
0
PSD [dB/Hz]

0
PSD [dB/Hz]

e(n)

(b)

Modulator input

50

f0
Frequency (log scale)
(c)

Figure 1.16

y(n)

filter
(a)

100

linear
feedback

fs/2

50

100

f0
Frequency (log scale)

fs/2

(d)

(a) General modulator and (b) modulator with quantizer modeled with an
added error signal. The spectra for the 8-bit input and the 1-bit output of a firstorder modulator (OSR = 128) are shown in (c) and (d), respectively.

polycrystalline silicon (poly), which is separated from the substrate with a thin
layer of silicon dioxide (oxide). Free electrons in the substrate can be attracted to
the region under the gate and form a conducting channel between the drain and
the source by applying a proper voltage at the gate. The principle of a PMOS
transistor is similar, but the type of doping used is opposite to that of the NMOS
transistor.
The DAC circuits in this work have all been implemented in CMOS technology.
A brief overview of the characteristics of CMOS transistors is given in this section.
1.5.1 Large-Signal Models
Simple large-signal models for CMOS transistors [11], assuming long-channel
devices, are presented in this section to illustrate the basic behavior of the
devices. These models are similar to that presented by Shichman and Hodges in
1968 [21]. As device sizes decrease, these models become less accurate. Therefore, circuit simulators often make use of more elaborate models to obtain results
with higher accuracy, such as the BSIM3 model [22].

25

Introduction

A symbol for an NMOS transistor is shown in Fig. 1.17(a). It has four terminals;
gate (G), source (S), drain (D), and bulk (B). In all implementations presented in
this work, the bulk terminal is connected to ground for all NMOS transistors. In
that case, the symbol in Fig. 1.17(b), where the bulk terminal is omitted, can be
used instead. Similar symbols for PMOS transistors are shown in Fig. 1.17(c) and
(d), where the omitted bulk terminal in Fig. 1.17(d) implies that the bulk is connected to the supply voltage ( V DD ).
D

ID
G
VGS

B
VBS

VDS

G
S

(a)
VSG

VSB
B
VSD

(b)
S
G

ID

D
(c)
Figure 1.17

(d)

Device symbols for (a) four-terminal NMOS transistor, (b) NMOS transistor
with the bulk connected to ground, (c) four-terminal PMOS transistor, and (d)
PMOS transistor with the bulk connected the supply voltage.

In the simple model, the transistors have three different regions of operation; the
cut-off region, the linear region, and the saturation region. The approximate current-voltage relationships for NMOS and PMOS devices are listed in the following sections. The model parameters, e.g., carrier mobility and body-effect
constants, for NMOS and PMOS transistor typically have different values. However, we use the same notation for the two transistor types in order to avoid the
use of additional indices.
NMOS Devices
An NMOS transistor operates in the cut-off region if
V GS < V T ,

(1.55)

where V T is the threshold voltage of the transistor. In the transistor model used
here,

26

CMOS Technology

ID = 0

(1.56)

in the cut-off region. In reality, a small subthreshold current flows in the device.
When V GS is increased such that
V GS V T ,

(1.57)

a channel of free electrons is formed under the gate and the transistor is conducting current.
In the linear operation region,
V DS < V GS V T = V eff ,

(1.58)

where V eff is the effective gate-to-source voltage. The current I D is modeled

with
2
V DS
W

I D = 0 C ox ----- V eff V DS ----------- ,

L
2

(1.59)

where 0 is the electron mobility and C ox is the oxide capacitance per unit area.
W and L are the width and the length of the transistor, respectively.
The saturation region is characterized by the relationship
V DS V eff

(1.60)

and the current in the saturation region is modeled with

0 C ox W 2
- ----- V ( 1 + ( V DS V eff ) ) .
I D = --------------2 L eff

(1.61)

is a parameter known as the channel-length modulation parameter and is

roughly proportional to 1 L . Due to the body effect, the threshold voltage of the
transistor is dependent on the bulk-to-source voltage according to
V T = V T, 0 + (

2 F V BS

2 F ) ,

(1.62)

where V T, 0 is the threshold voltage at zero V BS . The built-in Fermi potential,

F , and the body-effect constant, , are process dependent parameters.
PMOS Devices
A PMOS transistor in the cut-off region is characterized by

27

Introduction

V SG < V T ,

(1.63)

and the drain current is modeled with

ID = 0 .

(1.64)

A PMOS transistor is conducting current when

V SG V T .

(1.65)

In the linear region,

V SD < V SG V T = V eff ,

(1.66)

where V eff is the effective source-to-gate voltage. The current is modeled with
2
V SD
W
I D = 0 C ox ----- V eff V SD ---------- ,
L
2

(1.67)

where 0 is the hole mobility, which is typically a factor three or so lower than
the electron mobility for an NMOS transistor.
The transistor operates in the saturation region when
V SD V eff ,

(1.68)

and the current is modeled with

0 C ox W 2
- ----- V ( 1 + ( V SD V eff ) ) .
I D = --------------2 L eff

(1.69)

The threshold voltage, which is negative, varies with the source-to-bulk voltage
according to
V T = V T, 0 (

2 F V SB

2 F ) .

(1.70)

1.5.2 Small-Signal Models

The models presented in Sec. 1.5.1 have nonlinear relationships between currents
and voltages. Therefore, the analysis of a circuit containing more than just a few
transistors becomes complicated if these models are used. Linearized models, or
small-signal models, are commonly used in order to analyze the influence of a
small perturbation in some voltage or current [11].

28

CMOS Technology

A g-parameter small-signal model of an NMOS transistor is shown in

Fig. 1.18(a). The current and the voltages shown in the figure are the small signal
quantities, i.e., the deviations from the dc levels. The small-signal parameters are
given by
gm =

I D
,
V GS Q

g mbs =

(1.71)

I D
,
V BS Q

(1.72)

and
g ds =

I D
,
V DS Q

(1.73)

where the index Q indicates that the partial derivatives are evaluated in the quiescent point. For both the linear region and the saturation region, we have
gm
-.
g mbs = ------------------------------------2 2 F V BS

(1.74)

In analog circuits, the transistors are usually biased to operate in the saturation
region, because the transconductance, g m , is higher and the output conductance,
g ds , is lower than in the linear region for the same V GS . In the saturation region,
we have
id

G
vgs

gmvgs

gmbsvbs

gds vds
S

(a)
S
vsg

gmvsg

gmsbvsb

gds vsd
id

(b)
Figure 1.18

Simple small-signal models for (a) NMOS and (b) PMOS transistors.

29

Introduction

W
g m 2 0 C ox ----- I D
L

(1.75)

and
g ds I D .

(1.76)

For a PMOS transistor,

gm
-,
g msb = ------------------------------------2 2 F V SB

(1.77)

in both the linear region and the saturation region. Further, in the saturation
region, we have
W
g m 2 0 C ox ----- I D
L

(1.78)

and
g ds I D .

(1.79)

1.5.3 Parasitics
The transistor models discussed in Sec. 1.5.1 and Sec. 1.5.2 model the transistor
behavior for low signal frequencies. For higher frequencies, the transistor behavior is also influenced by capacitive parasitics [11]. Simple small-signal models of
NMOS and PMOS transistors with parasitic capacitances included are shown in
Fig. 1.19(a) and (b), respectively. In Fig. 1.19, it is assumed that the bulk terminals are connected to small-signal ground, i.e., constant voltages. The source-tobulk capacitance, C SB , and the drain-to-bulk capacitance, C DB , are depletion
capacitances in the reverse-biased p-n junctions between the source and the bulk
and the drain and the bulk, respectively. They also include the depletion capacitance between the conducting channel and the bulk. In the saturation region, the
channel is pinched off at the drain side, and the channel-to-bulk capacitance is
entirely associated with the source-to-bulk capacitance [11]. The gate-to-source
capacitance, C GS , and the gate-to-drain capacitance, C GD , are due to the thin
oxide layer between the gate and the substrate. They consist of an overlap capacitance, caused by a small overlap between the gate and the diffused drain and
source areas, and of a capacitance between the gate and the channel. Due to that
the channel is pinched off in the saturation region, the gate-to-channel capacitance is entirely associated with the gate-to-source capacitance.

30

CMOS Technology

CGD

CDB

CGS

gmvgs

gmbsvbs

gds
S
CSB

(a)
CSB
S
CGS

gmvsg

gmsbvsb

gds

D
CGD

CDB

(b)
Figure 1.19

Simple small-signal models for (a) NMOS and (b) PMOS transistors with parasitic capacitances included.

1.5.4 Device Matching

Due to variations in, e.g., oxide thickness and doping concentrations, the parameters of a manufactured device (transistor, resistor, capacitor, etc.) deviate from the
nominal values. Therefore, two devices on the same die that are designed to be
identical have different parameter values. This is referred to as mismatch or
matching errors. Two nominally identical rectangular devices are shown in
Fig. 1.20(a). The rectangles may represent, e.g., an MOS transistor gate, a parallel-plate capacitor, or a resistor. The devices have a nominal length L , a nominal
width W , and are separated by a distance D . Much of research on MOS matching properties is based on the work presented by Pelgrom in [23]. In [23], the
processes causing mismatch in a parameter P are divided into two different
classes. The processes in the first class cause short-distance variations, or local
variations, for which the correlation distance is much smaller than the device
dimensions. For this class, the resulting matching errors are independent of the
distance between the devices. However, parameters typically show a circular
value distribution over a wafer, as illustrated in Fig. 1.20(b). The processes in the
second class give rise to these global variations. Over a small area (e.g., a chip),
the global parameter variations are often approximated by a plane (i.e., the first31

Introduction

order Taylor expansion) as indicated in Fig. 1.20(b). The global variations are,
therefore, also referred to in terms of parameter gradients or as linearly graded
errors.

D
W
L
(a)

(b)
Figure 1.20

(a) Two nominally identical rectangular devices and (b) illustration of circular
parameter variation over a wafer.

Let P denote the difference in the value of parameter P between the two
devices. According to [23], P can be modeled as a stochastic variable with
Gaussian distribution having zero expectation value and variance
A P2
2
(P) = -------- + S P2 D 2 ,
WL

(1.80)

where A P and S P are proportionality constants for parameter P . A further analysis in [23], using the simple square-law model for a MOS device in saturation,
yields that the difference in drain current between two transistors has a Gaussian
distribution and that

32

CMOS Technology
2()
4 2(V T)
2(I D)
----------------------------+
--------------=
------------,
2
( V GS V T )
ID
2

(1.81)

where
W
= 0 C ox ----L

(1.82)

and 2() denotes the variance operator. Having well-matched drain currents is
important in order to obtain high accuracy in a current-steering DAC. Some general guidelines for obtaining good matching can be extracted from (1.80) and
(1.81). For example, the local variations have less influence on the parameters for
transistors with large areas than for transistors with small areas, and the influence
of the global variations is decreased if the devices are placed closer together.
There is, of course, a trade-off, since increasing the device dimensions also
causes an increase in the minimum required distance between two devices. From
(1.81), it can be concluded that increasing the effective gate-to-source voltage
decreases the influence of variations in the threshold voltage.
In [24], it is argued that (1.80) is applied incorrectly to the threshold voltage in
the analysis in [23], and a mismatch model, based on the BSIM3 MOS model,
that better fits observed data is derived. However, the general guidelines for transistor matching that were observed from (1.80) and (1.81) are still valid with this
more accurate mismatch model.
Apart from device geometries and biasing, there are other factors that influence
the matching accuracy. For example, wire routing in low-level metal layers over
transistors having critical matching requirements should be avoided [25]. Moreover, it is important that the devices have the same geometrical boundary conditions. Therefore, an array of transistors or capacitors is often surrounded by a
frame of unused dummy elements that ensures that the outer devices in the array
have the same surroundings as the inner devices.
1.5.5 CMOS Transistors in Current-Steering DACs
Two critical basic building blocks used in current-steering DACs are the current
source and the current switch. An overview on how these building blocks can be
implemented in CMOS technology is given in this section.

33

Introduction

The Current Source

The current delivered by an ideal current source is independent of the voltage
drop across it, i.e., it has infinite output impedance. A current source implemented with a single PMOS transistor, Msource, is shown in Fig. 1.21(a). For the
simple transistor model, the output resistance of this current source is
1
.
R out = ----------------------g ds, source

(1.83)

As discussed in Sec. 1.5.2, g ds is smaller (i.e., R out is larger) in the saturation

region than in the linear region. Hence, in order to obtain a high output resistance, Msource should be biased in the saturation region. For some applications,
the obtainable output resistance using a single transistor is too low. Increased output resistance can be obtained with the use of a cascode transistor [11], as illustrated in Fig. 1.21(b). The output resistance for the current source in Fig. 1.21(b)
is approximately
g m, casc
1
-.
R out ----------------------- -----------------g ds, source g ds, casc

(1.84)

Usually, g m g ds for a transistor biased in the saturation region. Hence, the output resistance for the current source using a cascode transistor is much higher
than for a single-transistor current source. For higher frequencies, the magnitude
of the output impedance is limited by capacitive parasitics. The output impedance of a current source is approximately
1 - + sC 1 ,
Z out = --------out
R

(1.85)

out

where C out is the effective capacitance to ground associated with the output node
of the current source. For the current source in Fig. 1.21(a), C out is approximately a parallel connection of C GD and C DB for transistor Msource. For the current source in Fig. 1.21(b), C out is approximately a parallel connection of C GD
and C DB for transistor Mcasc, the parasitics in transistor Msource are suppressed
due to the use of a cascode transistor. If the widths of Msource and Mcasc are
approximately the same, then C out is approximately the same for both types of
current source. Hence, their output impedances are approximately the same for
high frequencies.

34

CMOS Technology

Vbias

Vbias

Msource

Vcasc

Mcasc

Msource
Iout

Iout
(a)
Figure 1.21

(b)

PMOS current source implemented (a) with a single transistor and (b) with a
cascode transistor.

The Switch
A differential current switch can, e.g., be implemented with two PMOS transistors, as depicted in Fig. 1.22(a). If both transistors are simultaneously cut off,
charge is accumulated at the output node of the current source. This results in
severe glitches in the transient response of the DAC when one of the transistors in
the switch starts to conduct. Therefore, when the state of the switch is changed, it
is important to have a short moment when both transistors are conducting in
order to avoid charge accumulation [26]. This is obtained with the nonoverlapping control signals shown in Fig. 1.22(b). If NMOS transistors are used in the
switch, the control signals should instead be overlapping in order to avoid having
both transistors simultaneously off.
Q+
Q

Q+

Q
I+

Voltage

Iin
high

I
low
Time
(a)

Figure 1.22

(b)

(a) Differential switch implemented with two PMOS transistors and (b) proper
control signals for the switch in (a).

35

Introduction

1.6 Outline of the Thesis

A brief outline of the remainder of this thesis is given in this section. The content
of each chapter is discussed together with short remarks on the authors contributions in the different fields. Some of the work presented in this thesis has previously been presented in the authors licentiate thesis [27], whereas some of the
ideas presented in [27] that have not been further investigated are omitted in this
thesis.
1.6.1 Chapter 2
Behavioral-level modeling and simulation of current-steering DACs is presented
in Chapter 2. In order to interpret presented simulation results correctly, it is
important to know how the results have been evaluated. Therefore, the methods
used in this thesis for evaluation of static errors are outlined in Sec. 2.1.
One limiting factor for the static linearity of a current-steering DAC is mismatch
between current sources. In Sec. 2.2, behavioral-level modeling of matching
errors is discussed. Modeling of random matching errors, which is used in later
parts of the thesis for evaluation of different techniques, is presented in
Sec. 2.2.2. This type of model is well known and has been used previously by
others. In Sec. 2.2.3, modeling of linearly graded matching errors is discussed.
The authors contribution to this part is a mathematical analysis of this type of
error.
Another factor that limits the linearity, both static and dynamic, is the finite output impedance in the current sources which is discussed in Sec. 2.3. This is a well
known problem. The authors contribution to the field is the development of two
different behavioral-level models presented in Sec. 2.3.2.
Glitches present in the DAC output are yet another factor that degrades the DAC
linearity discussed in Chapter 2. One source of glitches is asymmetry in the settling behavior when switching on and off a current source. A model of this specific glitch source has been developed by the author as a generalization of a
model presented previously by others. The developed model is presented in
Sec. 2.4 together with extensive mathematical analyses. All work presented in
Sec. 2.4 is original work by the author.
1.6.2 Chapter 3
The code used for representing the digital control word in a current-steering DAC
has a large influence on the circuit performance. Different types of codes and
their respective properties are discussed in Chapter 3. First, the well known
binary-weighted and segmented DAC architectures are presented in Sec. 3.1 and

36

Outline of the Thesis

Sec. 3.2, respectively. Then, the novel decomposed DAC architecture, which has
been developed by the author together with Prof. Mark Vesterbacka is presented
in Sec. 3.3. This is followed by an extension of the decomposed architecture,
denoted the partially decomposed architecture, proposed by the author which is
presented in Sec. 3.4, and a short discussion on miscellaneous other codes given
in Sec. 3.5.
The behavioral-level DAC models of random matching errors and glitches presented in Chapter 2 are utilized to compare the different types of architectures
with respect to their impact on the circuit performance in Sec. 3.6. All work presented in Sec. 3.6 is original work by the author.
In order for an architecture to be of practical interest, it must be possible to
implement at a reasonable hardware cost, e.g., in terms of circuit area and power
consumption. In Sec. 3.7, means for implementing the digital encoders required
in the segmented and decomposed DAC architectures are discussed. The intention with this section is to show that the hardware overheads for implementing
these encoders are not unreasonably large but rather quite small.
1.6.3 Chapter 4
In Chapter 4, different techniques for improving the DAC linearity are presented.
A family of techniques for reducing the distortion due to mismatch known as
dynamic element matching (DEM) is presented in Sec. 4.1. Presentations of
well-known DEM techniques in Sec. 4.1.1 - Sec. 4.1.3, are followed by a presentation of a DEM technique for the decomposed DAC architecture proposed by the
author and Prof. Mark Vesterbacka in Sec. 4.1.4.
A well-known technique for reducing the influence of graded parameter variations over the chip area denoted distributed biasing is presented in Sec. 4.2. This
technique is utilized in two of the DAC implementations presented in Chapter 5.
An oversampling technique based on modulation developed by the author is
presented in Sec. 4.3. The technique utilizes a model of the DAC nonlinearity in
a feedback loop for spectral shaping of the resulting distortion. In Sec. 4.3.2, the
technique is used for suppressing the influence of output impedance related
errors utilizing one of the models presented in Sec. 2.3.2. The utilization of the
technique for enhancing the yield of binary-weighted DACs with respect to nonlinearity errors caused by mismatch is presented in Sec. 4.3.3. All the work presented in Sec. 4.3 is original work by the author.

37

Introduction

1.6.4 Chapter 5
The DAC chips developed in this work used for investigating different techniques
and ideas are presented in Chapter 5. Overall descriptions of design strategies
and measurement setups used are presented in Sec. 5.1, followed by presentations of the different implementations given in chronological order.
The first chip developed in this work is a 14-bit DAC utilizing 5-bit segmentation
and is presented in Sec. 5.2. The chip was designed in corporation with M.Sc.
Niklas U Andersson and Ph.D. J Jacob Wikner, but a major part of the design
work for this circuit was performed by the author. The circuit has been utilized
for measurements on the technique for spectral shaping of nonlinearity errors
presented in Sec. 4.3.2.
The second chip, presented in Sec. 5.3, is a 14-bit DAC that was developed for
evaluation of dynamic element matching techniques. Included in this section is a
comparison between measurement and simulation results. A majority of the
design and simulations were performed by M.Sc. Niklas U Andersson. The
authors contribution to the work includes design of miscellaneous digital building blocks and development of models used in the simulations.
The third chip, presented in Sec. 5.4, is a dual 14-bit DAC implemented with a
doubly segmented architecture. The chip utilizes distributed biasing discussed in
Sec. 4.2 for suppression of graded parameter variations over the chip area. The
work performed on this chip was evenly distributed between the author and
M.Sc. Niklas U Andersson and was assisted by Ph.D. J Jacob Wikner.
The fourth chip, which was designed by the author and is presented in Sec. 5.5, is
a 12-bit configurable DAC used for comparison between the decomposed architecture, proposed in Sec. 3.4, with the well-known segmented and binaryweighted architectures. A result of the design work is a design methodology for
efficient layout generation based on parameterized cells. This methodology is
also overviewed in Sec. 5.5.

1.7 Publications
Publications related to the work presented in this thesis authored or coauthored
by the author are listed in this section. The publications are listed in chronological order for each category. Publications upon which the thesis is based are
marked with an asterisk (*) before the number in the list below, whereas remaining publications cover related work not included in the thesis.

38

Publications

1.7.1 Journal Publications

*1

N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,

Models and implementation of a dynamic element matching DAC,
Kluwer International Journal of Analog Integrated Circuits and Signal
Processing, Special Issue: Selected Papers from the NORCHIP 2001
Conference, vol. 34, no. 1, pp. 7-16, Jan. 2003.

*2

K.O. Andersson and M. Vesterbacka, Modeling of glitches due to rise/fall

asymmetry in current-steering digital-to-analog converters, submitted to
IEEE Trans. Circuits Syst. Part I: Regular Papers.

*3

K.O. Andersson and M. Vesterbacka, A parameterized cell-based design

approach for digital-to-analog converters, submitted to Annals for Micro
and Nano Systems: Special Issue for the IWSOC 2004 Conference.

1.7.2 Conference Publications

*4

K.O. Andersson and J.J. Wikner, Modeling of the influence of graded

element matching errors in CMOS current-steering DACs, Proc.
NORCHIP Conference, pp. 399-404, Oslo, Norway, Nov. 8-9, 1999.

*5

K.O. Andersson and J.J. Wikner, Characterization of a CMOS currentsteering DAC using state-space models, Proc. 43rd Midwest Symposium
on Circuits and Systems, pp. 668-671, Lansing, Michigan, USA, Aug. 8-11,
2000.

*6

K.O. Andersson, N.U. Andersson, and J.J. Wikner, Spectral shaping of

DAC nonlinearity errors through modulation of expected errors, Proc.
IEEE International Symposium on Circuits and Systems, vol. 3, pp. 417420, Sydney, Australia, May 6-9, 2001.

*7

N.U. Andersson, K.O. Andersson, J.J. Wikner, and M. Vesterbacka,

Models and implementation of a dynamic element matching DAC, Proc.
NORCHIP Conference, pp. 155-160, Kista, Sweden, Nov. 12-13, 2001.

K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner, A

differential DAC architecture with variable common-mode level, Proc.
IEEE International Symposium on Circuits and Systems, vol. 1, pp. 113116, Scottsdale, AZ, USA, May 26-29, 2002.

39

Introduction

K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner,

Combining DACs for improved performance, Proc. 4th IEE
International Conference on Advanced A/D and D/A Conversion
Techniques and their Applications, Prague, Czech Republic, June 26-28,
2002.

10 M. Vesterbacka, K.O. Andersson, N.U. Andersson, and J.J. Wikner,

Using different weights in DACs, Proc. 4th IEE International
Conference on Advanced A/D and D/A Conversion Techniques and their
Applications, Prague, Czech Republic, June 26-28, 2002.
* 11 K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner, A
method of segmenting digital-to-analog converters, Proc. IEEE Southwest
Symposium on Mixed-Signal Design, pp. 32-37, Las Vegas, NV, USA, Feb.
23-25, 2003.
* 12 K.O. Andersson, N.U. Andersson, M. Vesterbacka, and J.J. Wikner, A 14bit dual current-steering DAC, Proc. Swedish System-on-Chip Conference
2003, Eskilstuna, Sweden, Apr. 8-9, 2003.
* 13 K.O. Andersson and M. Vesterbacka, A testbed for different codes in
digital-to-analog converters, Proc. Swedish System-on-Chip Conference
2004, Bstad, Sweden, Apr. 13-14, 2004.
* 14 K.O. Andersson and M. Vesterbacka, Partial decomposition of digital-toanalog converters, Proc. IEEE Mediterranean Electrotechnical
Conference, Dubrovnik, Croatia, May 12-15, 2004.
15 E. Sll, M. Vesterbacka, and K.O Andersson, A study of digital decoders
in flash analog-to-digital converters, Proc. IEEE International Symposium
on Circuits and Systems, Vancouver, Canada, May 23-26, 2004.
16 E. Sll, K.O Andersson, and M. Vesterbacka, A dynamic element
matching technique for flash analog-to-digital converters, Proc. 6th
Nordic Signal Processing Symposium, Espoo, Finland, June 9-11, 2004.
* 17 K.O. Andersson and M. Vesterbacka, A parameterized cell-based design
approach for digital-to-analog converters, Proc. IEEE International
Workshop on System-on-Chip for Real-Time Applications, Banff, Canada,
Jul. 19-21, 2004.
* 18 K.O. Andersson and M. Vesterbacka, Dynamic element matching in
decomposed digital-to-analog converters, Proc. IEEE NORCHIP Conf.,
Oslo, Norway, Nov. 8-9, 2004.

40

Abbreviations

* 19 K.O. Andersson and M. Vesterbacka, A yield-enhancement strategy for

binary-weighted DACs, submitted to the European Conference on Circuit
Theory and Design, Cork, Ireland, Aug. 29-Sept. 1, 2005.
20 E. Backenius, E. Sll, K.O. Andersson, and M. Vesterbacka,
Programmable Reference Generator for On-Chip Measurement,
submitted to the European Conference on Circuit Theory and Design,
Cork, Ireland, Aug. 29-Sept. 1, 2005.
1.7.3 Theses
* 21 O. Andersson, Mismatch Modeling and Design of CMOS Current-Steering
Digital-to-Analog Converters, Master Thesis, LiTH-ISY-EX-3026,
Linkping, Sweden, 1999.
* 22 K.O. Andersson, Studies on Performance Limitations in CMOS DACs,
Linkping studies in science and technology, Thesis No. 976, Linkping,
Nov. 2002, ISBN 91-7373-452-7.
1.7.4 Patents
23 K.O. Andersson, Improved current-steering D/A conversion, Swedish
patent SE-0000731, 2001.
* 24 K.O. Andersson and J.J. Wikner, Digital-to-analog converter having error
correction, Swedish patent SE-0201272, 2003.
25 K.O. Andersson, Current-steering DAC, pending Swedish patent.

1.8 Abbreviations
The abbreviations used in the thesis are listed below.
ADC

Analog-to-digital converter

ADSL

Asymmetric digital subscriber line

AFE

Analog front end

CMOS

Complementary metal-oxide-semiconductor

CO

Central office

CPE

Customer premises equipment

DAC

Digital-to-analog converter

DCVS

Differential cascode voltage switch

41

Introduction

DEM

Dynamic element matching

DFT

Discrete Fourier transform

DMT

Discrete multi-tone

DNL

Differential nonlinearity

DSL

Digital subscriber line

DSP

Digital signal processing

ECH

Echo-canceled hybrid

ENOB

Effective number of bits

FDM

Frequency division multiplexing

FFT

Fast Fourier transform

FIR

Finite-length impulse response

FRDEM

Full randomization dynamic element matching

GPIB

General purpose interface bus

HDSL

High bit-rate digital subscriber line

IFFT

Inverse fast Fourier transform

INL

Integral nonlinearity

LUT

Look-up table

LVDS

Low voltage differential signalling

MTPR

Multi-tone power ratio

OSR

Oversampling ratio

PAM

Pulse-amplitude modulation

PC

Personal computer

PCB

Printed circuit board

POTS

Plain old telephone service

PRBS

Pseudorandom binary sequence

PRDEM

Partial randomization dynamic element matching

42

Abbreviations

PSD

Power spectral density

QAM

Quadrature amplitude modulation

SDR

Signal-to-distortion ratio

SFDR

Spurious-free dynamic range

SHDSL

Single-pair high-speed digital subscriber line

SNDR

Signal-to-noise-and-distortion ratio

SNR

Signal-to-noise ratio

VDSL

Very high bit-rate digital subscriber line

43

Introduction

44

2 Modeling of CurrentSteering DACs

Transistor-level simulations of complex circuits using accurate transistor models
require long simulation times. For example, an N -bit current-steering DAC contains 2 N 1 unit current sources, a large number of switches, circuitry for
encoding the input to the corresponding control word and for generation of
proper control signals, etc. For N in the order of 12 to 14, it may take several
days merely to simulate the circuits response to a ramp input going through all
possible input values. Hence, a transistor-level model of a DAC used in a system
simulation is likely to be a severe bottleneck limiting the overall system simulation speed. Moreover, investigations of stochastic parameter variations using,
e.g., Monte Carlo analyses require multiple simulation runs with different parameter values, making the use of models on transistor level unsuitable.
The reasons above motivate the need for behavioral-level models with reasonably
short simulation times. Behavioral-level models can also be used to find the
requirements on different building blocks on high abstraction levels, supporting
the use of efficient top-down design methodologies [28].
Models of different nonideal properties in current-steering DACs that have been
used and developed in this work are presented in this chapter. Evaluation of performance metrics in the presence of static errors are discussed in Sec. 2.1. Modeling of the influence of matching errors in current sources is presented in
Sec. 2.2, and the influence of finite output impedance in the current sources is
discussed in Sec. 2.3. Sec. 2.4 is devoted to behavioral-level modeling of glitches
due to asymmetry in the settling behavior when switching on and off a current
source.

45

Modeling of Current-Steering DACs

Modeling of nonlinear behavior in analog circuits is often performed using polynomial models, such as Taylor or Volterra series expansions [13, 29]. Some initial attempts of characterizing DACs using Volterra models were made. These
were, however, unsuccessful in capturing the nonlinear behavior of the currentsteering DAC except for in very limited frequency bands. Therefore, polynomialtype models are discarded in this thesis.

2.1 Evaluation of Performance Metrics for Static Errors

If only static errors are considered, the DAC output level y(x) is the same every
time a certain input x is applied, regardless of previous input values. For static
errors, the DAC can be characterized by DNL and INL metrics, but also in terms
of, e.g., the SNDR. All these metrics are largely dependent on the choice of the
nominal transfer characteristics
y nom(x) = Kx + y offset ,

(2.1)

where K is the nominal gain and y offset is the nominal offset. In this section, we
discuss and motivate the approach used in this work for evaluation of performance metrics for static errors. For the calculation of the SNDR, it is required
that the total power of noise and distortion, P nd is calculated. For an input
sequence x(n) , n = 0, 1, , n max , P nd is given by
1
P nd = --------------------n max + 1

n max

[ y(x(n)) ynom(x(n)) ]2 .

(2.2)

n=0

If the input value x has the probability p(x) to occur, we may express P nd as
2N 1

P nd =

p(x) [ y(x) y nom(x) ] 2 .

(2.3)

x=0

In, e.g., an ADSL modem, the signal is transferred to the copper wire via a transformer that removes the dc component of the signal. Hence, we are not interested
in the dc term of the error y y nom . If the DAC is subject to a pure gain error
(i.e., a deviation from the desired K ), the error is a linear function of the input
and cannot easily be distinguished from the nominal output signal in, e.g., measurements with a spectrum analyzer. Therefore, we choose the values of K and
y offset that minimizes P nd . A consequence of this is that we allow different
nominal characteristics for different input sequences.
An endpoint definition of the nominal characteristics

46

Modeling of Matching Errors

y(2 N 1) y(0)- and y

K = ------------------------------------offset = y(0) ,
2N 1

(2.4)

has been used in many analyses of the influence of static errors on the INL presented in the literature [30, 31, 32, 33]. However, in this work we choose a definition that relates the INL to P nd , since, in the authors opinion, this choice better
reflects the DAC behavior in the targeted applications. K and y offset are chosen
to minimize (2.3) for the situation where all input values are equally probable.
Hence, the nominal characteristics is a best-fit straight line with respect to the
actual characteristics in the least-squares sense. With this choice, we can express
P nd for a signal where every input value is equally probable as
1 P nd = --------------2N 1

2N 1

K 2 INL 2(x) .

(2.5)

x=0

Other choices of the nominal characteristics may be suitable in other types of

applications. For example, if it is crucial that the DAC is monotone over the
whole input range, the maximum value of INL(x) is a relevant value. In that situation, it is reasonable to choose the nominal characteristics that minimizes the
maximum INL(x) .

2.2 Modeling of Matching Errors

In this section, we discuss behavioral-level modeling of the influence of matching
errors on the DAC performance. Only binary-weighted DACs, for which the digital control word is in binary-offset representation and the nominal weights are
wk = 2 k

(2.6)

are considered in this section. The models discussed here are applied to other
DAC architectures in later chapters.
The mathematical notation used for the modeling of matching errors in this work
is introduced in Sec. 2.2.1. As discussed in Sec. 1.5.4, sources of matching errors
in CMOS transistors is usually divided into two main groups; short-distance variations and long-distance variations. Modeling of the former type is discussed in
Sec. 2.2.2, whereas the influence of the latter type is modeled in Sec. 2.2.3.

47

Modeling of Current-Steering DACs

2.2.1 Notation
On a behavioral level, matching errors in the transistors constituting the current
sources can be modeled with additional error current sources connected in parallel with the nominal current sources. This is illustrated for a unit current source in
Fig. 2.1(a). The output current is given by
I unit, m = I unit + m ,

(2.7)

where m is an index that uniquely identifies the unit current source, I unit is the
nominal unit current, and m is the error current associated with the unit current
source.
A similar model for a weighted current source with weight w l is shown in
Fig. 2.1(b). A current source with weight w l is usually implemented with w l unit
current sources connected in parallel. Assume that the indices associated with
these unit current sources constitute a set A l . Then,
I l = w l I unit +

m Al

m ,

(2.8)

where the first term is the nominal output current and the second term is the error
current l .

Iunit

dm
Iunit, m
(a)

Figure 2.1

wlIunit

Dl
Il
(b)

Models of (a) a unit current source and (b) a weighted current source subject to
matching errors.

2.2.2 Modeling of Random Matching Errors

The influence of short-distance variations is usually modeled by letting the errors
m be mutually uncorrelated stochastic variables (or observations of mutually
uncorrelated stochastic variables) having Gaussian distribution with zero expectation value and standard deviation , i.e.,
m N(0, ) .
For the weighted current sources, we have
48

(2.9)

Modeling of Matching Errors

l =

m ,

mA

(2.10)

which is a sum of w l mutually uncorrelated m . Hence,

l N ( 0, w l ) .

(2.11)

Moreover, the errors l are mutually uncorrelated since the sets A l are disjoint.
Let b lx denote the individual bits of the control word for a given input x . The
DNL errors are given by

l ( blx blx 1 )I l

( b lx b lx 1 ) l
I unit
l
DNL(x) = ------------------------------------------ 1 = ---------- + ------------------------------------------- 1 . (2.12)
K
K
K
The nominal step size K is different for different stochastic outcomes of the
matching errors. However, if the number of bits is large and is reasonably
small,
K I unit

(2.13)

is a good approximation. Setting K equal to I unit in (2.12) yields

l ( blx blx 1 )l

DNL(x) = -------------------------------------------- .
I unit

(2.14)

The numerator in (2.14) is a sum of uncorrelated stochastic variables with Gaussian distributions. Hence, DNL(x) is a stochastic variable with Gaussian distribution with zero expectation value whose variance is given by

1
( b lx b lx 1 ) 2 Var( l) =
Var(DNL(x)) = ---------2
I unit
l
2
2
x b x 1 w = ----------S
= ---------b
( x) ,
l
l
l
2
2
I unit
I
unit
l

(2.15)

l blx blx 1 wl

(2.16)

where
S ( x) =

49

Modeling of Current-Steering DACs

is the total number of switched unit current sources in the transition from x 1 to
x at the DAC input. S(x) is only dependent on how the digital input is encoded to
form the control word. Hence, S(x) can be used as a high-level performance metric to compare different encoding strategies; a small S(x) results in a small probability of a large DNL(x) , whereas a larger S(x) results in a larger probability of
a large DNL(x) . S(x) is plotted for a 12-bit binary-weighted DAC in Fig. 2.2.
The large peak at the middle code transition typically results in large DNL errors,
making the binary-weighted DAC architecture unsuitable for obtaining good
static linearity.
S(x), 12-bit binary-weighted DAC

S(x)

4095

2047
1023
511
1

Figure 2.2

2048
x

4095

S(x) plotted as a function of x for a 12-bit binary-weighted DAC.

Several analyses on how random matching errors influence the INL of a DAC
have been presented in the literature [30, 31, 32, 33]. An endpoint definition of
the nominal characteristics (see (1.23)) is used in all the analyses presented in
[30, 31, 32, 33]. The DAC yield was defined in [30, 31, 32] as the relative number of DACs having
max INL(x) < 0.5 .
x

(2.17)

This approach is not suitable in this work, since it rules out a DAC with
INL(x) = 0.5 for x = x 0 and
INL(x) 0 otherwise,

(2.18)

while accepting a DAC with

INL(x) = 0.499 for every x ,

50

(2.19)

Modeling of Matching Errors

where the latter DAC clearly has a higher associated average power of noise and
distortion (calculated with (2.5)) than the former.
The approach favored in this work is to determine the yield in terms of the
SNDR. As an example, we consider a Monte Carlo type analysis of a 12-bit
binary-weighted DAC. The matching errors are characterized by the relative standard deviation
- = 10 % ,
--------I unit

(2.20)

and simulations are performed for 10 4 different stochastic outcomes. The input
x(n) consists of clipped and quantized values of observations from uncorrelated
stochastic variables with Gaussian distribution having expectation value
( 2 12 1 ) 2 and standard deviation 464, yielding an approximate clipping probability of 10 5 . The length of the test signal is set to 2 14 samples. P nd is evaluated in accordance with the discussion in Sec. 2.1, and the signal power is
calculated with

1P signal = ------[y
(x(n)) y nom(x) ] 2 ,
2 14 n nom

(2.21)

where x denotes the average value of the input x(n) . A histogram of the resulting
SNDR values is shown in Fig. 2.3. We let SNDR req denote the required SNDR,
and define the yield as the relative number of DACs having SNDR SNDR req .
The yield resulting from the simulations is plotted as a function of SNDR req in
Fig. 2.3(b). Plots similar to that shown in Fig. 2.3(b) are used in Chapter 4 for
illustration of how the use of different techniques for error compensation influence the DAC performance.
2.2.3 Modeling of Linearly Graded Matching Errors
In this section we analyze the influence of linearly graded matching errors on the
linearity of a binary-weighted DAC using a naive layout strategy. The analysis
was first presented in [34].
When implementing current-steering DACs, it is common to arrange the unit current sources in an array, as illustrated in Fig. 2.4(a), where each square represents
a unit current source. For the analysis presented in this section, each unit current
source has associated geometrical X and Y coordinates according to Fig. 2.4(a)
(capital coordinate labels are used to clearly distinguish the coordinates from signals x(n) and y(t) ). Here, we normalize the coordinate system such that the distance between adjacent unit current sources is unity. We let I unit, ( X , Y ) denote

51

Modeling of Current-Steering DACs

SNDR histogram, 12-bit binary-weighted DAC

No. of outcomes

1500

1000

500

0
35

40

45

50
SNDR

55

60

65

(a)

Yield [%]

Yield, 12-bit binary-weighted DAC

100
90
80
70
60
50
40
30
20
10
0
35

40

45

50
SNDRreq

55

60

65

(b)
Figure 2.3

Results from the Monte Carlo type analysis of the 12-bit binary-weighted DAC.
A histogram of the obtained SNDR values are plotted in (a), and the yield is
plotted versus the required SNDR in (b).

the output current from the unit current source whose center coordinate is
( X , Y ) . In accordance with the discussion on long-distance parameter variations
in Sec. 1.5.4, we make a first-order approximation of the unit currents yielding
I unit, ( X , Y ) = I unit + k X X + k Y Y .
The matching error ( X , Y ) is

52

(2.22)

Modeling of Matching Errors

( X, Y ) = k X X + k Y Y .

(2.23)

One approach for assigning unit current sources to the different bits in a binaryweighted DAC is illustrated for the 6-bit case in Fig. 2.4(b). This approach results
in simple routing of wires for connecting the unit current sources in parallel, but
is known to have poor properties for suppressing linearly graded matching errors.
Here, we use this approach to illustrate the influence of linearly graded matching
errors on the DAC linearity. The assignment of unit current sources is characterized by two parameters; the number of bits, N , and the number of weighted current sources fitted into the bottom row of the array, M . In the example in
Fig. 2.4(b), N = 6 and M = 3 . The current source in the lower right corner of
Fig. 2.4(b) is an unused dummy element.
Y

(a)
Figure 2.4

5
5
5
5
4
4
3
2

5
5
5
5
4
4
3
2

5
5
5
5
4
4
3
2

5
5
5
5
4
4
3
2

Y
5
5
5
5
4
4
3
1

5
5
5
5
4
4
3
1

5
5
5
5
4
4
3
0

5
5
5
5
4 X
4
3

(b)

(a) Array of unit current sources and (b) unit current source assignment for a 6bit binary-weighted DAC.

According to analyses presented in [27] and [34], the matching errors l can be
approximated with
kY l

------ ( 2 2 l + N M )
for l = 0, , M 1

2
l =
,
kY
2l

M
l
+
N

M
-(3 2
2
) for l = M , , N 1
----2

(2.24)

where the influence of parameter k X has been neglected since it only influences
the errors for the M LSBs which are typically much smaller than for the more
significant bits.
Assuming that the individual bits, b l(n) , of the input are uncorrelated, the power
of the error signal caused by mismatch can be approximated with [27, 34]

53

Modeling of Current-Steering DACs

2 4N - 2
P error = ----------------------k .
210 2 2M Y

(2.25)

For a sinusoidal signal, acos(t) , the signal power is given by

a2 .
P signal = ----2

(2.26)

Normalizing the DAC output by setting I unit = 1 yields that the amplitude of a
full-scale sinusoidal signal is
2N 1
a = ---------------- 2 N 1 ,
2

(2.27)

where the approximation is valid if N is large, i.e., 2 N 1 . For this signal,

2N
---------- .
P signal = 2
8

(2.28)

Further, the power of the quantization noise is given by

1- .
P Q = ----12

(2.29)

Assuming that the error caused by mismatch and the quantization error are
uncorrelated, we can express SNDR as
P signal
105 2 2 ( N + M ) - .
SNDR = --------------------------= ------------------------------------------------------P error + P Q
4 2 4N k Y2 + 70 2 2M

(2.30)

For large k Y , the second term in the denominator can be neglected and
SNDR 14.0 + 6.0 ( M N ) 20log 10( k Y ) dB .

(2.31)

In [34], there is an analysis of SFDR due to graded matching errors utilizing a

Fourier series expansion of an approximated error signal to estimate the power of
the spurious tones. The resulting expression was given as
SFDR = 21.6 + 6.0 ( M N ) 20log 10( k Y ) dB .

(2.32)

Behavioral-level simulations were performed to check the validity of (2.31) and

(2.32). The parameter values N = 14 and M = 7 were used in the simulations.
Simulated and calculated values of SNDR are plotted as functions of k Y in
Fig. 2.5(a). Good agreement is observed between the two curves. The discrep-

54

Modeling of Matching Errors

SNDR vs. |k |
Y

90
simulated
calculated

80
SNDR [dB]

70
60
50
40
30
20
10 7
10

10

10

|kY|

10

10

10

(a)

SFDR [dB]

SFDR vs. |kY|

120
110
100
90
80
70
60
50
40
30
20
10 7
10

simulated
calculated

10

10

|kY|

10

10

10

(b)
Figure 2.5

Simulated and calculated values of (a) SNDR and (b) SFDR plotted as functions
of k Y .

ancy (approximately 3 dB for k Y > 10 5 ) is due to that the assumption that the
individual bits are uncorrelated is incorrect for a sinusoidal input. An extended
analysis given in [34], that takes the correlation between b N 1(n) and b N 2(n)
into account, yields a maximum deviation of approximately 0.1 dB. Simulated
and calculated values of SFDR are plotted as functions of k Y in Fig. 2.5(b). A
good agreement between calculated and simulated values is observed also for the

55

Modeling of Current-Steering DACs

SFDR. For small k Y , the simulated SFDR is limited by the noise floor given by
the quantization noise, which explains the discrepancy between the two curves
for small k Y .
As mentioned in the beginning of this section, the simple approach for assigning
unit current sources to the different bits illustrated in Fig. 2.4(b) has poor properties for suppressing linearly graded matching errors. Several strategies of assigning unit current sources developed for suppressing the influence of linearly
graded matching errors appear in the literature (e.g., [35, 36, 37, 38, 39, 40]).
The principle behind all of these strategies is to spread out the unit current
sources that constitute a weighted current source over the array. The improved
performance resulting from these methods comes to the cost of increased wirerouting complexity. A simple modification of the original approach illustrated in
Fig. 2.4(b) is illustrated in Fig. 2.6(a). For the modified approach, half of the unit
current sources have been moved to the bottom of the array, which results only in
a slight increase of wire-routing complexity. The influence on the DAC performance is illustrated in Fig. 2.6(b), where simulated values of SNDR for the original and modified approaches are plotted as functions of k Y . The input signal
used is a full-scale sinusoid, and the parameter values are N = 14 and M = 7 .
For large values of k Y , the modified approach results in approximately 11 dB
higher SNDR than the original approach.

2.3 Modeling of Finite Output Impedance

An ideal current source delivers the same current regardless of the voltage across
it, i.e., it has infinite output impedance. When implementing current sources in,
e.g., CMOS or bipolar technologies, the output impedance is finite. In this section, we present DAC models that include this property and analyze the influence
on the DAC linearity.
2.3.1 Finite Output Resistance
In this section, we examine what influence the finite output resistance has on the
transfer characteristics of the DAC. The results presented here have previously
been presented by Wikner in [41], and are not original parts of this work. It is
included here because it provides a good starting point for the modeling of finite
output impedance, including capacitive parts, in Sec. 2.3.2.
Assume that we have unit current sources with finite output resistance, R unit . For
input code x there are x unit current sources connected in parallel to the output
node. The equivalent circuit for the DAC model is shown in Fig. 2.7.
The output voltage of the circuit in Fig. 2.7 is

56

Modeling of Finite Output Impedance

5
5
4
4
3
2
5
5

5
5
4
4
3
2
5
5

5
5
4
4
3
2
5
5

Y
5
5
4
4
3
1
5
5

5
5
4
4
3
2
5
5

5
5
4
4
3
1
5
5

5
5
4
4
3
0
5
5

5
5
4
4
3 X
5
5

(a)
SNDR vs. |kY|
90
original
modified

80
SNDR [dB]

70
60
50
40
30
20
10 7
10

10

10

|kY|

10

10

10

(b)
Figure 2.6

(a) Illustration of a modified approach for assigning unit current sources and (b)
SNDR comparison between the original and the modified approaches.
VDD
xIunit

Runit/x
Vout(x)
RL

Figure 2.7

Equivalent model of current-steering DAC with finite output resistance in the

current sources.

57

Modeling of Current-Steering DACs

V DD
x
---------------------------- R L ,
V out(x) = I unit + ----------RL
R unit
1 + ----------- x
R unit

(2.33)

which clearly is a nonlinear function of x . Hence, the finite output resistance in

the current sources introduces nonlinear behavior, and we can conclude that is
important to have high output resistance compared with the load resistance to get
high linearity. Equation (2.33) can be used to find design criteria for the output
resistance of the current sources [42].
2.3.2 Finite Output Impedance
In this section, modeling of the influence of finite output impedance, including
capacitive parasitics, is discussed. The work presented in this section has previously been presented in [27] and [43]. First, a simple DAC model with linearized
components is analyzed. The system of differential equations that characterizes
this model is written on a state-space form and can be solved with standard methods within a numerical computation environment, e.g., MATLAB. This model is
here referred to as the state-space model. Then, a model with lower computational complexity, which enables shorter simulation times, is presented. The
parameters for this low-complexity model can be extracted from simulations on
the state-space model, yielding good agreement between the two models.
State-Space Model
The modeling of the current source and the switch is considered first. In previous
presentations of the model [27, 43], the current source and the switch were considered separately. The switch was modeled with a resistance, which is inaccurate
if the switch transistor is operated in the saturation region. Therefore, a different
approach where the switch and the current source are modeled together is used
here.
The model of the combined current source and switch is shown in Fig. 2.8(a).
There are three important parameters for this model; the resistances R l and R s, l
and the capacitance C l . We consider two different types of CMOS implementations of the current source and switch, which are shown in Fig. 2.8(b) and (c).
The implementation shown in Fig. 2.8(b) is a PMOS current source with an
NMOS switch, whereas a PMOS current source with a PMOS switch is shown in
Fig. 2.8(b). In the following, we discuss the mapping of these two types of circuit
elements to the linearized model in Fig. 2.8(a). There are, of course, also two
types of circuit elements with NMOS current sources. These are not discussed

58

Modeling of Finite Output Impedance

here, but the derivation of model parameters is similar. This is also true for current sources utilizing cascode transistors, which are also discarded from the discussion given here.

Il

Rs, l

Rl

Cl

bl

(a)
VDD
Vbias

Q+

Mcs

Msw+

Msw
(b)

Figure 2.8

VDD
Vbias

Q+

Mcs

Msw+

Msw

(c)

(a) Linearized model of a current source and a switch, (b) PMOS current source
with NMOS switch, and (c) PMOS current source with PMOS switch.

First, we consider the case in Fig. 2.8(b) where a PMOS current source is used
together with an NMOS switch. One of the two transistors in the switch is conducting, and the other is off. It is desirable to have a high output resistance in the
current source transistor. Therefore, it is common to use a transistor length much
higher than the minimum transistor length available in the process. This results in
a small W L for the current source transistor, which in turn yields a relatively
large V SG . The consequence of this is that in order to bias the current source
transistor in the saturation region, which is required to get a high output resistance, the V SD of that transistor must also be relatively large. A simple analysis
using the transistor models given in Sec. 1.5.1 yields that the conducting switch
transistor is in the linear region if the V SD of the current source transistor is
larger than the V T of the switch transistor, which is likely to be the case. In this
case, the mapping to the linearized model is straightforward. R s, l is the on resis59

Modeling of Current-Steering DACs

tance of the switch transistor, R l is the output resistance of the current source
transistor, and C l is the total parasitic capacitance at the drain node of the current
source transistor. C l is mainly a sum of C DB and C GD for the three transistors.
The mapping of the circuit elements in Fig. 2.8(c) to the linearized model is not
as straightforward as for the previous case. A simple analysis using the transistor
models given in Sec. 1.5.1 yields that the switch transistor is in the saturation
region as long as the output voltage, i.e., the drain potential of the switch transistor, is smaller than the threshold voltage of the switch. Since the current source
transistor requires a large V SD , the switch transistor has a large V SB if the
body is tied to V DD . Therefore, it also has a large V T . Hence, it is likely that the
switch transistor is in the saturation region. Actually, it is desirable to operate the
switch transistor in the saturation region since it then acts as a cascode transistor
for the current source. The small signal equivalent of the circuit element in
Fig. 2.8(c) is shown in Fig. 2.9 and is used to calculate the output impedance. C P
is the total parasitic capacitance at the drain node of the current source, mainly a
sum of C GD and C DB of the current source transistor and C GS and C SB of the
switch transistors. In Fig. 2.9, g m, sw and g ds, sw are small signal parameters for
the conducting switch transistor, i.e., either M sw+ or M sw , whereas g ds, cs is
the output conductance for transistor M cs .

gds, cs

CP

vx
vxgm, sw

v
Figure 2.9

gds, sw
output terminal to
which the conducting
switch transistor
is connected

Small-signal equivalent of a PMOS current source with PMOS switch.

The current i in Fig. 2.9 is

i = g m, sw v x + g ds, sw ( v v x ) = v x ( g ds, cs + sC P ) ,

(2.34)

from which it can be derived that

g ds, sw
-v .
v x = -------------------------------------------------------------------------g m, sw + g ds, sw + g ds, cs + sC P
60

(2.35)

Modeling of Finite Output Impedance

Inserting (2.35) into (2.34) yields

g ds, sw ( g ds, cs + sC P )
-v ,
i = -------------------------------------------------------------------------g m, sw + g ds, sw + g ds, cs + sC P

(2.36)

which in turn yields the output impedance

g m, sw + g ds, sw + g ds, cs
sC P
---------------------------------------------------------- + -----------------------------g ds, sw g ds, cs
g ds, sw g ds, cs
v
Z out = -- = ------------------------------------------------------------------------------------------------- .
i
sC P
1 + ------------g ds, cs

(2.37)

The output impedance for the model in Fig. 2.8(a) is

R s, l + R l + sC l R l R s, l
R l ( sC l )
- = ---------------------------------------------------.
Z out = R s, l + ------------------------------R + 1 ( sC )
1 + sC R
l

(2.38)

l l

In order to properly map the circuit element in Fig. 2.8(c) to the linearized model
in Fig. 2.8(a), the two expressions for Z out given by (2.37) and (2.38) must be
equal. Hence,
C P ( g ds, sw g ds, cs )
C l R l R s, l
1 - = --------------R s, l = --------------------= ---------------------------------------------g ds, sw
C P g ds, cs
C l Rl

(2.39)

and
g m, sw + g ds, sw + g ds, cs
- =
R s, l + R l = ---------------------------------------------------------g ds, sw g ds, cs
g m, sw + g ds, sw
1 -.
= ------------------------------------- + --------------g ds, sw
g ds, sw g ds, cs

(2.40)

Combining (2.39) and (2.40) yields

g m, sw + g ds, sw
-.
R l = ------------------------------------g ds, sw g ds, cs

(2.41)

Another identity that can be derived from the equality of (2.37) and (2.38) is
g m, sw + g ds, sw
CP
- = ------------C l R l = C l -------------------------------------,
g ds, sw g ds, cs
g ds, cs

(2.42)

where the first equality is derived using (2.41). Solving for C l in (2.42) yields
61

Modeling of Current-Steering DACs

g ds, sw
-.
C l = C P ------------------------------------g
+g
m, sw

(2.43)

ds, sw

The output wire and load are modeled with a resistor in parallel with a capacitor.
The load capacitance includes the parasitic capacitance at the output nodes of the
switch transistors as well as the parasitic capacitance in the wires, pads, and
printed circuit board (PCB). A more accurate model is obtained if the output
wires are instead modeled with distributed elements or as transmission lines [44].
However, the goal here is to obtain a simple model with few circuit nodes in
order to have short simulation times. Therefore, the lumped element model is
used for the output wires and load. For the same reason, parasitic inductances
have been ignored. A schematic view of the complete model is shown in
Fig. 2.10.

Il1

Il

Rl1
Rs, l1

Cl1

Rs, l

Il+1
Rl

Cl

Rl+1
Rs, l+1

V+

V
RL

Figure 2.10

Cl+1

CL

CL

RL

Schematic view of the DAC model including capacitive parasitics.

We now consider one of the output terminals during one update period, i.e.,
between two consecutive update instants. For simplicity, we consider the time
interval 0 t < T . The output terminal has K current sources connected to it. For
simple notation, we let these current sources be indexed l = 1, 2, , K . The situation is illustrated in Fig. 2.11.
The system in Fig. 2.11 is described by the differential equations

62

Modeling of Finite Output Impedance

I1

Rs, 1

IK

V1
R1

C1

Rs, K

Io, 1

RK

CK

Io, K

RL

Figure 2.11

VK

CL

One output terminal during one update period.

V l(t)
I o, l(t) = I l ---------- C l V l(t) ,
R
t

(2.44)

V l(t) V (t)
I o, l(t) = --------------------------,
R s, l

(2.45)

(t ) ,
I (t) = V
--------RL

(2.46)

and

I (t) =

I o, l(t) C t V (t) .

(2.47)

l=1

Combining (2.44) and (2.45) yields

1
1
1- + --------1 + V (t) -------- V (t) = ----.
I V l(t) ---Cl l
R s, l
R l R s, l
t l

(2.48)

Similarly, combining (2.45), (2.46) and (2.47) yields

1-
V (t) = --
C
t

l=1

1
V l(t)
---------- V (t) ------+
R s, l
RL

1
--------R s, l

(2.49)

l=1

63

Modeling of Current-Steering DACs

We define the voltage vector

V (t) = [ V 1(t), V 2(t), , V K (t), V (t) ] T

(2.50)

and the state vector

X(t) = V (t) V (0) ,

(2.51)

where V (0) contains the initial voltages, i.e., the voltages just before the
switching occurs at time t = 0 . Using (2.48)-(2.51), we derive
V (t) = X(t) = AX(t) + Bu(t) .
t
t

(2.52)

The matrix A is given by

A =

A1 A2
,
A3 a

(2.53)

where
1
1 - -----1
---- R - + ---------R C1
A1 =

1
1
1 - ----- ----
R - + ---------R C2

s, 1

s, 2

(2.54)

11 - ------1

------- + ----------R CK
R
K

s, K

T
1
1
1
A 2 = ------------------, ------------------, , -------------------- ,
R s, 1 C 1 R s, 2 C 2
R s, K C K

(2.55)

1
1
1
A 3 = ------------------, ------------------, , -------------------- ,
R s, 1 C L R s, 2 C L
R s, K C L

(2.56)

and
1
a = ------+
RL

11 -----.
--------R s, l C L

l=1

The vector B is given by

64

(2.57)

Modeling of Finite Output Impedance

T
IK
I1 I2
-, 0
, ------, , ------B = AV (0) + -----C1 C2
CK

(2.58)

and u(t) is a unit step used to apply the initial conditions given by B at time
t = 0 . We define the output vector
Y (t) = V (t) = X(t) + V (0)u(t) .

(2.59)

Equations (2.52)-(2.59) form a state-space representation of a linear system with

input u(t) and output Y (t) [45]. Hence, the nodal voltages in the DAC model are
given as the step response of a linear system on a state-space form. This kind of
system can easily be simulated with, e.g., MATLAB or another numerical computation tool.
The following algorithm is used for simulation of the model.
1. For a given value of the input, x , find the appropriate matrix A representing
one of the output terminals.
2. Use the final voltages from the previous update period as initial values to calculate the vector B . (Reasonable initial voltages are assigned for the first
update period.)
3. Calculate/simulate the vector V (t) , e.g., with a numerical computation tool
like MATLAB.
4. Repeat steps 1 through 3 for the other output terminal.
Some simulation results on a 14-bit binary-weighted DAC are presented here to
illustrate the use of the model. In the simulations presented in [27] and [43], only
the final output value in each update period was considered. However, as will be
clear from the modeling of glitches in Sec. 2.4, only considering the final values
may yield inaccurate results. For accurate results, one must consider that the output from the DAC is not band limited and should be filtered before it is sampled
to avoid aliasing. In the simulations presented here, we sample the DAC output
with a sampling frequency that is 16 times higher than the update frequency of
the DAC in order to reduce the aliasing problem with the help of the inherent sinc
weighting of the spectrum. The parameters used in the simulations are listed in
Table 2.1. The update frequency used is 10 MHz.
An output spectrum from a simulation using a full-scale sinusoidal input is
shown in Fig. 2.12(a). The dominating spurious tone is the third harmonic. The
simulated SFDR is plotted as a function of signal frequency in Fig. 2.12(b). It can
be observed that SFDR decreases approximately 12 dB/dec, which agrees well

65

Modeling of Current-Steering DACs

Parameter

Value

I l , [ A ]

1.22 2 l

R l , [ G ]

1.00 2 l

C l , [ fF ]

0.50 2 l

R s, l , [ ]

Table 2.1

100 , l = 0, , 7
100 2 7 l , l = 8, , 13

RL , [ ]

50

C L , [ pF ]

50

Model parameter values used in the simulations.

with the behavior observed in measurements of current-steering DACs which

typically shows a decrease in the range of 10-20 dB/dec (see, e.g., [38, 46, 47]
and the measurement results presented in Chapter 5).
Low-Complexity Model
The fundamental source of nonlinear behavior in the state-space model is the
connection of a signal dependent network of parasitic components to the DAC
output. In this section, we briefly discuss a model structure with lower computational complexity than the state-space model. A more thorough description of
this low-complexity model is given in [27]. A possible use for a model with low
computational complexity is that it can be implemented on chip at an acceptable
cost and be used for error compensation [48]. An example where the low-complexity model is used for error compensation is given in Sec. 4.3.2.
In its present form, the low-complexity model operates in discrete time and estimates the DAC settling error, i.e., the deviation from the desired output level at
the end of the update period. As discussed in the presentation of the state-space
model, only considering the output at the end of the update period may result in
inaccurate results. Further model development is required in order to take this
into account.
We let y x(n) and y(n) denote the desired (i.e., settled) and actual outputs for a
given input x(n) , respectively. The output sequence y(n) can be expressed as
y(n) = y(n 1) + ( y x(n) y(n 1) ) ( 1 e rel(n) ) ,

66

(2.60)

Modeling of Finite Output Impedance

Output spectrum, f

signal

= 1.1359 MHz

0
PSD [dB/Hz]

20
40
60
80
100
120
0

2
3
Frequency [Hz]

5
6

x 10

(a)
SFDR vs. fsignal
86

SFDR [dB]

84
82
80
78
76
74 5
10

10
Frequency [Hz]

10

(b)
Figure 2.12

(a) Example of an output spectrum from the state-space model and (b) simulated SFDR as a function of the signal frequency.

where y x(n) y(n 1) is the size of the desired step at the output and e rel(n) is
an error factor which we refer to as the relative step error. In the first approach to
establish a low-complexity model, we assume that e rel(n) is a function only of
the present input value x(n) . We use the abbreviated notation
e rel(n) = e rel(x(n)) .

(2.61)

67

Modeling of Current-Steering DACs

This assumption is based on that the matrix A given by (2.53), which in some
sense represents a time constant of the system, is a function only of the present
input x(n) .
We normalize the DAC output such that
y x(n) = x(n) .

(2.62)

The resulting DAC model is

y(n) = y(n 1) + ( x(n) y(n 1) ) ( 1 e rel(x(n)) ) .

(2.63)

A block diagram of a circuit computing (2.63) is given in Fig. 2.13. A solution

proposed in [27] to get a small LUT is to address the LUT only with a few MSBs
of the input. Further, in order to keep the size of both the LUT and the multiplier
small, e rel(x(n)) should be represented with as few bits as possible.
x(n)

LUT

1erel(n)

y(n)

z1
Figure 2.13

Block diagram of the low-complexity model in its simplest form.

By assuming that e rel is a function of only the present input, the influence of the
initial values of the internal node voltages (i.e., V 1, , V K ) of the circuit in
Fig. 2.11 is neglected. These initial values are roughly determined by the previous input x(n 1) . It was shown in [27] that the agreement between the lowcomplexity model and the state-space model is improved if it is assumed that e rel
is also a function of the previous input, i.e.,
y(n) = y(n 1) + ( x(n) y(n 1) ) ( 1 e rel(x(n), x(n 1)) ) .

(2.64)

A block diagram of a circuit computing (2.64) is shown in Fig. 2.14.

2.4 Modeling of Glitches due to Rise/Fall Asymmetry

Glitches are present in the DAC output, e.g., due to skew between the individual
bits in the control word [10, 11, 49], charge injection from switches [50], and
asymmetry in the settling behavior when switching on and off a current source
[51]. Glitches are dependent on the input sequence. This signal dependency
results in nonlinear distortion that degrades the overall circuit performance [10].

68

Modeling of Glitches due to Rise/Fall Asymmetry

x(n)
z1

LUT

1erel(n)

y(n)

z1
Figure 2.14

Block diagram of a modified version of the low-complexity model.

The glitch properties of a DAC are often specified by the area of the glitch at the
worst-case code transition [3, 51, 52], which is often the middle code transition.
However, specifying the worst-case glitch area does not provide enough information on how the glitches affect the DAC performance, e.g., in the frequency
domain which is important in many communication applications [10]. Therefore,
behavioral-level models that describe how glitches caused by different types of
error sources affect the DAC performance are important. However, such behavioral-level models are rarely presented in the literature. In [49], a statistical analysis of glitches caused by static timing mismatch between individual bits in the
DAC control word is presented. Different settling behavior when switching on
and off current sources, i.e., asymmetry in the rise/fall behavior, also causes
glitches. This type of glitch was modeled in [51], where the current wave forms
when switching on and off current sources were described by damped sinusoids
having different amplitudes and frequencies depending on the type of switching
(on or off). In this section, the glitch model presented in [51] is generalized in the
sense that the current wave forms when switching on and off current sources are
described by arbitrary functions. This generalization enables powerful analyses,
both in the time domain and in the frequency domain. The work presented in this
section is original work of the author and appears in [53].
First, an analysis of a 1-bit DAC is presented in order to illustrate the basic concept. The analysis of the 1-bit DAC is followed by an analysis of a general multibit DAC. Further, the developed model is analyzed in the frequency domain and a
simple method for estimating the resulting frequency-domain behavior is developed. The method can be utilized by DAC designers to derive requirements on
the current source settling behavior to fulfill a given frequency-domain specification through behavioral-level simulations. This approach can potentially be used
to relax circuit requirements compared with requirements based on a worst-case
analysis.

69

Modeling of Current-Steering DACs

Prerequisites for the modeling are presented in Sec. 2.4.1. The actual modeling is
presented in Sec. 2.4.2. Some examples on utilization of the developed model
and methods are given in Sec. 2.4.3. A short discussion on how the use of a differential output is modeled is given in Sec. 2.4.4.
2.4.1 Preliminaries
Due to different nonideal properties of DAC components, it is in practice not possible to implement a block that exactly performs the PAM operation given by
(1.3). As discussed in Sec. 1.2.3, nonlinearity errors are usually of special importance since they are more difficult to compensate for than linear errors. We let
y nom(t) denote the nominal DAC output obtained from the PAM operation

y nom(t) = K nom

x(n) p(t nT ) ,

(2.65)

n =

where K nom is the nominal DAC gain and p(t) is the nominal pulse. Further, let
y(t) denote the actual output. The error in the DAC output is the difference
between y(t) and y nom(t) . In the modeling presented in this section, we do only
consider the contribution due to rise/fall asymmetry in the current sources. Following the terminology used in [51], we denote the resulting error a glitch.
Hence, for this particular scenario, we define the glitch signal, y g(t) , as
y g(t) = y(t) y nom(t) .

(2.66)

If other error sources are included, e.g., mismatch in current sources or finite output impedance, (2.65) may be used to define a general error signal rather than a
glitch signal.
In order for the definition in (2.65) to make sense, we also have to provide definitions for the nominal gain and the nominal pulse. Choosing the proper nominal
pulse shape is not trivial. If the initial intention is to design a DAC with a certain
pulse shape (e.g., a square pulse), an intuitive approach is to use that pulse as the
nominal pulse. In [51], a pulse shape expressed with a tanh function was chosen
as the nominal pulse. In this work, we do not use a specific pulse shape. Instead,
the following approach is used. A set F of reconstruction filters is formed, containing all filters that can be implemented at an acceptable cost. What an acceptable cost is is up to the circuit designer to decide and is not defined here, but can,
e.g., be defined in terms of filter order, etc. Further, a set P of allowed pulse wave
forms is formed. The set P contains all pulses that in combination with a reconstruction filter in F performs signal reconstruction that only deviates from ideal
reconstruction within acceptable bounds. What these acceptable bounds are is

70

Modeling of Glitches due to Rise/Fall Asymmetry

also a choice for the circuit designer and is not defined here, but can, e.g., be
expressed in terms of rejection of spectral images and maximum attenuation
within the Nyquist band. In order to decide which element in P to choose as
p(t) , we define the signal energy, E(z(t), ) , of the continuous-time signal z(t)
on the time interval = [ t 0, t 1 ] as
E(z(t), ) =

z2(t) dt .

(2.67)

Using this definition of the signal energy, the SNDR due to glitches is given by
E(y nom(t), )
-,
SNDR = -----------------------------E(y g(t), )

(2.68)

provided that E(y nom(t), ) and E(y g(t), ) are both finite, which is the case, e.g.,
if the signals only adopt finite values and have finite extension in time. If the
interval is infinite, the energy may also be infinite and the SNDR has to be
defined in terms of power instead of energy as in Sec. 1.3.2. For cases where the
SNDR is a relevant metric of the DAC performance, the glitch energy E(y g(t), )
is a relevant metric for the glitch size. The term glitch energy is sometimes used
for the area of the glitch, even if this is not strictly correct [3]. Here, the term
glitch energy is used for the signal energy of the glitch signal.
We restrict the problem to only include contributions to the nonlinear distortion
in the DAC output. This is accomplished by choosing the nominal gain, K nom ,
and the nominal pulse, p(t) , from an allowed set of gain factors (e.g., allowed
ranges of unit currents or reference voltages, depending on the type of DAC that
is used) and the set P , respectively, such that the average glitch energy over all
time intervals of the type [ nT , ( n + 1 )T ) is minimized. This can be seen as a
least-squares adaptation of the nominal DAC transfer characteristics.
2.4.2 Model Derivation
In this section, we develop the model of glitches caused by rise/fall asymmetry in
the current sources. First, a 1-bit DAC is analyzed to illustrate the concept. Then,
an analysis of a general multi-bit DAC, which involves a more complex derivation than the 1-bit DAC, is made in a similar way. Further, a simple method for
accurately estimating the behavior of the modeled glitches in the frequency
domain is developed. For the analyses presented in this section, we let the set P
of allowed nominal pulse shapes be the set of all pulse shapes, i.e., no restrictions
are set on P . The main reason for doing so is to be able to use the nominal pulse
shape that corresponds to the global minimum of the glitch energy, which in turn
enables an analytical derivation of the nominal pulse shape.

71

Modeling of Current-Steering DACs

Analysis of a 1-bit DAC

First, the behavior of a 1-bit DAC is analyzed. Assume that, for the currentsource-and-switch (CS) cell in Fig. 2.15(a), the switch is initially connected such
that the whole current delivered from the current source is directed towards the
positive output terminal. In that situation,
I A = wI unit

(2.69)

and
IB = 0 ,

(2.70)

where wI unit is the settled output current from the current source. At time
t = 0 , a switching is initiated, and at time t = T , the system has settled such
that
IA = 0

(2.71)

and
I B = wI unit .

(2.72)

For the time interval ( 0, T ) , we allow the two currents I A and I B to have arbitrary waveforms with the only boundary condition being that the currents have
reached their final values before t = T . For example, the current waveforms
may look like the ones in Fig. 2.15(b), in which case I A = I off and I B = I on .
In general, the total output current from the current source is not constant during
the switching, as indicated in Fig. 2.15(b). Further, we assume that the CS cell is
symmetric in the sense that if the current is instead switched from the negative to
the positive output terminal, then I A = I on and I B = I off . Also, if no switching
takes place, the currents are assumed to remain constant during the whole interval. The system analyzed is assumed to be time invariant and memoryless, i.e.,
for every n such that a switching is initiated at time nT , the current waveforms
are the same during the interval ( nT , ( n + 1 )T ) regardless of the history of the
control signal and the value of n .
We continue with the analysis of the single-ended output at the positive output
terminal, letting I out(t) denote the output current at that terminal. The result for
the negative output terminal is obtained by simply replacing b(n) with 1 b(n) .
We define two functions of time, s on(t) and s off(t) , with the properties

72

Modeling of Glitches due to Rise/Fall Asymmetry

CS cell
b
IA

IB

I+

I
load
(a)
Ion
Ioff
Ion + Ioff

wI

Current

unit

0
T

0
t
(b)
Figure 2.15

(a) 1-bit current-steering DAC and (b) output current waveforms during switching.

s on(t) = s off(t) = 0 for t 0 ,

1 for t T

(2.73)

I on(t) = wI unit s on(t) for 0 < t < T

(2.74)

and
I off(t) = wI unit ( 1 s off(t) ) for 0 < t < T .

(2.75)

If s on(t) and s off(t) are equal, the DAC performs a PAM operation with the pulse
shape

73

Modeling of Current-Steering DACs

p(t) = s on(t) s on(t T ) = s off(t) s off(t T ) .

(2.76)

Hence, the DAC is linear and no glitches occur. In this work, s on(t) and s off(t)
are assumed to be unequal. In [51], the current waveforms during switching on
and off a current source were modeled with damped sinusoids with different
amplitudes and frequencies depending on the type of switching (on or off). The
model developed in [51] was compared with transistor-level models and a good
agreement was observed. The use of unequal s on(t) and s off(t) as a source of
glitches is merely a generalization of using damped sinusoids with different
amplitudes and frequencies and is motivated with the good agreement with transistor-level models observed in [51].
We define a function s(t) from which the nominal pulse shape is to be derived.
s(t) is equal to s on(t) and s off(t) for t ( 0, T ) and defines the nominal current
waveforms according to
I on, nom(t) = wI unit s(t)

(2.77)

and
I off, nom(t) = wI unit ( 1 s(t) ) .

(2.78)

Choosing the proper nominal pulse shape is equivalent to choosing the proper
s(t) . For a 1-bit DAC, the determination of s(t) is straightforward, since half of
the switching events involves switching in one direction, and the other half
switching in the opposite directions. The average glitch energy is given by
T

P
E g = -----s ( I on(t) I on, nom(t) ) 2 + ( I off(t) I off, nom(t) ) 2 dt =
2

2
P s w 2 I unit
- [ ( s on(t) s(t) ) 2 + ( s off(t) s(t) ) 2 ] dt =
= ----------------------2

0
T

2
P s w 2 I unit
----------------------- f (t) dt ,
=
2

(2.79)

Where P s is the probability for a switching event to occur. Since the integrand
f (t) 0 for every t , E g is minimized by minimizing f (t) for every t . It is
readily shown that this is accomplished by choosing

74

Modeling of Glitches due to Rise/Fall Asymmetry

s on(t) + s off(t)
-.
s(t) = --------------------------------2

(2.80)

The resulting glitches are

s on(t) s off(t)
I on, g(t) = I on(t) I on, nom(t) = wI unit --------------------------------
2

(2.81)

and
s on(t) s off(t)
I off, g(t) = I off(t) I off, nom(t) = wI unit --------------------------------,
2

(2.82)

respectively. Hence, every time a switching event occurs, the same glitch
I g(t) = I on, g(t) = I off, g(t) is present at the DAC output, regardless of the type
of switching (on or off).
The nominal DAC output for an input sequence b(n) is given by

I out, nom(t) = wI unit

b(n) p(t nT ) ,

(2.83)

n =

where the nominal pulse p(t) is given by

p(t) = s(t) s(t T ) .

(2.84)

The actual output, I out(t) , for an arbitrary input can be expressed as

I out(t) = I out, nom(t) + I out, g(t)

(2.85)

where

I out, g(t) = wI unit

( b(n) b(n 1) ) p g(t nT )

(2.86)

n =

is the overall glitch current and

s on(t) s off(t)
p g(t) = --------------------------------.
2

(2.87)

The expression ( b(n) b(n 1) ) appearing in (2.86) is used to detect whether

or not a switching event occurs at t = nT .

75

Modeling of Current-Steering DACs

Analysis of a Multi-Bit DAC

We now extend the analysis to an N -bit DAC with arbitrary encoding of the control word. The topology analyzed is shown in Fig. 2.16. It consists of a number of
CS cells. For the present analysis, we assume that output currents for each individual CS cell are independent on the states of the other CS cells. This is of
course an approximation, since in an actual implementation, on-chip cross talk
causes the currents to be dependent on switching actions taking place in surrounding cells.
CSl1
IA, l1

CSl
IB, l1

IA, l

CSl+1
IB, l

I+

IA, l+1

IB, l+1

I
load

Figure 2.16

N -bit DAC topology with arbitrary encoding of the control word.

Each CS cell, CS l , has an associated weight, w l , and an associated control bit,

b l . During an internal switching event initiated at t = 0 in CS l , either
I A, l(t) = w l I unit ( 1 s off(t) )

(2.88)

and
I B, l(t) = w l I unit s on(t) ,

(2.89)

I A, l(t) = w l I unit s on(t)

(2.90)

or

and
I B, l(t) = w l I unit ( 1 s off(t) ) ,

(2.91)

depending on the type of switching. The functions s on(t) and s off(t) have the
properties given in (2.73). Further, we assume that all CS cells have identical
s on(t) and s off(t) .

76

Modeling of Glitches due to Rise/Fall Asymmetry

As in the analysis of the 1-bit DAC, we analyze the behavior of the positive output terminal, letting I out(t) denote the output current at that terminal. For an
input sequence x(n) , we can express the corresponding output current in the
interval ( n 1 )T t nT as
I out(t) =

= I unit x(n 1) +
w l s on(t nT )
w l s off(t nT ) ,

lL
lL

on

(2.92)

off

where
L on = { l : b l(n) b l(n 1) = 1 }

(2.93)

and
L off = { l : b l(n) b l(n 1) = 1 } .

(2.94)

Further, the nominal output current for the same interval is

I out, nom(t) = I unit x(n 1) +

wl
w l s(t nT ) ,

l L

lL

on

(2.95)

off

where s(t) is a function that describes the nominal switching behavior of the
DAC. The choice of s(t) is not as straightforward as for the 1-bit DAC and
involves assumptions on the statistics of the input sequence.
To simplify the notation, we consider the case n = 0 and, hence, the time interval ( 0, T ) . The glitch current is
I out, g(t) = I out(t) I out, nom(t) =

= I unit
w l ( s on(t) s(t) )
w l ( s off(t) s(t) ) .
l L

lL

on

(2.96)

off

As for the 1-bit DAC, s(t) should be chosen to minimize the average glitch
energy per switching event. Let a denote the event characterized by
x( 1) = x a1 and x(0) = x 0a . Further, let A denote the (finite) set of all possible
a . To each a , there are associated sets L on, a and L off, a , as defined in (2.93) and
(2.94). The average glitch energy is given by

77

Modeling of Current-Steering DACs

T

Eg =

2
a
P(a) ( I out

, g (t) ) dt ,
aA

(2.97)

where
a
I out
, g (t) =

= I unit
l L

w l ( s on(t) s(t) )

on, a

lL

off, a

w l ( s off(t) s(t) )

(2.98)

and P(a) is the probability for the event a to occur. If a is such that
a
x( 1) = x(0) , then I out
, g (t) = 0 , so events of this type give zero contributions
to E g , regardless of the choice of s(t) . We combine the events for which
x( 1) x(0) into pairs of events ( a, b ) for which
x 0a = x b1

(2.99)

and
x a1 = x 0b .

(2.100)

The pairs ( a, b ) and ( b, a ) are considered identical, and the set of all pairs is
denoted AB . We can now rewrite (2.97) as
T

Eg =

2
2
a
b
[ P(a) ( I out

, g (t) ) + P(b) ( I out (t) ) ] dt

( a, b ) AB

E g( a, b ) .

( a, b ) AB

(2.101)

In order to derive the proper s(t) , we have to make an assumption on the statistical properties of the input sequence. The assumption is that
P(a) = P(b) for every ( a, b ) AB ,

(2.102)

i.e., the transition from x a1 to x 0a occurs on the average as often as the reverse
a and n a to be the total number of unit
transition. We define the numbers n on
off
current sources that are switched on and off during the event a , respectively. The
a and n a are given by
numbers n on
off

78

Modeling of Glitches due to Rise/Fall Asymmetry

a =
n on

lL

wl

(2.103)

wl ,

(2.104)

on, a

and
a =
n off

l L off, a

respectively. We have that

b = na
n on
off

(2.105)

and
b = na
n off
on

(2.106)

for any given pair ( a, b ) AB . A given term, E g( a, b ) , in (2.101) is minimized

by minimizing
E g( a, b )
=
e g( a, b ) = --------------------2 P(a)
I unit
T

a (t) ) 2 + ( n a (t) n a (t) ) 2 ] dt

off
off on
on off
[ ( nona on(t) noff

0
T

f (t) dt ,

(2.107)

where
on(t) = s on(t) s(t)

(2.108)

and
off(t) = s off(t) s(t) .

(2.109)

Since the integrand f (t) 0 for every t , e g( a, b ) is minimized by minimizing f (t)

for every t . This is accomplished by choosing
s on(t) + s off(t)
-.
s(t) = --------------------------------2

(2.110)

79

Modeling of Current-Steering DACs

Since this choice of s(t) minimizes each term in (2.101) separately, it also minimizes E g . Hence, assuming that P(a) = P(b) for every ( a, b ) AB results in
the same s(t) as for the 1-bit DAC and, therefore, the same nominal pulse p(t) .
Inserting (2.110) into (2.96) yields the glitch current
I out, g(t) =

lL L
on

s on(t) s off(t)
w l -------------------------------- I unit
2
off

= I unit p g(t)n tot ,

(2.111)

where
s on(t) s off(t)
p g(t) = --------------------------------
2

(2.112)

and
n tot =

lL L
on

wl .

(2.113)

off

The number n tot is the total number of unit sources that are subject to a switching operation. For an input sequence x(n) , the nominal and actual DAC outputs
can be expressed as

I out, nom(t) = I unit

x(n) p(t nT )

(2.114)

n =

and
I out(t) = I out, nom(t) + I out, g(t) =

= I unit

x(n) p(t nT ) +

n =

n =

g(n) p g(t nT ) ,

(2.115)

respectively, where
g(n) =

80

l bl(n) bl(n 1) wl

(2.116)

Modeling of Glitches due to Rise/Fall Asymmetry

is the total number of switched unit current sources during the transition from
x(n 1) to x(n) at the DAC input and is dependent on the encoding strategy
(e.g., degree of segmentation). In order to have small glitches, it is desirable to
have small values of g(n) . Hence, g(n) can be used as a high-level performance
metric to compare different encoding strategies, just as the metric S(x) defined in
Sec. 2.2.2 as the total number of switched unit current sources in the transition
from x 1 to x . We introduce the notation
G(x(n 1), x(n)) = g(n) .

(2.117)

G(x(n 1), x(n)) is related to S(x) according to

S ( x ) = G ( x , x 1) .

(2.118)

G(x(n 1), x(n)) and S(x) are used in Chapter 3 for high-level comparison of
different DAC architectures.
Analysis in the Frequency Domain
So far, the modeling has been performed in the time domain. An analysis on how
the modeled glitches affect the frequency-domain properties of the DAC is presented in this section. For a simplified notation, we normalize the output with
respect to the unit current to obtain the output

y(t) =

x(n) p(t nT ) + g(n) p g(t nT ) .

(2.119)

n =

The spectrum (Fourier transform) of the output is

Y () = X (e jT )P() + G(e jT )P g() ,

(2.120)

where P() and P g() are the Fourier transforms of p(t) and p g(t) , respectively, and

X (e jT ) =

x(n)e jnT

(2.121)

g(n)e jnT

(2.122)

n =

and

G(e jT ) =

n =

81

Modeling of Current-Steering DACs

are the (discrete-time) Fourier transforms of x(n) and g(n) , respectively. The first
term in (2.120), X (e jT )P() , is the spectrum of the nominal output and the second term, G(e jT )P g() , is the spectrum of the glitch signal.
From this point, we restrict the analysis to the Nyquist band ( T , T ) .
In accordance with the commonly used concept of input-referred noise, we introduce the concept of input-referred glitches. The input referred glitch spectrum is
defined as
P g()
- G(e jT ) .
G ir(e jT ) = ------------P()

(2.123)

It is readily verified that within the Nyquist band,

Y () = P() ( X (e jT ) + G ir(e jT ) ) ,

(2.124)

i.e., the input-referred glitch is a signal in the discrete-time input domain that
applied to the input of the nominal PAM block results in the same spectrum as the
glitch signal within the Nyquist band.
In order to make the concept of input-referred glitches practically useful, the
analysis is continued with a few approximations. If p(t) is close to a square pulse
then
-) .
P() T sinc(----------2 f s

(2.125)

If the DAC is oversampled, i.e., the signal bandwidth f 0 is significantly smaller

than half the sampling frequency, then
P() P(0) for ( 2 f 0, 2 f 0 ) ,

(2.126)

where ( 2 f 0, 2 f 0 ) is the signal band. We assume that a similar approximation is valid for P g() , i.e.,
P g() P g(0) for ( 2 f 0, 2 f 0 ) .

(2.127)

This is a valid approximation, e.g., if p g(t) is a short square or triangular pulse or

has a shape that resembles one of these. Provided that the approximations (2.126)
and (2.127) are valid, G ir(e jT ) can be approximated with
P g(0)
- G(e jT ) .
G ir(e jT ) --------------P(0)

82

(2.128)

Modeling of Glitches due to Rise/Fall Asymmetry

For a finite-length input sequence, we can make an approximate analysis of the

spectral distribution of the glitch energy by considering the squared absolute
value of the discrete Fourier transform (DFT) of the input-referred glitch
sequence, which we define as
P g(0)
- g(n)
g ir(n) = --------------P(0)

(2.129)

and compare this with the squared absolute value of the DFT of the input
sequence in order to obtain SNR values for different frequency bands, etc. Note
that g ir(n) is not the inverse transform of G ir(e jT ) but only an approximation.
A more accurate approach is to form a sampled version of the output
z(m) = y(mT 1) ,

(2.130)

where T 1 T in order to reduce aliasing effects [3], and analyze the DFT of
z(m) . This approach has a higher computational cost than the previous, since it
requires T T 1 more samples. Both methods are used and compared in
Sec. 2.4.3.
Comments to the Modeling
In this section, we provide a summary of the modeling and give a few comments
regarding its use. The purpose of the summary is to simplify the understanding of
the results before proceeding with the examples presented in the following section.
The switching on and off of current sources was characterized by two functions,
s on(t) and s off(t) . The glitches modeled in this work occur due to that s on(t) and
s off(t) are assumed not to be equal. This assumption is motivated with the work
presented in [51], where it was shown that the switching on and off of current
sources could be accurately modeled with damped sinusoids having different
amplitudes and frequencies depending on the type of switching. The modeling
presented here is a generalization of the modeling presented in [51] that enables a
powerful analysis both in the time domain and the frequency domain.
The nominal DAC output was characterized by the nominal switching function
s(t) , which was chosen as the average of s on(t) and s off(t) in order to minimize
the resulting glitch energy. The resulting nominal pulse is p(t) = s(t) s(t T ) .
Choosing a nominal pulse that does not minimize the glitch energy results in a
glitch current on the form

83

Modeling of Current-Steering DACs

I out, g(t) =

= K

n =

x(n) p g, linear(t nT ) +

n =

g(n) p g(t nT )

(2.131)

where the first part is a linear function of the input sequence that does not contribute with any nonlinear distortion and can be compensated for using a linear
filter.
An important piece of information that can be extracted from the model is that
the magnitude and the area of the glitch associated with the transition from
x(n 1) to x(n) is proportional to the total number of switched unit current
sources g(n) . This has been stated previously by others (see, e.g., [50, 52]), but
only motivated with intuitive argumentation.
In many cases, the glitch specification of a DAC is given in terms of the worstcase glitch area [3, 51, 52]. Worst-case analyses have a tendency of resulting in
unnecessarily hard circuit requirements. Applying the simple frequency-domain
analysis on signals that are typical for a given application allows the designer to
instead use behavioral-level simulations in discrete time to obtain requirements
on P g(0) P(0) . These requirements can be used as design targets on lower
abstraction levels in the design of current sources, switches, and switch drivers.
Note that P(0) can be calculated with

P(0) =

p(t) dt

(2.132)

and similarly for P g(0)

P g(0) =

pg(t) dt .

(2.133)

In the derivation for the multi-bit case, it is stated that if the input is constant during two consecutive samples, no switching and, hence, no glitches occur. This
assumes a static mapping between the digital input and the control word. In a
DAC utilizing dynamic element matching (DEM), which is discussed in Sec. 4.1,
redundancy in the control word is exploited by random selection of different representations of the same input value in order to reduce nonlinear distortion arising from current source mismatch. In a DEM DAC, switching can occur even if

84

Modeling of Glitches due to Rise/Fall Asymmetry

the input is constant. Even if the properties of a DEM DAC do not conform with
the assumptions used in the derivation, the results given in (2.114)-(2.116) are
valid also for a DEM DAC.
The rise/fall asymmetry is not the only existing source of glitches. Due to mismatch in parasitic load capacitances and driving capabilities between different
signal paths in, e.g., the clock distribution network of the digital part, there will
be a static timing mismatch between different bits in the control word which is
another source of glitches. This type of error has a stochastic component, i.e., it
varies from chip to chip, and is strongly layout dependent. A statistical analysis
of timing errors caused by mismatch in DACs is given in [49]. Glitches may also
be caused by cross talk from the digital parts of the DAC. These glitches are also
strongly layout dependent and have to be addressed at the layout level. Note that
properties such as the signal dependency for glitches caused by other sources
might differ considerably from the corresponding properties of the derived
model. In order to obtain an accurate general glitch model, it is of course required
that models of all relevant glitch sources are combined into one model. This is,
however, beyond the scope of the present work.
2.4.3 Examples
A few examples on application of the developed model are given in this section.
An analytical examination of the properties of a fully thermometer-coded DAC is
presented, followed by simulation examples on one binary-weighted and one
thermometer-coded DAC.
Analysis of the Thermometer-Coded DAC
In this section, we analyze the behavior of a fully thermometer-coded DAC with
respect to glitches caused by rise/fall asymmetry using the developed model and
methods. In the following, we neglect the fact that the input is quantized to simplify the analysis. For a fully thermometer-coded DAC, the number of switched
unit current sources g(n) is given by
g(n) = x(n) x(n 1) .

(2.134)

For a sinusoidal input,

x(n) = x dc + x a cos(nT ) ,

(2.135)

we make the first-order approximation

x(n 1) x(n) + ( 1 )x a cos(nT ) = x(n) + x a T sin(nT ) ,
n

(2.136)

85

Modeling of Current-Steering DACs

resulting in
g(n) x a T sin(nT ) .

(2.137)

A Fourier series expansion of (2.137) yields

2x a T 4x a T
- + ----------------g(n) ---------------

1 cos(2knT ) .
----------------2
4k 1

(2.138)

k=1

Hence, even-order distortion appears in the output. The spurious tone with largest
amplitude is the second harmonic (corresponding to the term with k = 1 in
(2.138)). The SFDR is in linear scale approximately given by
x a2
3 P(0) 2
SFDR lin = -----------------------------------------= ----------------------------
2
4T
P g(0)
P g(0) 4x a T
----------------------------- P(0) 3

(2.139)

and in logarithmic scale,

3 P(0) ) 20log () .
SFDR log = 20log 10(----------------------10
4T P g(0)

(2.140)

Hence, the SFDR decreases 20 dB/dec with increasing signal frequency. Since
P(0) is roughly proportional to T (see, e.g., (2.125)), the factor P(0) T that
appears in (2.139) and (2.140) is approximately constant. Therefore, T has little
or no influence on the SFDR, even though it may seem from (2.139) and (2.140)
that T has a large influence on the SFDR.
Simulation Examples
Some examples of simulations performed in MATLAB, intended to illustrate the
application of the developed model, are presented in this section. The functions
s on(t) and s off(t) used in the simulations are plotted together with the resulting
s(t) in Fig. 2.17(a). In the transition region, s on(t) and s off(t) are described by
one period of a sine wave superpositioned onto a straight line. The resulting
pulses p(t) and p g(t) are plotted in Fig. 2.17(b).
Two different 8-bit DACs are considered, one binary-weighted DAC and one
fully thermometer-coded DAC. A sinusoidal input sequence
28 1
x(n) = -------------- ( 1 + sin(2 f N n) )
2

86

(2.141)

Modeling of Glitches due to Rise/Fall Asymmetry

s (t)
on
soff(t)
s(t)
1

0
T

0
t
(a)

p(t)
p (t)
g
I

unit

0
T

0
t
(b)
Figure 2.17

Waveforms used in the simulations. The functions s on(t) , s off(t) , and s(t) are
plotted in (a), whereas the resulting pulses p(t) and p g(t) are plotted in (b).

is used, where f N = f signal f s is the normalized signal frequency. The output

waveforms for the binary-weighted and the thermometer-coded DACs are plotted
in Fig. 2.18(a) and (b), respectively, for f N 0.078 . Large deviations from the
nominal output, i.e., glitches, are present in the output from the binary-weighted
DAC. The glitches for the thermometer-coded DAC are considerably smaller.
Hence, using a thermometer-coded architecture efficiently limits the impact of
rise/fall asymmetry in the current sources. The glitch currents for the binaryweighted and thermometer-coded DACs are plotted in Fig. 2.19(a) and (b),
respectively.
In order to estimate frequency-domain behavior, we use the sequence

87

Modeling of Current-Steering DACs

Binary-weighted 8-bit DAC

actual output
nominal output

Iout/Iunit

300
200
100
0
10

12

14

16

18

20

t/T
(a)
Thermometer-coded 8-bit DAC
actual output
nominal output

Iout/Iunit

300
200
100
0
10

12

14

16

18

20

t/T
(b)
Figure 2.18

Transient responses for 8-bit DACs. The output from a binary-weighted DAC is
plotted in (a) and the output from a thermometer-coded DAC is plotted in (b).

x g(n) = x(n) + g ir(n) ,

(2.142)

where g ir(n) is defined in (2.129). For the waveforms used in the simulations,
P g(0)
--------------- 0.030 .
P(0)

88

(2.143)

Modeling of Glitches due to Rise/Fall Asymmetry

Binary-weighted 8-bit DAC

250

Iout, g/Iunit

200
150
100
50
0
10

12

14

16

18

20

t/T
(a)
Thermometer-coded 8-bit DAC
250

Iout, g/Iunit

200
150
100
50
0
10

12

14

16

18

20

t/T
(b)
Figure 2.19

Glitch currents for 8-bit DACs. The glitches for a binary-weighted DAC is plotted in (a) and the glitches for a thermometer-coded DAC is plotted in (b)

The magnitude of the DFT of x g(n) for the binary-weighted DAC is plotted in dB
scale in Fig. 2.20(a). The corresponding plot for the thermometer-coded DAC is
shown in Fig. 2.20(b). The signal spectra shown in Fig. 2.20 have been normalized with respect to the power of the fundamental tone.
Simulations were also performed using the more accurate method utilizing
z(m) = y(mT 1) with T 1 = T 16 . The resulting spectra are almost identical to
those plotted in Fig. 2.20. This indicates that the simple method of calculating the

89

Modeling of Current-Steering DACs

Binary-weighted 8-bit DAC

0

PSD [dB]

20
40
60
80
0

0.1

0.2
0.3
0.4
Normalized frequency (f/fs)

0.5

(a)
Thermometer-coded 8-bit DAC
0

PSD [dB]

20
40
60
80
0

0.1

0.2
0.3
0.4
Normalized frequency (f/fs)

0.5

(b)
Figure 2.20

Magnitude of the DFT of x g(n) for (a) a binary-weighted 8-bit DAC and (b) a
thermometer-coded 8-bit DAC.

DFT of x g(n) gives a good estimation of the amplitudes of the spurious tones, at
least for the waveforms used in these examples, even though the corresponding
phases might be incorrectly estimated.
The SFDR values for the thermometer-coded DAC estimated from the simulations are plotted as a function of f N in Fig. 2.21, together with the theoretical
values given by (2.140). Good agreement is observed between the different methods.

90

Modeling of Glitches due to Rise/Fall Asymmetry

SFDR due to glitches, 8-bit thermometer-coded DAC

60

analytical
using z(m)
using x (n)

SFDR [dB]

55

50
45
40
35
2

10
Figure 2.21

10
Normalized frequency (f/fs)

SFDR as a function of f N for the thermometer-coded 8-bit DAC estimated with

different methods.

In [50], it is argued that glitches do not contribute to nonlinear distortion in a

fully thermometer-coded DAC. The underlying assumption implied in the discussion given in [50] is that the rise/fall behavior of the current sources is symmetric.
In practice, it is not possible to design a current source with perfectly symmetric
rise/fall behavior which, according to the analysis presented in this work, results
in nonlinear distortion. In order to reduce the nonlinearities, the current sources
should be designed to have as symmetric rise/fall behavior as possible, which is
equivalent to keeping the ratio P g(0) P(0) as small as possible.
2.4.4 Glitches in the Differential Output
Since the number of switched unit current sources, g(n) , is the same for both the
positive and the negative output, it is easily realized that the glitches modeled in
this work are identical in the positive and negative outputs. Hence, these glitches
constitute a common-mode error that cancels perfectly in the differential output if
the two outputs are perfectly matched. However, in practice there is always a
small mismatch between the two outputs, e.g., due to mismatch between the load
resistors. Moreover, intermodulation in subsequent stages (e.g., filters or buffers)
between the fundamental tone and the spurious tones in the two single-ended outputs may cause errors that do not cancel in the differential output. Therefore, it is
desirable to keep the glitch errors small in the single-ended outputs, even if they
cancel for perfectly matched differential signal paths.
The differential output is given by

91

Modeling of Current-Steering DACs

I out, diff(t) = 2I unit

n =

2N 1
x(n) p(t nT ) 2I unit ---------------- ,
2

(2.144)

where
p(t) = s(t) s(t T )

(2.145)

and
s on(t) + s off(t)
-.
s(t) = --------------------------------2

(2.146)

Hence, the differential output may be described with a PAM operation using the
same pulse as for the nominal output in the single-ended case.

92

3 Digital Encoding in
Current-Steering DACs
From the modeling of matching errors and glitches presented in Sec. 2.2 and
Sec. 2.4, respectively, we realize that the performance of a current-steering DAC
is dependent on the sizes of the weights and the mapping of the digital input to
the control word. In this chapter, we give an overview of current-steering DAC
architectures that utilize different sets of weights and ways of mapping the digital
input to the control word. Some of these architectures are well established and
some have been developed in this work.
The well-established binary-weighted and segmented DAC architectures are
overviewed in Sec. 3.1 and Sec. 3.2, respectively. The decomposed and partially
decomposed DAC architectures, that have been developed in this work, are presented in Sec. 3.3 and Sec. 3.4, respectively. Miscellaneous code types are briefly
overviewed in Sec. 3.5. The architectures discussed in Sec. 3.1-Sec. 3.4 are compared in Sec. 3.6 using some of the behavioral-level models from Chapter 2.
In Chapter 2, we introduced the number of switched unit current sources in the
transition from x 1 to x and in a general transition from x(n 1) to x(n) as
high-level metrics for comparing different architectures in terms of static linearity and glitch properties. These metrics are frequently used in this chapter to
investigate the properties of the different architectures. In order to make fair comparisons, one must take into account the hardware costs associated with the
codes. It is difficult to define a general measure of hardware cost. Here, we use
the number of bits in the control word as a rough measure of hardware cost. The
number of bits in the control word is equal to the required number of switches
and control wires and, therefore, it is related to the circuit area. However, the circuit area is usually dominated by the area required for the current sources. Fur93

Digital Encoding in Current-Steering DACs

ther, it is not a good design strategy to use the same size for the transistors in all
switches in the DAC. The transistors conducting currents with large weights
should be made wider than transistors conducting currents with small weights.
Therefore, the number of bits in the control word may be inaccurate as a measure
of hardware cost, but it is nevertheless used here due to the lack of a better metric.

3.1 Binary-Weighted DACs

In a binary-weighted DAC, the control word is given in binary-offset representation and the weights are
wl = 2 l .

(3.1)

In the digital blocks, it is common to represent the data in a closely related code
such as twos-complement code. Therefore, no or very simple encoding is
required to form the control word in a binary-weighted DAC, resulting in a low
hardware complexity. On the other hand, the performance of a binary-weighted
DAC is usually poor due to the large number of switched unit current sources.
The traditional example is to consider the middle code transition, from the code
where b N 1 = 0 and all other b l = 1 to the code where b N 1 = 1 and all
other b l = 0 . For this transition, all unit current sources in the circuit are subject
to switching, resulting in a large glitch and a large DNL error, as discussed in
Chapter 2. This is illustrated in Fig. 3.1(a), where S(x) , i.e., the number of
switched unit current sources in the transition from x 1 to x , is plotted for a 6bit binary-weighted DAC. The large peak in the middle of the plot corresponds to
the middle code transition. G(x(n), x(n 1)) , i.e., the number of switched unit
current sources in the transition from x(n 1) to x(n) , for the 6-bit binaryweighted DAC is visualized in Fig. 3.1(b). The values of x(n) and x(n 1) are
given on the x and y axes, respectively. The different values of G(x(n), x(n 1))
are represented with different shades of gray, as indicated on the scale in the right
part of Fig. 3.1(b). It is observed that for points in the upper left and lower right
quadrants, corresponding to transitions for which b N 1 changes, the values of
G(x(n), x(n 1)) are large even if the corresponding values of x(n) x(n 1)
are small. Hence, there are many code transitions for which a small change at the
input results in large glitches due to that most of the unit current sources are
switching. The one-dimensional plot in Fig. 3.1 may mislead the observer to
believe that there is only one such code transition.

94

Segmented DACs

G(x(n), x(n1))

S(x)

x(n1)

S(x)

63

31

63

63

31

31

15
7
32
x

63

(a)
Figure 3.1

31
x(n)

63

(b)

(a) S(x) and (b) G(x(n), x(n 1)) for a 6-bit binary-weighted DAC.

3.2 Segmented DACs

In order to reduce the number of switched unit current sources, it is common to
use a segmented architecture [11, 17, 50]. In a K -bit segmented N -bit DAC, the
K MSBs of the input (which is assumed to be given in binary-offset representation) are encoded into a thermometer code. Hence, the weights are

l
for the binary-weighted LSBs .
wl = 2
N

K
for
the thermometer-coded MSBs
2

(3.2)

The number of bits in the control word is

NB seg(N , K ) = N K + 2 K 1 .

(3.3)

The reduction in number of switched unit current sources in a transition compared with a binary-weighted DAC is illustrated in Fig. 3.2, where S(x) and
G(x(n), x(n 1)) are plotted for various degrees of segmentation of a 6-bit DAC.
The lowest degree of segmentation, i.e., 2-bit segmentation, is illustrated with the
plots in Fig. 3.2(a) and (b). Comparing Fig. 3.1(a) with Fig. 3.2(a) shows that the
value of S(x) for the middle code transition is reduced from 63 ( = 2 N 1 ) to 31
( = 2 N 1 1 ) when using a 2-bit segmented instead of a binary-weighted architecture, but for the remaining code-transitions, S(x) is identical for the two architectures. A larger difference between the two architectures is observed when
comparing Fig. 3.1(b) with Fig. 3.2(b). The number of switched unit current
sources are largely reduced for a multitude of code transitions when using a 2-bit
segmented instead of a binary-weighted architecture. A further reduction is
obtained by increasing the degree of segmentation, as illustrated in Fig. 3.2(c)
95

Digital Encoding in Current-Steering DACs

and (d), where S(x) and G(x(n), x(n 1)) are plotted for a 3-bit segmented 6-bit
DAC. The plots for a 6-bit segmented, or fully thermometer-coded, 6-bit DAC
are shown in Fig. 3.2(e) and (f). It is readily deduced that for any type of code
used in a current-steering DAC,
G(x(n), x(n 1)) x(n) x(n 1) .

(3.4)

For the fully thermometer-coded DAC,

G(x(n), x(n 1)) = x(n) x(n 1) .

(3.5)

Hence, in terms of the number of switched unit current sources, the fully thermometer-coded architecture is an optimal solution. However, using a fully thermometer-coded architecture results in a large hardware complexity. For example,
for N = 14 we have 16 383 bits in the control word yielding equally many control wires and switches and a complex routing of wires. Hence, there is a trade off
between performance and hardware complexity.
It should be mentioned that there exist variations on the segmented architecture.
For example, several groups of bits in the input may be encoded into thermometer codes with different weights. An example is the doubly segmented 14-bit
DAC presented in Sec. 5.4 for which both the 7 MSBs and the 7 LSBs are
encoded into thermometer code.

3.3 Decomposed DACs

The decomposed DAC architecture was proposed in [54] as an alternative to the
traditional segmented architecture for obtaining small numbers of switched unit
current sources. The simplest form of decomposition, denoted 1-layer decomposition, is presented in Sec. 3.3.1. Recursively applying 1-layer decomposition
results in multi-layer decomposition, which is discussed in Sec. 3.3.2.
3.3.1 1-Layer Decomposition
In 1-layer decomposition, the N -bit input word is decomposed into two ( N 1 )bit words and one 1-bit word. The 1-bit word is a copy of the MSB of the input. If
the MSB is 0, the N 1 LSBs of the input are mapped onto the first ( N 1 )-bit
word, whereas all bits in the second ( N 1 )-bit word are set to 0. If, on the other
hand, the MSB is 1, the LSBs are mapped onto the second ( N 1 )-bit word,
whereas all bits of the first ( N 1 )-bit word are set to 1. The mapping is illustrated for the case N = 4 in Table 3.1 where the integers 0 to 15 are represented
in binary-offset and 1-layer decomposed codes. For the decomposed case in

96

Decomposed DACs

S(x)

G(x(n), x(n1))

x(n1)

S(x)

63

31

63

63

31

31

15
7
1

32
x

63

(a)

63

(b)

S(x)

G(x(n), x(n1))

x(n1)

63

S(x)

31
x(n)

31

63

63

31

31

15
7
1

32
x

63

(c)

63

(d)

S(x)

G(x(n), x(n1))

x(n1)

63

S(x)

31
x(n)

31

63

63

31

31

15
7
1

32
x
(e)

Figure 3.2

63

31
x(n)

63

(f)

S(x) and G(x(n), x(n 1)) for segmented 6-bit DACs. The plots for 2-bit segmentation are shown in (a) and (b), the plots for 3-bit segmentation are shown in
(c) and (d), and the plots for 6-bit segmentation are shown in (e) and (f).

97

Digital Encoding in Current-Steering DACs

Table 3.1, the column in the middle represents the 1-bit word, whereas the three
columns to the right represents the first ( N 1 )-bit word and the three columns
to the left represents the second ( N 1 )-bit word.
decimal

Table 3.1

binaryoffset

decomposed

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1

0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1

0
0
0
0
0
0
0
0
0
1
0
1
0
1
0
1

0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1

0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1

0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
1

0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1

weight:

Representation of the integers 0 to 15 in binary-offset and 1-layer decomposed

codes.

3.3.2 Multi-Layer Decomposition

Increasing the degree of segmentation in a segmented architecture is obtained by
increasing the number of bits that are encoded to thermometer code. The corresponding operation in a decomposed architecture is to increase the number of
layers of decomposition. For example, recursively applying 1-layer decomposition to the two ( N 1 )-bit words resulting from 1-layer decomposition results in
2-layer decomposition and a total of four ( N 2 )-bit words and one 1-bit word.
In the general case with M layers of decomposition, there are 2 M ( N M )-bit
words and 2 M 1 1-bit words, yielding
NB dec(N , M ) = 2 M ( N M + 1 ) 1

(3.6)

bits in the control word. Multi-layer decomposition is illustrated with an encoder

for 3-layer decomposition in Fig. 3.3.

98

Decomposed DACs

1-layer
1-layer

N2

1-layer

encoder N3

encoder N2

N3

1-layer

N3
1

encoder N3

N1
1

encoder N1

1-layer
1-layer

N2

N3
1

encoder N3

encoder N2

1-layer

N3
1

encoder N3
Figure 3.3

Encoder for 3-layer decomposition.

3.3.3 Properties of Decomposed DACs

In this section, we present some properties of decomposed DACs. We would like
to compare an M -layer decomposed DAC with the corresponding segmented
DAC. However, due to the different hardware structures, it is not trivial to conclude which degree of segmentation that corresponds to a given degree of decomposition in terms of hardware complexity. Using the number of bits in the control
word as a metric for the hardware complexity, as has been discussed earlier in
this chapter, is one choice. In this section, we make a simple pairwise comparison
between M -layer decomposed DACs and ( M + 1 )-bit segmented DACs. This
choice is motivated in the following points.
1. If the trivial cases 0-layer decomposition and 1-bit segmentation are included
in the analysis, there are N different types of decomposition and N different
types of segmentation. This allows us to make pairwise comparisons between
the two types of architectures.
2. Considering the largest and smallest possible values of M , i.e., M = N 1
and M = 0 , the two types of architectures are equivalent. 0-layer decomposition and 1-bit segmentation both result in a binary-weighted architecture, and
( N 1 )-layer decomposition and N -bit segmentation both result in a fully
thermometer-coded architecture.

99

Digital Encoding in Current-Steering DACs

3. The largest bit weights for M -layer decomposition and ( M + 1 )-bit segmentation are equal. A consequence of this is that the largest values of S(x) are also
equal in the two cases.
The number of bits in the control word is included as a metric for hardware complexity in the performance comparisons presented in Sec. 3.6.
Consider once again the middle code transition. In a binary-weighted DAC,
2 N 1 (i.e., all) unit current sources are switched. This value is reduced to
2 N 1 1 using 2-bit segmentation. For a 1-layer decomposed DAC, the only
thing that happens in this code transition is that the bit in the 1-bit word is
changed from 0 to 1. Hence, only one unit current source is switched. This is
shown in Fig. 3.4(a), where S(x) is plotted for a 1-layer decomposed 6-bit DAC.
The large peak that is present at the middle code transition for the 2-bit segmented DAC (Fig. 3.2(a)) is removed using 1-layer decomposition. For the
remaining values of x , the values of S(x) are equal for the two architectures. The
difference between the two architectures is more obvious if a general code transition from x(n 1) to x(n) is considered. Examining Fig. 3.2(b) and (f) and
Fig. 3.4(c), we find that for the upper left and lower right quadrants, the values of
G(x(n), x(n 1)) for the 1-layer decomposed DAC is equal to those of the fully
thermometer-coded DAC, whereas the values for the 2-bit segmented DAC are
higher. Hence, for approximately half of the code transitions, the 1-layer decomposed DAC is optimal in terms of the number of switched unit current sources.
For the two other quadrants, the values of G(x(n), x(n 1)) for the 1-layer
decomposed and 2-bit segmented DACs are equal.
The values of S(x) and G(x(n), x(n 1)) for a 2-layer decomposed 6-bit DAC are
plotted in Fig. 3.4(c) and (d), respectively. The maximum value of S(x) is the
same as for a 3-bit segmented DAC, but it appears for fewer values of x . In terms
of G(x(n), x(n 1)) , the number of transitions for which the 2-layer decomposed
DAC is equivalent to a fully thermometer-coded DAC is higher than the corresponding number for a 1-layer decomposed DAC. S(x) and G(x(n), x(n 1)) for
a 3-layer decomposed 6-bit DAC are plotted in Fig. 3.4(e) and (f), respectively, in
order to further illustrate how the number of switched unit current sources is
affected by an increasing number of layers.

3.4 Partially Decomposed DACs

The qualitative comparisons between decomposed and segmented architectures
presented in the previous section indicate some advantages for the decomposed
architecture. However, as has been hinted earlier, the two architectures have different hardware complexity. For example, if the number of bits in the control
word is a relevant measure of hardware complexity, the designer should be aware
100

Partially Decomposed DACs

S(x)

G(x(n), x(n1))

x(n1)

S(x)

63

31

63

63

31

31

15
7
1

32
x

63

(a)

63

(b)

S(x)

G(x(n), x(n1))

x(n1)

63

S(x)

31
x(n)

31

63

63

31

31

15
7
1

32
x

63

(c)

63

(d)

S(x)

G(x(n), x(n1))

x(n1)

63

S(x)

31
x(n)

31

63

63

31

31

15
7
1

32
x
(e)

Figure 3.4

63

31
x(n)

63

(f)

S(x) and G(x(n), x(n 1)) for decomposed 6-bit DACs. The plots for 1-layer
decomposition are shown in (a) and (b), the plots for 2-layer decomposition are
shown in (c) and (d), and the plots for 3-layer decomposition are shown in (e)
and (f).

101

Digital Encoding in Current-Steering DACs

of that an M -layer decomposed DAC has more bits in the control word than an
( M + 1 )-bit segmented DAC. This is illustrated in Fig. 3.5, where
NB seg(6, M + 1) and NB dec(6, M ) given by (3.3) and (3.6), respectively, are
plotted as functions of M .
Number of bits vs. M

NB

10

10

(M+1)bit segmented
Mlayer decomposed
0

10

M
Figure 3.5

Number of bits in the control words for 6-bit DACs utilizing M -layer decomposition and ( M + 1 )-bit segmentation.

A modified version of the decomposed architecture, denoted the partially decomposed architecture, was proposed in [55] in order to obtain a decomposed architecture with reduced hardware complexity. The idea behind partial
decomposition is that if the typical signal used in the application that the DAC is
intended for is nonuniform, it is not necessary to use an equal amount of decomposition for the whole range of possible input values. Instead, one should focus
on the range of input values that have the largest probability of occurring, and use
a lower degree of decomposition for the other ranges of input values. A general
partially decomposed architecture is characterized by that in each layer, only a
subset of the binary-weighted words are selected for further decomposition. For
example, in multi-carrier applications, the signals approximately have Gaussian
distributions where the values of most samples are close to the middle of the
input range, whereas very high and very low values are rarely occurring. For such
applications, the special case of partial decomposition illustrated with the 4-layer
encoder in Fig. 3.6 might be a suitable choice. For this special case of partial
decomposition, only the two binary-weighted words closest to the center of the
encoder tree are selected for further decomposition in each layer. For convenient
notation, the term partial decomposition will in the remainder of this chapter
refer to this special case of partial decomposition.

102

Other Codes

1-layer
N

1-layer

N1

N2
1

encoder N2

N3
1

encoder N3

1-layer

N4
1

encoder N4

encoder N1

1-layer

N2
1

encoder N2

Figure 3.6

1-layer

1-layer

N3
1

encoder N3

1-layer

N3
1

encoder N3

Encoder for a special case of 4-layer partial decomposition.

The number of bits in the control word for an N -bit DAC utilizing M -layer partial decomposition is
NB pdec(N , M ) = M ( 2N M 1 ) + 1 for M > 2 .

(3.7)

For M = 1 and M = 2 , the partially decomposed architecture is identical to the

decomposed architecture and, therefore, has the same properties. However, for
M > 2 , the architectures are different. S(x) and G(x(n), x(n 1)) for a 3-layer
partially decomposed 6-bit DAC are plotted in Fig. 3.7(a) and (b), respectively, to
illustrate the properties of partially decomposed converters in terms of the number of switched unit current sources. The corresponding plots for a 4-layer partially decomposed 6-bit DAC are shown in Fig. 3.7(c) and (d), respectively.

3.5 Other Codes

The codes discussed in the previous sections are not the only codes used or proposed for use in DACs. As mentioned in Sec. 3.2, an extension of the segmented
architecture is the multi-segmented architecture where several segments of the
binary-weighted input are encoded into thermometer codes with different
weights. An example of such a DAC, i.e., a 14-bit DAC where both the seven
MSBs and the seven LSBs are encoded into 127-bit thermometer codes, is presented in Sec. 5.4. For this DAC, the weights for the thermometer-coded LSBs
are 1 and the weights for the thermometer-coded MSBs are 128. Several other
code types providing compromises between the binary-weighted and fully thermometer-coded architectures have been proposed (e.g., [56, 57]). None of these
are, however, considered in this work.
103

Digital Encoding in Current-Steering DACs

G(x(n), x(n1))

S(x)

x(n1)

S(x)

63

31

63

63

31

31

15
7
32
x

63

(a)

63

(b)

G(x(n), x(n1))

S(x)

x(n1)

63

S(x)

31
x(n)

31

63

63

31

31

15
7
32
x

1
(c)
Figure 3.7

63

31
x(n)

63

(d)

S(x) and G(x(n), x(n 1)) for 6-bit DACs utilizing a special case of partial
decomposition. The plots for 3-layer partial decomposition are shown in (a) and
(b), and the plots for 4-layer partial decomposition are shown in (c) and (d).

3.6 Comparison of Codes

In this section, we compare the different DAC architectures presented earlier in
this chapter using some of the behavioral-level models discussed in Chapter 2.
The influence of matching errors is investigated in Sec. 3.6.1, whereas the glitch
properties of the different architectures are examined in Sec. 3.6.2. 14-bit DACs
are considered in all simulations. Four different test signals are used, all containing 2 12 samples and having the mean value

2 14 1- = 8191.5 .
x dc = ---------------2

104

(3.8)

Comparison of Codes

Test signals x 1(n) and x 2(n) are both sinusoidal signals with normalized frequency
f signal
f N = -------------- 0.142 .
fs

(3.9)

The amplitudes of x 1(n) and x 2(n) are

2 14 1x 1, ac = ---------------2

(3.10)

and
2 14 1- ,
x 2, ac = ---------------16

(3.11)

respectively. Test signals x 3(n) and x 4(n) are both (clipped) white Gaussian signals with standard deviations
3 1800

(3.12)

and
4 220 ,

(3.13)

respectively.
3.6.1 Influence of Matching Errors
In this section, the influence of matching errors on the performance of the different DAC architectures. The matching errors in the unit current sources are modeled with mutually uncorrelated stochastic variables having Gaussian
distributions with expectation value 0 and a 5 % relative standard deviation. For
each architecture, 10 4 different stochastic outcomes of the matching errors are
considered. The values of SNDR and SFDR that are presented in this section are
the 90 % yield values, i.e., the SNDR and SFDR requirements resulting in 90 %
yield. The quantization error is also included in the SNDR calculations in this
section.
Results from simulations using test signal x 1(n) are shown in Fig. 3.8 and
Fig. 3.9. In Fig. 3.8(a) and (b), SNDR is plotted as a function of M and the number of bits in the control word, respectively. There is only a 2.5 dB difference

105

Digital Encoding in Current-Steering DACs

between the best and the worst values. The differences between the architectures
are even smaller when considering the SFDR plots shown in Fig. 3.9(a) and (b)
where all values are between 70 dB and 71 dB.
SNDR, test signal x1

SNDR, test signal x

69

69

68

68
SNDR [dB]

SNDR [dB]

67
segmented
decomposed
partially decomposed

66
65
0

4
M

67
segmented
decomposed
partially decomposed

66
65 1
10

10

10
(b)

SNDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 1(n) .
SFDR, test signal x1

SFDR, test signal x1

71.5

71.5

segmented
decomposed
partially decomposed

71

SFDR [dB]

SFDR [dB]

segmented
decomposed
partially decomposed

70.5

70
0

4
M
(a)

Figure 3.9

106

NB

(a)
Figure 3.8

10

71

70.5

70 1
10

10

10

10

NB
(b)

SFDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 1(n) .

Comparison of Codes

Results from simulations using test signal x 2(n) are shown in Fig. 3.10 and
Fig. 3.11. Here, clear improvements are present when the degrees of segmentation and decomposition are increased. SNDR is plotted as a function of M and
the number of bits in the control word in Fig. 3.10(a) and (b), respectively. There
is a 9 dB span between the best and the worst values plotted. Fig. 3.10 shows an
advantage for the decomposed and partially decomposed architectures when the
parameter M is used in the comparison. Specifically, an 8 dB improvement over
the binary-weighted architecture is obtained by simply applying 1-layer decomposition. If instead the number of bits in the control word is the important parameter, the three architectures yield similar performance. Similar relations between
the architectures are observed in the SFDR plots shown in Fig. 3.11(a) and (b).
SNDR, test signal x2

60

60

58

58

56

56

SNDR [dB]

SNDR [dB]

SNDR, test signal x2

54
52

segmented
decomposed
partially decomposed

50
48
0

4
M
(a)

Figure 3.10

54
52

segmented
decomposed
partially decomposed

50
8

48 1
10

10

10

10

NB
(b)

SNDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 2(n) .

We now consider the results for the Gaussian distributed test signals. SNDR
using test signal x 3(n) is plotted as a function of M and the number of bits in the
control word in Fig. 3.12(a) and (b), respectively. Also for this signal, there are
clearly visible performance improvements when the degrees of segmentation and
decomposition are increased. Plotting SNDR vs. M indicates a small advantage
for the decomposed and partially decomposed architectures, whereas plotting
SNDR vs. the number of bits in the control word indicates a small advantage for
the segmented architecture.
For the test signals used so far, the three architectures have similar behavior when
the number of bits in the control word is considered as the relevant measure of
hardware complexity. For some cases, the partially decomposed and decomposed

107

Digital Encoding in Current-Steering DACs

SFDR, test signal x

SFDR, test signal x

64

64

62

62

60

60

SFDR [dB]

SFDR [dB]

58
56

segmented
decomposed
partially decomposed

54
52
0

4
M

58
56

segmented
decomposed
partially decomposed

54
52 1
10

SNDR, test signal x3

62

60

60
SNDR [dB]

SNDR [dB]

SFDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 2(n) .

62

58
56
segmented
decomposed
partially decomposed

54

4
M
(a)

Figure 3.12

10

(b)

SNDR, test signal x3

52
0

10
NB

(a)
Figure 3.11

10

58
56
segmented
decomposed
partially decomposed

54

52 1
10

10

10

10

NB
(b)

SNDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 3(n) .

architectures are slightly better than the segmented. For other cases, the relation
is the opposite. For signal x 4(n) , which has a Gaussian distribution with small
standard deviation, the situation is different. SNDR is plotted as a function of M
and the number of bits in the control word in Fig. 3.13(a) and (b), respectively. A
benefit of the decomposed and partially decomposed architecture is that by
merely applying 1-layer decomposition, the SNDR improvement over the binary-

108

Comparison of Codes

weighted architecture is approximately 12 dB. Obtaining the same improvement

in performance using a segmented architecture requires 6-7 bits of segmentation
and a factor of 2.4-4.6 as many bits in the control word.
SNDR, test signal x4

SNDR, test signal x

55

55

50

50
SNDR [dB]

SNDR [dB]

45
segmented
decomposed
partially decomposed

40
35
0

4
M

45
segmented
decomposed
partially decomposed

40

35 1
10

(a)
Figure 3.13

10

10

10

NB
(b)

SNDR due to mismatch plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 4(n) .

The simulation results for the four test signals can be summarized as follows.
Making pairwise comparisons between the different architectures using the
parameter M yields higher performance for the decomposed and partially
decomposed architectures than for the segmented architecture. Using the number
of bits as the relevant measure of hardware complexity yields similar performance for all architectures for the first three test signals. For test signal x 4(n) ,
there was a clear advantage for the decomposed and the partially decomposed
architectures. Comparing M -layer decomposition with M -layer partial decomposition shows that they have nearly identical performance, other than for the
full-scale sinusoidal test signal. Due to the lower hardware complexity, the partially decomposed architecture is preferred over the decomposed architecture.
3.6.2 Influence of Glitches
In this section, we use the glitch model developed in Sec. 2.4 to investigate the
properties of the different architectures. The calculation of SNDR is carried out
as follows. The input referred glitch signal
P g(0)
P g(0)
- g k(n) = --------------- G(x k(n), x k(n 1))
g ir, k(n) = --------------P(0)
P(0)

(3.14)

109

Digital Encoding in Current-Steering DACs

is constructed in accordance with the procedure given in Sec. 2.4.2. Further, we

set
P g(0)
--------------- = 0.003 .
P(0)

(3.15)

The total power of noise and distortion, P nd , and the signal power, P signal , are
calculated as the variances of g ir, k(n) and x k(n) , respectively. Hence, dc components in the signals are discarded and the quantization error is not considered in
the calculations.
The calculation of SFDR for the sinusoidal test signals utilizes the DFT of the
signal
x g, k(n) = x k(n) + g ir, k(n) ,

(3.16)

as in the simulation examples in Sec. 2.4.3.

The resulting SNDR and SFDR for the different test signal are plotted in
Fig. 3.14-Fig. 3.19. In the (a) figures, SNDR or SFDR is plotted vs. the parameter
M , whereas in the (b) figures, SNDR or SFDR is plotted vs. the number of bits in
the control word.
SFDR and SNDR for test signal x 1(n) are plotted in Fig. 3.14 and Fig. 3.15,
respectively. It is observed that, except for minor parts of the (b) figures, the
decomposed and partially decomposed architectures result in better performance
than the segmented architecture.
An interesting property of the decomposed architecture is that the performance
has a maximum for 2-3 layers and then actually decreases with increasing number of layers and approaches the curve for the segmented architecture. Since the
number of switched unit current sources decreases with increasing M , one would
expect the performance to be monotonically increasing with increasing M . The
explanation for this unexpected behavior is that the fraction of the total glitch
power associated with the dc component (which is discarded in the SNDR calculations) is larger for M = 2, 3 than for larger values of M . It should be noted
that the maximum values of SNDR and SFDR obtained using decomposition and
partial decomposition are not reached using any degree of segmentation (at least
not for up to 9-bits of segmentation).
The SNDR and SFDR resulting from test signal x 2(n) are plotted in Fig. 3.16
and Fig. 3.17, respectively. The relations between the different architectures are
similar to those for test signal x 1(n) .

110

Comparison of Codes

SNDR, test signal x

SNDR, test signal x

63

63

62

62

61

61

SNDR [dB]

SNDR [dB]

60
59

segmented
decomposed
partially decomposed

58
57
0

4
M

60
59

segmented
decomposed
partially decomposed

58
57 1
10

SFDR, test signal x1

64

62

62
SFDR [dB]

SFDR [dB]

SNDR due to glitches plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 1(n) .

64

60
segmented
decomposed
partially decomposed

58

4
M
(a)

Figure 3.15

10

(b)

SFDR, test signal x1

56
0

10
NB

(a)
Figure 3.14

10

60
segmented
decomposed
partially decomposed

58

56 1
10

10

10

10

NB
(b)

SFDR due to glitches plotted as functions of (a) M and (b) the number of bits in
the control word for the different architectures using test signal x 1(n) .

The SNDR values resulting from test signals x 3(n) and x 4(n) are plotted in
Fig. 3.18 and Fig. 3.19, respectively. For test signal x 3(n) , the three architectures
have similar performance when plotted vs. the number of bits in the control word.
However, for signal x 4(n) , which has a smaller standard deviation than x 3(n) ,

111

Digital Encoding in Current-Steering DACs

SNDR, test signal x

SNDR, test signal x

70

70

60

60
SNDR [dB]

SNDR [dB]

50
segmented
decomposed
partially decomposed

40
30
0

4
M

50
segmented
decomposed
partially decomposed

40
30 1
10

SFDR, test signal x2

65

60

60

55

55

SFDR [dB]

SFDR [dB]

SNDR due to glitches plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 2(n) .

65

50
45

segmented
decomposed
partially decomposed

40
2

4
M
(a)

Figure 3.17

10

(b)

SFDR, test signal x2

35
0

10
NB

(a)
Figure 3.16

10

50
45

segmented
decomposed
partially decomposed

40
8

35 1
10

10

10

10

NB
(b)

SFDR due to glitches plotted as functions of (a) M and (b) the number of bits in
the control word for the different architectures using test signal x 2(n) .

the decomposed and partially decomposed architectures have obvious advantages

compared with the segmented architecture. In order to reach the performance
obtained with 1-layer decomposition, 7-bit segmentation is required.

112

Comparison of Codes

SNDR, test signal x

SNDR, test signal x

60

60

55

55
SNDR [dB]

SNDR [dB]

50
segmented
decomposed
partially decomposed

45
40
0

4
M

50
segmented
decomposed
partially decomposed

45
40 1
10

SNDR, test signal x4

60

50

50
SNDR [dB]

SNDR [dB]

SNDR due to glitches plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 3(n) .

60

40
segmented
decomposed
partially decomposed

30

4
M
(a)

Figure 3.19

10

(b)

SNDR, test signal x4

20
0

10
NB

(a)
Figure 3.18

10

40
segmented
decomposed
partially decomposed

30

20 1
10

10

10

10

NB
(b)

SNDR due to glitches plotted as functions of (a) M and (b) the number of bits
in the control word for the different architectures using test signal x 4(n) .

Considering the decomposed and partially decomposed architectures, we conclude that 2 or 3 layers appear to be the proper choice to obtain the best or close
to the best possible performance (in terms of the glitches modeled in Sec. 2.4) for
the test signals used. Obtaining the same performance with a segmented architecture is either not possible or requires a large degree of segmentation.

113

Digital Encoding in Current-Steering DACs

3.6.3 Simulation Result Summary

In this section, we summarize the simulation results on matching errors and
glitches presented in Sec. 3.6.1 and Sec. 3.6.2. Using the parameter M for making a simple comparison between different degrees of decomposition, partial
decomposition, and segmentation shows that the decomposed and partially
decomposed architectures are better than the segmented architecture both in
terms of sensitivity to matching errors and in terms of glitches. If the number of
bits in the control word is used as a measure of hardware complexity, the three
architectures yield similar performance in terms of matching errors, except for a
white Gaussian test signal with small standard deviation. For this case, the partially decomposed architecture was the best for all values of the number of bits.
The results from the glitch simulations are similar. However, for the full-scale
sinusoidal test signal, the performance obtained with 2 and 3 layers of decomposition was not reached with any degree of segmentation considered in the simulations.
The authors opinion, based on the simulation results, is that using 2 or 3 layers
of decomposition results in a good trade off between hardware complexity and
performance. Increasing the degree of decomposition does not result in a large
performance improvement. In some cases, it actually results in a performance
degradation. Moreover, in most cases, a similar or higher hardware complexity
(in terms of number of bits in the control word) is required to obtain a similar
performance using a segmented architecture. The simulation results indicate that
the decomposed and partially decomposed architectures are viable alternatives to
the traditionally used segmented architectures and that the two former architectures may be preferred over the latter when the signal contains many samples
close to the middle of the input range. The results could, of course, be different if
other measures of hardware complexity and other classes of test signals are used.

3.7 Encoder Implementation

An important factor to consider when choosing the code for the control word is
that the hardware overhead for implementing the encoder should be acceptable.
In this section, we give an overview of possible implementations of encoders for
segmented, decomposed, and partially decomposed architectures. The purpose is
to show that the encoder implementation for these architectures is trivial.
3.7.1 Decomposition Encoder Implementation
The operation of a 1-layer decomposition encoder is described in Sec. 3.3.1. A
straightforward solution for the implementation of a 1-layer decomposition
encoder obtained from that description is shown in Fig. 3.20. It consists of N 1

114

Encoder Implementation

OR gates and N 1 AND gates. In practice, an AND gate is implemented by

connecting an inverter to the output of a NAND gate and an OR gate is implemented by connecting an inverter to the output of a NOR gate. Hence, if the complementary outputs are used, the 1-layer encoder can be implemented with N 1
NOR-gates, N 1 NAND gates, and 1 inverter increasing the speed of the
encoder and reducing the transistor count.
MSB

(N1)-bit word #2

LSB
MSB

1-bit word
MSB

N-bit input
(N1)-bit word #1
LSB
Figure 3.20

LSB

Implementation of an encoder for 1-layer decomposition.

Implementing the 1-layer encoders in Fig. 3.3 according to the structure illustrated in Fig. 3.20 results in the implementation of a multi-layer encoder. Naturally, since the MSB of each binary-weighted word is connected to several gate
inputs, additional drivers are required for these bits in order to obtain sufficient
speed. Also for the multi-layer case, it is possible to increase the speed of the
encoder and reduce the transistor count by properly replacing AND and NAND
gates with NAND and NOR gates and by inserting inverters in the proper places.
3.7.2 Binary-to-Thermometer Encoder Implementation
There is an obvious and trivial solution for the implementation of a K -bit binaryto-thermometer encoder, i.e., a ( K 1 )-layer decomposition encoder. Another
solution, that has been used for some of the DACs implemented in this work, is
illustrated in Fig. 3.21, where b k denotes bits in the input and t l denotes bits in
115

Digital Encoding in Current-Steering DACs

the output. The simplest type of binary-to-thermometer encoder, i.e., the 2-bit
encoder, is illustrated in Fig. 3.21(a). It consists of one AND gate and one OR
gate. In Fig. 3.21 it is shown how a ( K 1 )-bit encoder can be used together with
a set of AND gates and OR gates to implement a K -bit encoder. The ( K 1 )-bit
encoder used for the implementation of the K -bit encoder is implemented in the
same way utilizing a ( K 2 )-bit encoder, which in turn utilizes a ( K 3 )-bit
encoder, etc. A more thorough description of this type of encoder is given in [27].
A similar (possibly identical) solution has been used by others [58]. As for the
decomposition encoders discussed in Sec. 3.7.1, an increase in speed and a
decrease in transistor count can be obtained through appropriate replacing of
AND and OR gates with NAND and NOR gates. This is further discussed in [27].
t3
b1

t2
t1

b0
(a)

t2K1
t2K2

t2K1+1
bK

t2K1
t2K11

bK1

t2K12

b1

(K1)-bit
binary-to-thermometer
encoder

b0

t1

(b)
Figure 3.21

116

Implementation of (a) 2-bit and (b) K -bit binary-to-thermometer encoders.

4 Correction and
Compensation of Errors
It can be hard to meet a DAC design specification using a straightforward implementation. In this chapter, techniques for improvement of the DAC linearity are
discussed. Dynamic element matching techniques are used for transforming spurious tones caused by matching errors into white or shaped noise. These techniques are overviewed in Sec. 4.1 together with a technique developed in this
work for the decomposed DAC architecture. Distributed biasing of current
sources, which has been used in two of the implemented DACs presented in
Chapter 5 to reduce the errors due to linearly graded parameter variations, is discussed in Sec. 4.2. In modulation, feedback of the quantization error is utilized to spectrally shape the quantization noise to reduce its power within the
signal band. A technique based on this principle has been developed for spectral
shaping of DAC nonlinearity errors utilizing a DAC model in a feedback loop.
The basic idea is presented in Sec. 4.2 together with two examples of utilization
of the technique.

4.1 Dynamic Element Matching

Dynamic element matching (DEM) techniques are used for reducing the nonlinear distortion caused by matching errors. One purpose of this section is to provide a background to DEM in order to simplify the understanding of the
description of the DEM DAC presented in Sec. 5.3, where measurement and simulation results are presented as well.

117

Correction and Compensation of Errors

In all of the DAC architectures discussed in Chapter 3, the mapping from the
input to the control word is static, i.e., a given input x results in the same control
word each time it is applied. If mismatch is the dominating error source and we
consider the output in discrete time, this static mapping from the input to the control word results in the same error
e = y(x) y nom(x)

(4.1)

every time a given input x is applied. In other words, the error sequence e(n) is a
function only of the input sequence x(n) , i.e.
e(n) = f (x(n)) .

(4.2)

Hence, if x(n) is periodic, then e(n) is periodic with the same fundamental frequency as the input. For a sinusoidal input, this property causes harmonic distortion in the DAC output.
In DACs utilizing DEM, redundancy in the control word is exploited to allow a
given input x to be represented by several different control words to ensure that
the same error does not appear every time a given input x is applied. Generally,
we have
e(n) = f (x(n), r(n)) ,

(4.3)

where r(n) is a control sequence, which may be, e.g., (pseudo) random, a deterministic function of the input, or a combination of the two. With a proper choice
of r(n) , the error can be altered from yielding distortion to having more noiselike properties.
Using DEM reduces the spurious tones in the output to the cost of a higher noise
floor. In order to get an overall improvement in the SNDR, it is required that
oversampling is used. Therefore, DEM is especially suitable in audio applications where the signal bandwidth is low (compared with, e.g., bandwidths in DSL
applications) and a large amount of oversampling can be afforded.
Some DEM algorithms transform distortion into white noise, whereas the noiseshaping DEM techniques move a large amount of the noise out of the signal
band, similar to what a modulator does with the quantization noise. These two
types of DEM are discussed in Sec. 4.1.1-Sec. 4.1.3. There are also DEM techniques that minimize the number of switched unit elements [59, 60] and, hence,
the glitches. This approach is in Sec. 4.1.4 applied to the decomposed architecture to provide a reduction of spurious tones caused by mismatch without
increasing the number of switched unit current sources compared with the
decomposed architecture without DEM.

118

Dynamic Element Matching

4.1.1 Generalized DEM

x2(n)

x3(n)

scrambler

x1(n)

binary-to-thermometer encoder

A block diagram of a general DEM DAC proposed by Carley [61] is shown in

Fig. 4.1. It consists of a binary-to-thermometer encoder, a scrambler, and a set of
1-bit DACs whose individual outputs are summed to form the output of the DEM
DAC. Three digital signals, x 1(n) , x 2(n) , and x 3(n) , are indicated in Fig. 4.1.
The integer values of these three signals are identical, but different representations are used. The input x 1(n) uses a binary-offset representation, the intermediate signal x 2(n) uses a thermometer-coded representation, and the signal x 3(n)
controlling the 1-bit DACs uses a scrambled thermometer-coded representation.

r(n)
Figure 4.1

combined output

1-bit
DACs

Block diagram of a generalized DEM DAC.

Let t l(n) and u l(n) denote the individual bits of x 2(n) and x 3(n) , respectively.
The scrambler maps each t l(n) onto a unique u k(n) such that u k(n) = t l(n) .
Which t l(n) is mapped onto what u k(n) is determined by the control signal r(n) .
Each u l(n) controls one of the 1-bit DACs with an associated error l . Consider
first the case of a static mapping, i.e., letting r(n) be constant yielding that each
bit in x 2(n) is mapped onto the same bit in x 3(n) for every n . For simplicity, we
let
u l(n) = t l(n) for every n .

(4.4)

Then, the error at the output is given by

e(n) =

l t l(n)l .

(4.5)

119

Correction and Compensation of Errors

Hence, if the input is periodic, the error is also periodic, resulting in harmonic
distortion at the output. If instead r(n) is not constant, the mapping between the
bits in x 2(n) and x 3(n) is dynamic and the error adopts noise-like properties
rather than resulting in harmonic distortion, provided that the control signal r(n)
is properly chosen.
For an N -bit input, x 2(n) and x 3(n) both have 2 N 1 bits. Hence, there are
n map = ( 2 N 1 )!

(4.6)

different mappings between the bits in x 2(n) and x 3(n) (i.e., ways to reorder the
bits in x 2(n) ). For large N , implementing a scrambler capable of performing all
different mappings results in a large hardware overhead. Therefore, a proper subset of the n map different mappings that enables an efficient hardware implementation should be selected. There is a large amount of research on DEM circuit
techniques with reduced hardware complexity presented in the literature (see,
e.g., [62, 63, 64]). Some of these techniques are overviewed in the following. For
comparisons of different networks used for DEM realizations, see, e.g., [65, 66].
4.1.2 DEM Utilizing Switching Trees
One hardware-efficient way of implementing DEM is to utilize a binary switching tree. Two DEM techniques that utilize binary switching trees are the full randomization DEM (FRDEM) and the partial randomization DEM (PRDEM)
techniques proposed by Jensen and Galton [62]. These two techniques are briefly
overviewed in this section. The hardware structure of a DEM DAC utilizing a
binary switching tree is similar to that of a decomposed DAC described in
Sec. 3.3. The operation is, however, quite different. The DEM DAC relies on
switching many unit elements for each update instant to obtain a randomization
effect, whereas the decomposed DAC aims at keeping the number of switched
unit elements low to obtain small glitches and good static linearity.
Full Randomization DEM
The digital encoder used in an FRDEM [62] DAC is depicted in Fig. 4.2. The
input to the tree, denoted x(n) in Fig. 4.2, is in binary-offset representation, so
the tree performs both the binary-to-thermometer encoding and the scrambling.
Each switch layer, k , is controlled by a (pseudo) random control signal
r k(n) { 0, 1 } . Each switch in layer k has one ( k + 1 )-bit input and two k -bit
outputs which we denote out 1 and out 2 . These outputs are inputs to switches in
the layer k 1 . If r k = 1 , then the bits of out 1 are given the values of the k
LSBs of the input, while the MSB of the input is assigned to all bits of out 2 .
When r k = 0 , the MSB of the input is instead mapped onto the bits of out 1 and

120

Dynamic Element Matching

the k LSBs of the input are mapped onto out 2 . The number of output bits for
each switch is linearly decreasing with decreasing layer index, and the tree is terminated with the switching layer consisting of 1-bit outputs. These 1-bit signals
constitute a scrambled, thermometer coded word that is used to control 1-bit
DACs, whose outputs are summed yielding the total output for the DEM DAC.
An additional bit with the same weight as the LSB, and fixed value 0, is added
to the input to give the LSBs the same total weight as the MSB. This is required
because there is an even number of output bits from the switching tree, whereas a
thermometer coded word has an odd number of bits. This causes at least one of
the output bits from the tree to have the value 0.
layer 1
2

r1(n)

layer N1
N

N+1

to 1-bit DACs

switch
rN1(n)

layer N
x(n)

switch

switch
rN(n)
N

switch
rN1(n)
2

switch
r1(n)

Figure 4.2

Binary switching tree for implementing the FRDEM technique.

Partial Randomization DEM

For DACs with a large number of input bits, the hardware complexity of the
FRDEM switching tree becomes large, since the number of outputs from the tree
grows exponentially with the number of input bits. An approach that has been
proposed to trade the hardware complexity for a lower degree of randomization is

121

Correction and Compensation of Errors

the PRDEM technique [62]. In PRDEM, the switching tree is terminated before
1-bit outputs are reached, resulting in a lower hardware complexity. The outputs
of the last layer are used as inputs to DAC banks consisting of one 1-bit DAC and
one multi-bit DAC. Design, modeling, and measurements of a current-steering
PRDEM DAC is discussed in Sec. 5.3. From the simulations and measurements
presented there, we find that randomization in a few layers only is enough for
making the distortion due to mismatch negligible compared with the dynamic
errors. Hence, terminating the switching tree after a few layers is acceptable.
4.1.3 Mismatch-Shaping DEM
Using random scrambling has the effect of transforming harmonic distortion
caused by mismatch into approximately white noise. Hence, the power of the distortion is evenly distributed over the whole frequency range. To gain even more
SNDR, it is desirable to shape the noise, so that a larger portion of the noise
appears outside of the signal band, where it can be filtered out. This is the goal of
so called mismatch shaping DEM [67, 68, 69]. In mismatch shaping DEM, the
scrambling is performed such that the 1-bit signals u l(n) are chosen according to
[68]
1
u l(n) = ----- x 1(n) + z l(n) ,
M

(4.7)

where M is the number of 1-bit signals and z l(n) is a signal with very little power
within the signal band. The total output is
M

y(n) =

1--- ( K + l ) x 1(n) +
M

l=1

= x 1(n) K 1 +

----M1- ( K + l ) zl(n) =

l=1
M

l + ( K + l ) zl(n) ,

l=1

(4.8)

l=1

where K is a gain factor. The first term in the right-hand side of (4.8) is the
desired output (with a slight gain error). The second term is the error e(n) due to
mismatch. Moreover
M

x 1(n) =

ul(n) =

l=1

yielding

122

x 1(n) +

z l ( n) ,

l=1

(4.9)

Dynamic Element Matching

M

zl(n) = 0 .

(4.10)

l=1

Combining (4.8) and (4.10) yields

M

e(n) =

l zl(n) .

(4.11)

l=1

Since each z l(n) has very little power within the signal band, so does e(n) . The
construction of the different u l(n) is nontrivial. Several circuit solutions have
been proposed (see, e.g., [67, 68, 70, 71]), and there are also solutions where the
different u l(n) are multi-bit words.
4.1.4 DEM in Decomposed DACs
In this section, a DEM technique for the decomposed DAC architecture is proposed. The main benefit of the decomposed DAC architecture presented in
Sec. 3.3 is that the number of switched unit current sources is low for many input
transitions. In order to keep this property, the DEM technique proposed in this
section utilizes a conditional scrambler that takes the previous values of the control bits into account to avoid unnecessary switching of unit current sources. The
work presented in this section was first published in [72]. A similar technique for
thermometer-coded DACs was proposed in [59].
Proposed Technique
The proposed technique is illustrated in Fig. 4.3 with the modified 1-layer
decomposition encoder. A normal 1-layer encoder is cascaded with a block that
performs conditional pairwise scrambling of the bits having equal weights. We
let b l1 and b l2 denote bit l of the first and the second multi-bit output word from
the normal 1-layer encoder, respectively. The corresponding outputs from the
scrambler are denoted c l1 and c l2 , respectively. The bits of the 1-bit words are
denoted b and c without indices. The 1-bit word is not subject to scrambling,
i.e., c = b . If the pairwise scrambling of the bits are performed according to the
truth table given in Table 4.1, no additional unit current sources are switched. In
Table 4.1, n denotes the sequence index and a(n) is a random binary sequence
whose complement is denoted a(n) . The function of the conditional scrambler
can be implemented with a simple finite state machine including only two D flipflops and a small number of logic gates, except for the generation of the random
sequence. The implementation of the conditional scrambler is straightforward
and is not further discussed here. This type of pairwise scrambling can be applied

123

Correction and Compensation of Errors

Figure 4.3

1
N1 {bl }

N1

{c2l }

N1

{c1l }

conditionally scrambled output

2
N1 {bl }

conditional scrambler

1-layer decomposition encoder

input

to any type of DAC architecture having several bits with equal weights. In the
special case of decomposition, the realization of the conditional scrambler can be
simplified by noting that the combination [ b l2, b l1 ] = [ 1, 0 ] cannot occur. Hence,
the values of c l2(n) and c l1(n) in the shaded rows of Table 4.1 can be replaced
with dont-care values.

1-layer decomposition encoder with conditional scrambling.

Note that the proposed scrambling can only be applied to the 1-layer encoders in
the last layer. Applying scrambling to previous layers destroys the good glitch
properties of the decomposed architecture.
Simulation Results
In this section, we present simulation results from behavioral-level MATLAB
simulations. 14-bit DACs with different architectures are simulated. The errors
considered in the simulations are random, uncorrelated matching errors in the
unit current sources having a Gaussian distribution with a relative standard deviation of 5 %. A full-scale sinusoidal test signal with 2 12 samples is used. The normalized signal frequency of the test signal is
f signal
f N = -------------- 0.114 ,
fu

(4.12)

where f signal is the signal frequency and f u is the update frequency.

First, we consider the case where only the MSB is subject to conditional scrambling. For the remaining bits, c l2(n) = b l2(n) and c l1(n) = b l1(n) . Simulated signal spectra for 1-layer decomposed converters without and with conditional
scrambling of the MSB are shown in Fig. 4.4(a) and (b), respectively. It can be

124

Dynamic Element Matching

c l2(n 1)

c l1(n 1)

b l2(n)

b l1(n)

c l2(n)

c l1(n)

a(n)

a(n)

a(n)

a(n)

a(n)

a(n)

a(n)

a(n)

Table 4.1

Truth table for pairwise conditional scrambling.

observed that the distortion is largely reduced when DEM is applied, to the cost
of a higher noise floor. The matching errors in the unit current sources used in the
simulations were identical in the two cases.
The spectra plotted in Fig. 4.4 are the results from a single stochastic outcome of
the matching errors. Due to the stochastic nature of the matching errors, the
results may differ considerably between different outcomes. Hence, one single
stochastic outcome does not provide sufficient information to base general conclusions upon. Therefore, simulations were performed for 10 3 different stochastic outcomes and the SFDR was used as a metric for measuring the DAC
linearity. Five different cases were considered. Three DAC architectures without
scrambling are included as references. These are the binary-weighted architec125

Correction and Compensation of Errors

With DEM

20

20
PSD [dB]

PSD [dB]

Without DEM

40
60
80
100
0

60
80
100

0.1 0.2 0.3 0.4

Normalized frequency
(a)

Figure 4.4

40

0.5

0.1 0.2 0.3 0.4

Normalized frequency

0.5

(b)

Simulated output spectra for 14-bit 1-layer decomposed DACs (a) without and
(b) with conditional scrambling of the MSB.

ture, the 1-layer decompose architecture, and the 2-layer decomposed architectures. The two other architectures are the 1-layer decomposed architecture with
conditional scrambling of the MSB and the 2-layer decomposed architecture with
conditional scrambling of the MSB applied to the 1-layer encoders in the last
layer. The yield vs. SFDR requirement is plotted in Fig. 4.5 for all five cases. The
difference between the unscrambled cases is small. The 2-layer decomposed
architecture is slightly better than the 1-layer decomposed architecture, which in
turn is slightly better than the binary-weighted architecture. A large improvement, compared with the unscrambled cases, is obtained when the proposed
DEM technique is applied to 1-layer decomposition. The SFDR at 90 % yield is
74.7 dB, compared with 70.2 dB for the unscrambled 1-layer decomposed case.
It is also clear from the plot in that the spurious-tone reduction is much more efficient when the DEM technique is applied in the 1-layer case than in the 2-layer
case. In the latter case, only a small SFDR improvement is obtained compared
with the unscrambled cases when a high yield is targeted.
The results presented so far indicate that applying the proposed DEM technique
to the 1-layer decomposed architecture yields the most efficient randomization.
Therefore, we focus on the 1-layer decomposed architecture and investigate the
influence of further randomization by introducing conditional scrambling of not
only the MSB but also of the bit with the second highest significance. The yield
vs. SFDR requirement for this case (referred to as 2-bit DEM) is plotted in
Fig. 4.6. Included in this plot are also the curves for the 1-layer decomposed
architectures without DEM and with conditional scrambling of the MSB
(referred to as 1-bit DEM). The spurious-tone reduction obtained using 2-bit
DEM is better than using 1-bit DEM. For example, the SFDR value at 90 % yield
using 2-bit DEM is 75.8 dB, which is 1.1 dB higher than the result obtained

126

Distributed Biasing

Yield vs. SFDR requirement

1

Yield

0.8
0.6
0.4

binary weighted
1-layer
1-layer DEM
2-layer
2-layer DEM

60

65

0.2

Figure 4.5

70
75
80
SFDR requirement

85

90

Yield plotted as a function of the SFDR requirement for different 14-bit DACs.

using 1-bit DEM. The SFDR values at 90 % and 99 % yield for the architectures
utilizing DEM considered in the simulations are given in Table 4.2. The hardware
overhead for the 1-layer decomposed architecture utilizing 2-bit DEM, which is
the best of these architectures, is only two small finite state machines performing
the operation described in Table 4.1 and the circuitry required for the random
number generation. Hence, the technique can be implemented at a low cost.
The performance of the 1-layer decomposed architecture can, of course, be further improved by introducing conditional scrambling of more bits than two. Each
additional pair of bits that is scrambled requires an additional finite state
machine, i.e., the cost of the suggested hardware increases linearly with the number of scrambled bit pairs. However, the influence on the SFDR reduces with
decreasing bit weight. Hence, there is a trade-off between performance and hardware cost and at some point, the improvement obtained by introducing conditional scrambling of an additional pair of bits might be negligible and not worth
the cost of the additional hardware required.

4.2 Distributed Biasing

The impact of graded element matching errors was discussed in Sec. 2.2.3. One
technique that can be used to reduce the effect of graded errors is distributed biasing [38, 50]. This design technique is used in the DACs presented in Sec. 5.4 and
Sec. 5.5 to obtain good matching properties.

127

Correction and Compensation of Errors

Yield vs. SFDR requirement, 1 layer

1

Yield

0.8
0.6
0.4
0.2

Figure 4.6

no DEM
1-bit DEM
2-bit DEM

60

65

70
75
80
SFDR requirement

85

90

Yield plotted as a function of the SFDR requirement for different types of 14-bit
DACs utilizing 1-layer decomposition.

1-layer decomposition

2-layer decomposition

Yield
1 bit scrambled

2 bits scrambled

1 bit scrambled

90 %

74.7 dB

75.8 dB

71.3 dB

99 %

72.0 dB

72.5 dB

67.6 dB

Table 4.2

Obtained SFDR at different yield values.

A multiple-output PMOS current mirror is shown in Fig. 4.7. If we neglect the

influence of channel-length modulation (i.e., assume that the output transistors
have infinite output resistance), we have
W out
-I
I out, l = ----------W in in

(4.13)

provided that the output transistors are operating in the saturation region and that
the transistors are perfectly matched. The transistors have the same length. W out
is the width of the output transistors and W in is the width of the input transistor.
In the following we discuss how current mirrors can be utilized for biasing current sources and how the matching properties are affected.
In Fig. 4.8(a) we show an example where the current-source array is made of the
output transistors of a single multiple-output current mirror. Graded parameter
variations, discussed in Sec. 2.2.3, cause the output currents from the different
128

Modulation of Expected Errors

Vbias

Iin
Figure 4.7

Iout, 1

Iout, M

Multiple-output PMOS current mirror.

current sources to vary over the array. The matching of the output currents can be
improved by partitioning the array of current sources into smaller parts, letting
each such part be an individual multiple-output current mirror, as indicated in
Fig. 4.8(b). This is because the bias voltage is set individually for each current
mirror. If the input transistors are located close to the output transistors, the bias
voltage is set to give the proper output current for the values of transistor parameters in the proximity of the input transistors, reducing the current variations over
the array due to graded parameter mismatch, compared with the approach in
Fig. 4.8(a). In order for the distributed biasing strategy to work, it is important
that the matching errors between the different bias currents are small. The biasing
strategy has no effect on the influence of random matching errors, so this problem remains.

4.3 Modulation of Expected Errors

modulation, which was briefly discussed in Sec. 1.4.6, is a technique used in
data conversion to obtain high resolution with quantizers having few quantization
levels. This is obtained using the quantization error in a feedback loop, spectrally
moving a large amount of the quantization noise power to a frequency range outside of the signal band. However, an ideal quantizer is a poor model of a real data
converter. Reference levels will not be evenly spaced due to, e.g., component
mismatch. Other dynamic and static errors also occur, as discussed in Chapter 2.
In this section, we propose a linearization technique based on modulation that
also spectrally shapes nonlinearities arising from other sources than the quantization. The technique presented here was first proposed in [73].
4.3.1 Basic Idea
A modulator spectrally shapes the quantization noise through feedback of the
quantization error. We want to do the same thing with the distortion arising from
nonlinearities in the DAC. Therefore, the quantizer in Fig. 1.16(a) is substituted
with a quantizer cascaded with a model of the DAC. The modulator structure
used in this work is shown in Fig. 4.9. We refer to this circuit as a distortion
shaper. The output from the quantizer is used as the input to the real DAC. The

129

Correction and Compensation of Errors

Ibias

Ibias, 1

Ibias, 2

array of unit
current sources

array of unit
current sources

Ibias, K
(a)
Figure 4.8

(b)

Arrays of unit current sources with (a) global bias voltage generation and (b)
distributed bias voltage generation.

corresponding modulator is obtained if the DAC model in Fig. 4.9 is replaced

with a multiplication with one. Then, the error e(n) is the quantization error and
the structure is commonly referred to as an error-feedback modulator. The
signal and noise transfer functions are
STF(z) = 1

(4.14)

and
NTF(z) = 1 H (z) ,

130

(4.15)

Modulation of Expected Errors

respectively. In this work, we let NTF(z) be an FIR filter. An L th-order NTF is

chosen by placing L poles in the origin and L zeros strategically on the unit circle. The filter coefficients in H (z) are implicitly given by (4.15).
DAC input
x(n)

H(z)
Figure 4.9

DAC
model

e(n)

Block diagram of the proposed distortion shaper.

4.3.2 Spectral Shaping of Output Impedance Related Errors

An example on how the proposed distortion shaping technique can be applied to
reduce the distortion due to limited output impedance in the current sources is
given in this section. The DAC model used for estimating the errors is a simple
version of the low-complexity model discussed in Sec. 2.3.2 and illustrated in
Fig. 2.13. The LUT is addressed only by the MSB, b N 1(n) , of the DAC input.
If b N 1(n) = 0 , it is assumed that the relative step error e rel(n) = 0 , and if
b N 1(n) = 1 , then it is assumed that e rel(n) = a , where a is a model parameter that is chosen to maximize the SFDR within the signal band. The distortion
shaper used in the example utilizes an oversampling ratio of OSR = 4 and has a
a fifth order NTF with zeroes in z = 1 , z = e j ( OSR ) , and
z = e j ( ( 2 OSR ) ) . The DAC used in the example is the circuit described in
Sec. 5.2 and the single-ended output at the positive output terminal is considered.
Measured single-tone output spectra for a 10 MHz update frequency with and
without the distortion shaper are shown in Fig. 4.10(a) and (b), respectively. The
improvement in SFDR when using the proposed distortion shaping technique is
almost 12 dB, from 53.8 dB to 65.7 dB. This improvement in linearity was consistent over a signal bandwidth of several hundred kHz. Since the modulator was
designed for a signal bandwidth of 1.25 MHz and the second harmonic was the
dominating spurious tone, it was not possible to use a signal frequency higher
than 625 kHz and still have any distortion remaining within the signal band.
As can be observed from the spectrum in Fig. 4.10(b), some harmonics that were
not present in the uncompensated output, e.g., the third harmonic, are present in
the compensated output. These spurious tones are not present in the model output, so there is a discrepancy between the behavior of the model and the actual

131

Correction and Compensation of Errors

Compensated output
PSD [dBm/Hz]

PSD [dBm/Hz]

Uncompensated output
0
10
20
30
40
50
60
70
80
90
100
0

2
3
4
Frequency [MHz]

0
10
20
30
40
50
60
70
80
90
100
0

(a)
Figure 4.10

2
3
4
Frequency [MHz]

(b)

Measured output spectra from a DAC (a) without and (b) with the distortion
shaped using the proposed technique.

DAC. A suggestion for further investigation is to use a finer model with a larger
LUT than the model used in the example, perhaps also using the previous DAC
input to address the LUT as in Fig. 2.14. It is likely that this kind of model refinement is required in order to make the compensation successful for larger signal
bandwidths than that used in the example. It would also be useful to use a multicarrier signal instead of a single-tone signal to avoid having the distortion appearing outside of the signal band. If a multi-carrier signal is used, distortion appear
within the signal band due to intermodulation.
4.3.3 Yield Enhancement of Binary-Weighted DACs
One of the major contributors to the static nonlinearity of a current-steering DAC
is, as discussed in Sec. 2.2, mismatch between current sources which causes the
currents to deviate from the nominal values. The nonlinear behavior of the DAC
causes harmonic distortion in the DAC output limiting the obtainable SFDR and
SNDR. Due to the stochastic nature of the matching errors, different chips
behave differently. For example, given a certain specification of the minimum
acceptable SFDR, some DAC chips will meet the specification whereas other
chips will fail to do so. In this section, we propose a strategy for enhancing the
yield for binary-weighted DACs based on the technique for spectral shaping of
expected errors proposed in Sec. 4.3.1. The technique aims at reducing the static
nonlinearity due to mismatch. Hence, dynamic errors are not affected, which is a
limitation of the technique. In the following sections, we provide an outline of the
proposed technique and use behavioral-level simulations for evaluation. The
work presented in this section appears in [74].

132

Modulation of Expected Errors

Proposed Technique
In a binary-weighted current-steering DAC, the largest DNL error due to current
source mismatch usually appears at the middle code transition [52], as discussed
in Sec. 2.2.2. In the approach presented in this section, we utilize this fact in two
DAC models with low computational complexity that may be integrated with the
DAC. Due to the low computational complexity of the models, the cost in terms
of circuit area and power consumption is negligible. The two models are illustrated in Fig. 4.11. The DNL errors in the models are nonzero only for the middle
code transition. In the model illustrated in Fig. 4.11(a), the DNL error in the middle code transition is 2a where a is a design parameter. The corresponding DNL
error for the model in Fig. 4.11(b) is 2a . The nominal transfer characteristics
for the DAC models are plotted with dashed lines in Fig. 4.11(a) and (b). As discussed in Sec. 2.1, there are alternative ways of choosing the nominal characteristics. Commonly used choices are a straight line between the endpoints of the
actual characteristics and a best fit straight line using the least squares method
[11]. The latter is the approach used for evaluation of code domain metrics in this
thesis, as mentioned in Sec. 2.1. A possible benefit of using one of the other two
methods for selecting the nominal characteristics is that the absolute value of the
error e(n) on the average is lower than for the method used in this section.
Hence, the risk for instability in the feedback loop is reduced. However, the complexity of calculating the error is somewhat higher for these other methods. With
the used method, the modeled error is simply either a or a depending on the
value of the MSB at the input of the DAC model.
After manufacturing, the performance of the DAC chips are evaluated without
error compensation, e.g., in terms of the SFDR. The chips that meet the given
specification can be used without error compensation. The chips that do not meet
the given specification are further evaluated using the spectral shaping technique
and the two DAC models. Some of these chips will meet the specification with
the error compensation using one of the two simple DAC models. Hence, the
yield can be improved. After testing, the chips require programming to set if error
compensation is required and, in that case, which of the two models should be
used. This programming can, e.g., be performed by burning a fuse inside the
chip. The usefulness of the technique is, of course, depending on whether or not
mismatch is the dominating error source and if oversampling can be afforded.
Simulation Results
The proposed strategy is evaluated through behavioral-level MATLAB simulations on 14-bit binary-weighted DACs which include matching errors in the current sources as the only error. The matching errors in the unit current sources are
observations of uncorrelated stochastic variables with Gaussian distribution hav-

133

Correction and Compensation of Errors

Model output

Model with positive DNL

2a

0
0

middle code
Model input

max code

(a)

Model output

Model with negative DNL

2a

0
0

middle code
Model input

max code

(b)
Figure 4.11

Illustration of DAC models with nonzero DNL errors at the middle code transition. The model in (a) has a positive DNL error and the model in (b) has a negative DNL error.

ing a relative standard deviation of 2 %. Each simulation presented in this section

uses 10 3 different stochastic outcomes, where each outcome represents an individual chip. A first-order modulator is used for the simulations, i.e., the filter in
the feedback loop is a simple delay element. Block diagrams of a possible imple134

Modulation of Expected Errors

mentation of the compensation circuitry used in the simulations is shown in

Fig. 4.12. In the simulations, we only consider integer values of the error parameter a . Therefore, no additional quantization is required in the feedback loop and
the quantizer present in Fig. 4.9 is omitted in the block diagram shown in
Fig. 4.12(a). The error used in the feedback loop can be calculated with the circuitry shown in Fig. 4.12(b). The signal p/n in Fig. 4.12(b) is used to select one
of the two models, i.e., if the modeled DNL error is positive or negative.
DAC input
DAC
error
model

x(n)

z1

e(n)

(a)
a
N

MSB of DAC input

p/n

a
N

N
modeled error
(b)

Figure 4.12

Block diagrams for (a) the compensation circuit used in the simulations and (b)
the implementation of the DAC error model.

The test signal used in the simulations is a half-scale sinusoid with normalized
frequency
f sig 0.068
- ------------- ,
f N = -------OSR
fu

(4.16)

where f sig is the signal frequency, f u is the update frequency, and OSR is the
oversampling ratio. The SFDR evaluated within the signal band
f [ 0, f u ( 2 OSR ) ) is used as a performance metric in the simulations and is
for each stochastic outcome evaluated as the highest SFDR obtained from the different test cases.

135

Correction and Compensation of Errors

In Fig. 4.13, SFDR is plotted as a function of the parameter a for different values
of the OSR. The values for a = 0 are the values obtained without compensation.
The plotted values are the 90 % yield values, i.e., the SFDR requirement that is
fulfilled in 90 % of the stochastic outcomes. From the plots in Fig. 4.13, we conclude that for this particular simulation setup, a = 2 gives the best 90 % yield
value of the SFDR for considered values of the OSR. For a = 6 , the 90 % yield
value of the SFDR is practically the same as for the case a = 0 for all values of
OSR. This means that applying compensation with the parameter a set to 6
improves the performance only for a negligible number of the stochastic outcomes. A better suppression of nonlinear distortion is obtained for higher values
of the OSR. This is hardly surprising, since the magnitude of the NTF for a firstorder modulator, which is [11]
NTF(z) = 1 z 1

(4.17)

is lower within the signal band for a high OSR than for a low OSR.
The simulation results for a = 2 are analyzed further since this parameter value
yields the best 90 % yield SFDR. As an example, we consider the case for which
OSR = 8 . The yield is plotted as a function of the SFDR requirement in
Fig. 4.14. A clear improvement of the yield using the proposed method is
observed. For example, an SFDR requirement of 73 dB results in a 89.7 % yield
without the proposed technique and a 99.7 % yield with the proposed technique.
The corresponding values for a 78 dB SFDR requirement is 56.6 % and 88.4 %,
respectively.
The simulation results presented in this section are merely illustrations of the
proposed method and should, of course, be used with care. Only one test signal
has been used for each value of OSR. For better performance estimation, several
different test signals relevant for the intended application should be used. Moreover, only static errors due to current source mismatch was considered. If
dynamic errors limit the DAC performance, it is likely that the benefit of using
the proposed technique is significantly less than indicated by the simulation
results presented in this section.

136

Modulation of Expected Errors

SFDR vs. a, OSR = 16

SFDR vs. a, OSR = 8

78
SFDR [dB]

SFDR [dB]

78
76
74
72
0

76
74
72

3
a

(a)

78
SFDR [dB]

SFDR [dB]

SFDR vs. a, OSR = 2

78
76
74
72

76
74
72

3
a
(c)

Figure 4.13

(b)

SFDR vs. a, OSR = 4

3
a

3
a

(d)

The 90 % yield value of SFDR as a function of the parameter a for different

values of the OSR.

137

Correction and Compensation of Errors

Yield vs. SFDR requirement

without compensation
with compensation

Yield [%]

100
80
60
40
20
0
65

Figure 4.14

138

70

75

80
85
SFDRreq [dB]

90

95

Yield vs. SFDR requirement with and without the proposed technique for
a = 2 and OSR = 8 .

5 Test-Chip
Implementations
Four different current-steering DACs implemented in CMOS technology have
been developed in this work to enable comparison between behavioral-level simulations and measurements on actual implementations and to provide platforms
for evaluation of different techniques for linearity improvement. In this chapter,
these four DAC chips are presented in chronological order. Design and measurement issues that are common to all implementations are discussed in Sec. 5.1.
The first chip, a 14-bit DAC in a 0.35 m CMOS process, is presented in
Sec. 5.2. The same process was used for the implementation of a 14-bit PRDEM
DAC, which is presented in Sec. 5.3. The presentation includes comparisons
between measurement results and results from behavioral-level simulations. A
14-bit dual DAC (i.e., two DACs on the same chip) implemented in a 0.25 m
CMOS process is presented in Sec. 5.4. A configurable 12-bit DAC capable of
operating with different degrees of segmentation and decomposition was implemented to enable comparisons between the different architectures. The circuit
was implemented in the same 0.35 m CMOS process as the DACs in Sec. 5.2
and Sec. 5.3 and is presented in Sec. 5.5.

5.1 Design and Measurement Strategies

Some overall design strategies are shared between the current-steering DAC
implementations presented in this chapter. These design strategies are compiled
in this section. The used measurement setup is also presented.

139

Test-Chip Implementations

5.1.1 Design Strategies

In this section, we present some design strategies that are common to all the
implementations presented in this chapter. We provide a rough floorplan for the
chips, means for generation of proper signals used for driving the current
switches, and we do briefly discuss clock distribution issues.
Floorplan

digital input

A DAC floorplan is outlined in Fig. 5.1. Starting from the left we have the digital
input entering the digital encoder. The type of encoding performed by the
encoder is different for different chips. All encoders have been implemented
using the complementary static CMOS logic style [75, 76, 77] to obtain a robust
design. The bits of the encoded data are applied to latches used for synchronization and generation of control signals suitable for driving the current switches.
The current sources are placed in the block in the right part of Fig. 5.1, and the
output current wires are placed between the array and the switches.

digital
encoder

latches
&
switches

current source array

output
currents
Figure 5.1

Coarse floorplan of a DAC chip.

In other design strategies, using so called row-column decoding for thermometer

encoding, the switches and some digital logic are placed within the arrays [9].
This may cause interference between digital and analog parts, leading to a noisy

140

Design and Measurement Strategies

output signal. With the layout strategy used in the implementations presented in
this chapter, the analog and digital parts are separated. Guard rings are used
around digital as well as analog parts to reduce the substrate noise in the analog
parts due to switching in the digital parts. Separate supply voltages are used for
digital and analog circuitry to reduce the amount of simultaneous switching noise
[78] induced in the analog signals.
Switch Signal Generation
It was mentioned in Chapter 1 that, in order to avoid large glitches, it is important
that the two transistors in the differential current switch are not simultaneously
switched off. In the case of a PMOS switch, this is avoided by using control signals for the switches having nonoverlapping waveforms, as outlined in
Fig. 1.22(b). The two circuits that have been used in this work for generation of
proper control signals are shown in Fig. 5.2. The circuit in Fig. 5.2(a) consists of
a cross-coupled pair of NOR gates. For one of the outputs to be high, it is
required that both inputs to the corresponding NOR gate are low. Hence, before
an output can make a transition from low to high, the complementary output has
to be low. The inputs to the circuit in Fig. 5.2(a) are synchronized with D flip
flops.
The circuit solution shown in Fig. 5.2(b) utilizes a clocked differential cascode
voltage switch (DCVS) [75] latch. It is required that the inputs only change state
while the clock signal is high, i.e., when the clocked transistors are off. This is
ensured by adding a latch at the input which is transparent only during the high
clock phase. By proper sizing of the transistors, the crossover point between Q +
and Q can be chosen to avoid having both switch transistors simultaneously off
[38].
Clock Distribution
Uncertainties in the timing of the switching signals, known as jitter, cause distortion and noise in the DAC output. It is therefore important that the DAC is
updated at well-defined instants in time. In order to obtain that, it is required that
the clock net driving the switch signal generators is carefully designed. A schematic of a clock net with a tree structure that has been used in the implementations is shown in Fig. 5.3. To avoid skew between the branches in the tree, it is
required that the loads present at the outputs of the buffers at the same level are
well matched. Therefore, the clock trees in the implemented DACs have been
designed with equal wire lengths for all wires present at the same level.

141

Test-Chip Implementations
D

Q+

D
(a)

VDD

VDD

VDD

Q+

(b)
Figure 5.2

Circuit solutions for switch signal generation. The circuit in (a) utilizes a crosscoupled pair of NOR gates, whereas the circuit in (b) is a differential latch based
on the DCVS logic style.

5.1.2 Measurement Setup

The DAC measurements presented in the following sections have been performed
using a measurement system outlined in Fig. 5.4. The measurement system is
controlled by a personal computer (PC) running MATLAB. Input data to the
DAC is delivered from a measurement board with a low voltage differential signalling (LVDS) interface to the DAC. This measurement board is also capable of
collecting digital data for, e.g., ADC measurements. This feature is not used during the DAC measurements and is therefore omitted in Fig. 5.4. The peripheral
instruments such as power supply, clock generator, oscilloscope, and spectrum
analyzer are connected to the PC via a general purpose interface bus (GPIB). The
instruments are controlled by a GPIB controller, which in turn is controlled from
MATLAB. Measurement data can be collected from the measurement instruments over the GPIB, and further analyzed in MATLAB.

142

Design and Measurement Strategies

Figure 5.3

Tree clock network for driving the switch signal generators.

A printed circuit board (PCB) for DAC measurement is outlined in Fig. 5.5. The
output currents from the DAC are directed into off-chip load resistors. An RFtransformer is used to convert the differential signal to a single-ended signal,
denoted combined output in Fig. 5.5, that can be handled by the different measurement instruments. In order to measure the individual single-ended outputs,
the transformer must be removed.

clock
generator
measurement
board
PC

power
supply
oscilloscope

DAC

GPIB
controller

spectrum
analyzer

GPIB bus
Figure 5.4

Block diagram of measurement system.

143

Test-Chip Implementations

digital input

clock

combined
output

DAC

digital supply
Figure 5.5

single-ended
outputs

analog supply

load
resistors

RF
transformer

Outline of a PCB used for DAC measurement.

5.2 A 14-bit Segmented DAC in 0.35 m CMOS

In this section, the first DAC chip is presented. The chip is used as a reference
design for evaluation of developed models and methods for linearity improvement. A brief overview of the chip is given in Sec. 5.2.1. Measurement results are
presented in Sec. 5.2.2.
5.2.1 Chip Description
The chip was fabricated in a 0.35 m CMOS process with three metal layers. The
total chip area is 7.3 mm2, whereas the core area is 2 mm2. The DAC is segmented, where the 5 MSBs are encoded into thermometer code and the remaining
9 LSBs are binary weighted. The current sources are of PMOS type utilizing a
single cascode transistor, and the switches are of NMOS type. In retrospective, it
would have been a better choice to use PMOS switches, since the switch transistors in that case act as cascode transistors for the current sources. This change
was introduced in the later implementations. A simple strategy, further discussed
in [79], for suppressing the influence of linearly graded parameter variations is
used for the assignment of unit current sources to the different bits. The switch
signal generators are of the type shown in Fig. 5.2(a), but implemented with
NAND gates to obtain proper signals for controlling the NMOS switches. A thorough description of the design is given in [79]. A photograph of the chip is shown
in Fig. 5.6.

144

A 14-bit Segmented DAC in 0.35 m CMOS

Figure 5.6

Chip photograph of the 14-bit current-steering DAC implemented in a 0.35 m

CMOS process.

5.2.2 Measurement Results

Output spectra from differential full-scale single-tone measurements are shown
in Fig. 5.7. For the (a) and (b) figures, the update frequency is 5 MHz, and the
signal frequencies are approximately 0.6 MHz and 1.6 MHz, respectively. The
update frequency in the (c) and (d) figures is 20 MHz, and the signal frequencies
are approximately 2.5 MHz and 6.5 MHz, respectively. A common property for
all spectra in Fig. 5.7 is that the dominating spurious tone is the third harmonic,
and it can be observed that the SFDR decreases with increasing signal frequency.
Output spectra for half-scale single-tone measurements are shown Fig. 5.8. The
signal and update frequency for each sub figure is the same as in the corresponding sub figure in Fig. 5.7. Once again we find that the dominating spurious tone is
the third harmonic and that the SFDR decreases with increasing signal frequency.

145

Test-Chip Implementations
Output spectrum, f = 5 MHz.

Output spectrum, f = 5 MHz.

0
10
20
30
40
50
60
70
80
90
0

PSD [dBm/Hz]

PSD [dBm/Hz]

0.5

1
1.5
2
Frequency [Hz]

2.5

0
10
20
30
40
50
60
70
80
90
0

0.5

x 10

(a)

4
6
8
Frequency [Hz]

PSD [dBm/Hz]

(c)
Figure 5.7

x 10

Output spectrum, fu = 20 MHz.

PSD [dBm/Hz]
2

2.5

(b)

Output spectrum, fu = 20 MHz.

0
10
20
30
40
50
60
70
80
90
0

1
1.5
2
Frequency [Hz]

10
6

x 10

0
10
20
30
40
50
60
70
80
90
0

4
6
8
Frequency [Hz]

10
6

x 10

(d)

Single-tone, full-scale measurements on 14-bit DAC in 0.35 m CMOS. For (a)

and (b), the update frequency is 5 MHz, and the signal frequencies are approximately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d), the update frequency is 20 MHz, and the signal frequencies are approximately 2.55 MHz and
6.55 MHz, respectively.

The measurements were carried out for several signal frequencies, and the SFDR
was extracted from the spectra. SFDR is plotted as a function of signal frequency
in Fig. 5.9. Fig. 5.9(a) shows SFDR for the full-scale inputs, whereas Fig. 5.9(b)
shows SFDR for the half scale inputs.
The behavior of decreasing SFDR with increasing signal frequency observed in
the measurements agrees with observations made in simulations on the statespace DAC model including finite output impedance in the current sources presented in Sec. 2.3.2.

146

A 14-bit PRDEM DAC in 0.35 m CMOS

Output spectrum, f = 5 MHz.

Output spectrum, f = 5 MHz.

0
10
20
30
40
50
60
70
80
90
0

PSD [dBm/Hz]

PSD [dBm/Hz]

0.5

1
1.5
2
Frequency [Hz]

2.5

0
10
20
30
40
50
60
70
80
90
0

0.5

x 10

(a)

4
6
8
Frequency [Hz]

PSD [dBm/Hz]

(c)
Figure 5.8

x 10

Output spectrum, fu = 20 MHz.

PSD [dBm/Hz]
2

2.5

(b)

Output spectrum, fu = 20 MHz.

0
10
20
30
40
50
60
70
80
90
0

1
1.5
2
Frequency [Hz]

10
6

x 10

0
10
20
30
40
50
60
70
80
90
0

4
6
8
Frequency [Hz]

10
6

x 10

(d)

Single-tone, half-scale measurements on a 14-bit DAC in 0.35 m CMOS. For

(a) and (b), the update frequency is 5 MHz, and the signal frequencies are
approximately 0.63 MHz and 1.64 MHz, respectively. For (c) and (d), the
update frequency is 20 MHz, and the signal frequencies are approximately
2.55 MHz and 6.55 MHz, respectively.

5.3 A 14-bit PRDEM DAC in 0.35 m CMOS

DEM techniques that use randomization to reduce the harmonic distortion caused
by component mismatch were presented in Sec. 4.1. In the PRDEM technique
the degree of randomization is lower than in fully randomized DEM techniques,
e.g., FRDEM, but the hardware cost is considerably lower. The design, simulation and measurement of a 14-bit PRDEM DAC is discussed in this section.

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Test-Chip Implementations

SFDR vs. signal frequency

70

65

65
SFDR [dB]

SFDR [dB]

SFDR vs. signal frequency

70

60
55
50
45
40 5
10

fu = 5 MHz
fu = 20 MHz
6

10
Signal frequency [Hz]

60
55
50
45

10

40 5
10

fu = 5 MHz
fu = 20 MHz

(a)
Figure 5.9

10
Signal frequency [Hz]

10

(b)

SFDR vs. signal frequency for (a) full-scale signals and (b) half-scale signals.

Comparisons between measurements and simulations using models of mismatch

and dynamic errors discussed in Chapter 2 are presented, showing a good agreement between simulations and measurements.
5.3.1 Implementation
The PRDEM chip is designed with four layers of switching. The control signals
for the switches are generated off-chip to allow flexibility. The switching tree is
terminated with DAC banks consisting of one 1-bit DAC and one 10-bit DAC, as
was discussed in Sec. 4.1.2. The current sources and the current switches are both
of PMOS type, and no cascodes have been used in the current sources. A description of the design strategy used is given in [80]. A chip photograph of the
PRDEM DAC is shown in Fig. 5.10. The core area of the chip is approximately
6.3 mm2.
5.3.2 Simulations and Comparison with Measurements
Comparisons between measurements and simulations of the PRDEM DAC are
presented in [81] and [82]. This section is a summary of these publications.
Simulation Setup and Results
In the simulations, a Gaussian distributed error current with a standard deviation
of approximately 10 % has been added to each unit current source. This is a
rather large value but it includes all static errors in the DAC, e.g., mismatch
between current sources, mismatch in biasing, gain errors between the DAC
banks etc. The input is a full scale sinusoid with frequency f sig 1.25 MHz and
update frequency f u = 10 MHz . The single-ended output, terminated over
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A 14-bit PRDEM DAC in 0.35 m CMOS

DAC bank

Figure 5.10

Chip photography of current-steering PRDEM DAC.

50 , is examined. The parameters used for the state-space model are given in
Table 5.1. The output without randomization is shown in Fig. 5.11(a). The SFDR
(59.6 dB) is determined by the third harmonic. When introducing switching in
the first layer (Fig. 5.11(b)) the SFDR is increased to 67.8 dB, an improvement of
8.2 dB corresponding to approximately one effective bit, to the cost of a somewhat higher noise floor. The SFDR is now limited by the second harmonic. When
introducing switching in all four layers (Fig. 5.11(c)) we can see some small differences compared with Fig. 5.11(b) but the SFDR remains the same, hence we
do not gain any SFDR performance by having more than one switching layer.
This can be explained by observing the second harmonic in Fig. 5.11(a), (b) and
(c). The second harmonic is almost unaffected by the randomization, because it
arises from dynamic errors in the DAC and as soon as the third harmonic, arising
from mismatch, is suppressed below the second harmonic nothing is gained in
SFDR performance by using DEM.

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DAC model parameter

Value

Unit current (nominal)

1.22 A

Output resistance (unit current source)

1 G

Output capacitance (unit current source)

10 fF

Switch resistance

200

Load resistance

50

Load capacitance

100 pF

Table 5.1 DAC model parameters used in the simulations.

Simulated Spectrum Without DEM
0
10

SFDR = 59.6 dB
20

PSD [dB/Hz]

30
40
50
60
70
80
90
100
0

2
3
Frequency [MHz]

(a)
Simulated With 1 Layer DEM

Simulated With 4 Layer DEM

10

10

30

30

40
50
60

40
50
60

70

70

80

80

90

90

100
0

100
0

2
3
Frequency [MHz]

(b)
Figure 5.11

150

SFDR = 68.1 dB
20

PSD [dB/Hz]

PSD [dB/Hz]

SFDR = 67.8 dB
20

2
3
Frequency [MHz]

(c)

Simulated spectra, 10 MHz update frequency, (a) without randomization, with

(b) one switching layer and (c) four layer switching.

A 14-bit PRDEM DAC in 0.35 m CMOS

Measurement Results
To enable comparisons between measurements and simulations, the implemented
DAC is measured with the update frequency f u = 10 MHz that was used for the
simulations. Fig. 5.12(a) and (b) show the measured output spectra without randomization and with switching in one layer, respectively. The SFDR is increased
from 60.7 to 67.3 dB when one layer is switched, an improvement of 6.6 dB
which could be expected from the simulation results. When all four layers are
switched, which is the case for the spectrum shown in Fig. 5.12(c), the improvement in SFDR compared with switching in only one layer is negligible.
Measured Spectrum Without DEM
0
10

SFDR = 60.7 dB
20

PSD [dB/Hz]

30
40
50
60
70
80
90
100

0.5

1.5

2
2.5
3
Frequency [MHz]

3.5

4.5

(a)
Measured With 1 Layer DEM

Measured With 4 Layer DEM

10

10

SFDR = 68 dB
20

30

30
PSD [dB/Hz]

PSD [dB/Hz]

SFDR = 67.3 dB
20

40
50
60

40
50
60

70

70

80

80

90

90

100

100

0.5

1.5

2
2.5
3
Frequency [MHz]

3.5

4.5

(b)
Figure 5.12

0.5

1.5

2
2.5
3
Frequency [MHz]

3.5

4.5

(c)

Measured spectra, 10 MHz update frequency, (a) without randomization, (b)

with one switching layer, and (c) with four layer switching.

Comparison of SFDR performance

To see how well the model works for different update frequencies, the simulated
results were compared with measurement results from the implemented PRDEM
DAC. The update frequency is varied while the ratio between signal frequency

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and update frequency, f sig f u 1 8 , is held constant. The simulated and measured SFDR without randomization are compared in Fig. 5.13(a). The same comparison with switching in all four layers is shown in Fig. 5.13(b). From
Fig. 5.13(a) and Fig. 5.13(b) we find that the simulated and measured results are
similar, which indicates that the models used for the simulation are able to
describe the behavior of the implemented circuit.
Simulated and measured SFDR without DEM

Simulated and measured SFDR with DEM

65
Measured
Simulated

Measured
Simulated

74

12

71
62

10

56

11

65
62

10

59
56

53

Number of bits

59

SFDR [dB]

Number of bits

SFDR [dB]

68

53
1

5
10
Sampling Frequency [MHz]

30

5
10
Sampling Frequency [MHz]

(a)
Figure 5.13

30

(b)

Simulated and measured SFDR performance for different update frequencies

with (a) no randomization, and (b) switching in all layers.

5.4 A 14-bit Dual DAC in 0.25 m CMOS

Design and measurement results of a 14-bit dual DAC implemented in a 0.25 m
CMOS process is presented in this section. The term dual indicates that two
DACs are implemented on the same chip. The material in this section was presented in [83].
5.4.1 Architecture and Implementation
The DAC has a doubly segmented architecture where both the seven LSBs and
the seven MSBs are converted into thermometer code controlling the current
switches. Single PMOS transistor current sources and PMOS current switches
are used. The circuit in Fig. 5.2(b) is used for generation of the switching signals.
Distributed biasing (see Sec. 4.2) is used to obtain good matching properties. The
current source arrays are divided into eight sub arrays with individual local bias
circuits. The bias currents for the local bias circuits are generated with a global
bias circuit consisting of a multiple-output cascoded NMOS current mirror,
which is shared between the two DACs to obtain good mutual matching. A photograph and a layout plot of the dual DAC chip are shown in Fig. 5.14(a) and (b),
respectively.

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A 14-bit Dual DAC in 0.25 m CMOS

(a)

(b)
Figure 5.14

(a) Chip photograph and (b) layout plot of the 14-bit dual DAC implemented in
a 0.25 m CMOS process.

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Test-Chip Implementations

Current source arrays and binary-to-thermometer encoders are examples of regular circuit structures. The regularity is utilized in this implementation for automated design. Some blocks, like a current source, a switch and logic gates, are
laid out manually, whereas practically all other parts of the design are based on
scripts for placement, routing, and for generation of circuit schematics. This simplifies the design work and reduces the design time compared with a completely
manual design. Similar approaches have been used by others [84]. There is a
trend of increased use of design automation for analog and mixed signal circuits
[85], which will likely continue in the future. A further development of the scriptbased approach using parameterized cells is used for the DAC presented in
Sec. 5.5 and discussed in Sec. 5.5.2.
5.4.2 Measurement Results
The SFDR for full-scale signals is plotted as a function of signal frequency in
Fig. 5.15. For the cases when the update frequency is 5 and 10 MHz, SFDR is
higher than 73 dB for a range of signal frequencies up to 3 MHz. This can be
regarded as a good result, even if an SFDR of at least 86 dB is required for 14
effective bits. The good static linearity obtained for this circuit indicates that the
use of distributed biasing efficiently suppresses the influence of linearly graded
matching errors. The linearity is deteriorated when the update frequency is
increased to 25 MHz. This behavior is not yet explained, and requires further
study.
SFDR vs. signal frequency
80

SFDR [dB]

75
70
65
60
55
50

fu = 5 MHz
fu = 10 MHz
fu = 25 MHz
6

10

10
Signal frequency [Hz]

Figure 5.15

Measured SFDR as a function of signal frequency.

A more adequate measure for DMT applications is the MTPR, which is defined
in Sec. 1.3.2. For this purpose, an ADSL-like input is used, which is quantized
values of
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A 12-bit Configurable DAC in 0.35 m CMOS

255

x ( n ) = x dc + K

j=1

j
a j sin 2n ------------f- + j ,
fu

(5.1)

where a j = 0 for j = 142 and a j = 1 otherwise. The frequency spacing is

f = 4.3125 kHz and the update frequency is f u = 10 MHz . The phases j
are randomly selected and the scaling factor K and the dc level x dc are chosen
such that the whole input range of the DAC ( [ 0, 2 14 1 ] ) is used. The measured
signal spectrum is shown in Fig. 5.16. The MTPR, limited by the noise floor, is
approximately 71 dB. This is a good result, even compared with commercial
DACs for DSL applications available at the time the chip was designed (2001),
e.g., AD9764 [47] from Analog Devices, Inc.

missing tone

Figure 5.16

MTPR measurement result.

5.5 A 12-bit Configurable DAC in 0.35 m CMOS

Different strategies for encoding the digital input to form the control word were
discussed in Chapter 3 together with behavioral-level simulation results. The
decomposed DAC architecture was proposed as an alternative to the commonly
used segmented architecture for a more efficient reduction of the number of
switched unit current sources in the transition between two consecutive inputs. In
order to enable further comparisons between the decomposed and segmented

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architectures, a 12-bit configurable DAC capable of operating with different

degrees of segmentation and decomposition has been implemented. The technology used for the implementation is the same 0.35 m CMOS technology that was
used in the implementations presented in Sec. 5.2 and Sec. 5.3.
5.5.1 Architecture
The analog part of the chip consists of a number of unit current sources (single
PMOS transistors) that are grouped (i.e., connected in parallel to a common
switch) to form the weighted current sources required for 4-layer decomposition.
By proper selection of control signals, these weighted current sources can in turn
be grouped to form the different weighted current sources required for a binaryweighted converter, 1 to 4 layers of decomposition and 2 to 5 bits of segmentation. In Fig. 5.17(a)-(e), these different groupings are illustrated for a simpler
case, namely a 4-bit DAC operating in either binary-weighted, 2-bit segmented,
3-bit segmented, 1-layer decomposed, or 2-layer decomposed conversion mode.
The digital part of the chip consists of a configurable encoder, which is preceded
by a register used for synchronization of the input bits. In the interface between
the encoder and the switches, there are a number of clocked switch drivers (one
for each switch) of the type outlined in Fig. 5.2(b).
5.5.2 Pcell-Based Design Approach
Design methodologies for digital circuits have evolved over the years. With the
help of automated design flows, including, e.g., logic synthesis and automatic
placement and routing, the design times have been decreased significantly compared with full-custom design. Further, design automation simplifies reuse of
components; if there exist a description of a component in a high-level hardware
description language, it is simple to incorporate that piece of code in other
designs than the component was initially developed for.
Design automation for analog and mixed-signal circuits is not as well developed
as for digital circuits, even though the use of tools for automatic layout generation and device size optimization is increasing [85]. Component reuse can be difficult, since, e.g., specifications on amplifier gains and bandwidths are different
in different applications. Transistor sizing and layout strategies are still, to a large
extent, based on designer experience rather than the use of systematic methods.
Analog and mixed-signal circuits with regular circuit topologies, containing, e.g.,
arrays of equally sized capacitors or transistors, are especially well suited for
automatic layout generation [86]. An example of such a regular circuit, that has
been subject to design automation [86, 87], is the current-steering DAC.

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A 12-bit Configurable DAC in 0.35 m CMOS

(a)

(b)

(d)
Figure 5.17

(c)

(e)

Connection of the unit current sources in a 4-bit DAC for (a) binary-weighted,
(b) 2-bit segmented, (c) 3-bit segmented, (d) 1-layer decomposed, and (e) 2layer decomposed conversion mode.

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Since design automation is not as well developed for analog circuits as for digital
circuits, designers are often forced to do full-custom designs. In order to obtain
reasonably short design times, it is important to use efficient design methodologies. In this section, we discuss a design methodology based on parameterized
cells for efficient layout generation. The design methodology has been used in
the design flow for the configurable DAC. This methodology is a further development of the script-based approach used for the design of the DAC presented in
Sec. 5.4. The material presented in this section has previously been published in
[88].
Pcells
In this work, we have used the Cadence Virtuoso design environment, which has
built-in support for creation of parameterized cells, or Pcells with Cadence notation, using the SKILL programming language [89]. Often, some Pcells are provided by the process manufacturer in the design kit associated with a specific
process. These Pcells are usually simple primitive devices, e.g., transistors, resistors, or parallel-plate capacitors. Typical parameters for a CMOS transistor are
length, width, number of fingers and Boolean parameters stating whether or not
drain/source contacts should be included. However, Pcells can be used for more
complex structures than primitive devices. For example, in deep sub-micron
CMOS processes, the parasitics in interconnects have a large impact on the circuit performance, and the behavior of a circuit may differ considerably from simulation results from the circuit schematic. Therefore, parasitics extracted from the
circuit layout are required for obtaining accurate simulation results. In [90],
SKILL Pcells were used for fast layout generation of operational amplifiers,
making it possible to include extracted parasitics in an amplifier optimization
process.
Pcells are used hierarchically in the design of the configurable DAC. Each sub
block is generalized in order to allow simple modification of the block parameters. For example, if the width or the length of a transistor in an array is changed,
this also affects the placement and the routing, which should be handled by the
Pcell. This generalization of the circuit layout results in an increased design time,
compared with a manual layout with fixed transistor sizes, etc. However, it is usually required to iterate the circuit layout during the design process. Since this normally is the case, the Pcell approach with generalized building blocks is
favorable, since the regeneration of the layout is almost instantaneous. Further,
the use of general Pcells enables simpler design reuse, since the circuits can be
modified to match different specifications by changing the parameter values.

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A 12-bit Configurable DAC in 0.35 m CMOS

There are, however, cases in which this approach is not feasible. For example,
when complex routing with good wire matching is required, a specialized tool
that optimizes the routing is preferred [86].
The structure of the SKILL code for a Pcell is shown in Fig. 5.18. The code starts
with a declaration of the Pcell, containing the name and location of the circuit in
the library hierarchy, followed by a list of parameters. The SKILL code defining
the placement of sub cells, routing of metal, poly, and diffusion layers, etc., is
placed after the parameter list. Even though there is an immense amount of various SKILL commands, only a few commands, e.g., for instantiation of sub cells
and generation of paths and rectangles, are required for a successful design with
Pcells.

pcDefinePCell((library name, cell name, view name)

list of parameters and default values
let((declaration of local variables)
SKILL code for layout generation
)
)

Figure 5.18

Structure of the SKILL code for a Pcell. Words in regular-weight font are
SKILL commands and words in bold font describe SKILL code to be inserted.

Analog Building Blocks

In this section, we describe the Pcells for the analog building blocks. One of the
basic building blocks is the unit current source. The unit current source is implemented with a single PMOS transistor. There are three basic configurations for
the unit current source Pcell; normal configuration, in which the output is connected to a switch, bias configuration, in which the transistor is diode connected
to serve as input transistor in a current mirror, and dummy configuration, in
which the drain and source of the transistor are shorted and connected to the supply voltage. The configuration of the unit current source is controlled by Boolean
parameters. Other parameters used are real-valued parameters for the transistors
width and length. Plots of unit current sources in the different configurations are
shown in Fig. 5.19.

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Test-Chip Implementations

(a)

(b)

(c)
Figure 5.19

Unit current source in (a) normal, (b) bias, and (c) dummy configuration. In (a)
and (b), the drains are connected to a routing channel above the transistor.

A number of unit current sources are connected in parallel to form weighted current sources. A number of binary-weighted and 1-bit sub DACs are required in
the configurable DAC. Here, we have chosen to design the sub DACs from a
number of cells denoted current cells. Each current cell consists of two current
sources with different weights. Further, the current cells consist of a number of
unit sources in dummy and bias configuration. Input parameters to the current
cell are width and length for the unit current sources, the number of rows and columns of unit current sources, the number of unit current sources in bias configuration, and the widths of the metal wires that connects the current sources to the
outputs. The current cell is illustrated in Fig. 5.20, where the Pcell has been
instantiated with different parameter values for the number of rows.

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A 12-bit Configurable DAC in 0.35 m CMOS

(a)

bias
wire

output
wires

(b)
Figure 5.20

The current cell Pcell consisting of 4 diode-connected transistors and current

sources with weights 8 and 4 implemented with (a) two and (b) four rows of
unit current sources.

Another basic building block in the current-steering DAC is the current switch.
The switch is implemented with two PMOS transistors with the sources connected to a common node, i.e., the output node of a weighted current source, and
the drains connected to the differential outputs of the DAC. Each switch is isolated with a guard ring to suppress the switching noise from the digital parts.
Parameters for the switch Pcell are lengths and widths for the switch transistors
and the height of the cell, which is required to determine the positions of the
guards. The switch is illustrated in Fig. 5.21, where the Pcell has been instantiated with different parameter values.
Because the configurable DAC should be able to operate in a 4-layer decomposed
mode, 16 binary-weighted and 15 1-bit DACs are required. Therefore, a sub DAC
Pcell containing one binary-weighted and one 1-bit DAC was constructed. The
Pcell consists of a number of instantiations of the current cell Pcell with different
parameter values. The current cells are placed on top of each other, and a guard
ring is drawn around the resulting current source array. The required number of
current switches are placed to the left of the current source array. The Pcell is
illustrated in Fig. 5.22(a) and (b), where a sub DAC with an 8-bit binaryweighted DAC is implemented with 4 and 8 rows of unit current sources per current cell, respectively. Other parameters in the Pcell are, e.g., transistor widths
and lengths, wire widths, number of bits in the binary-weighted DAC, and number of columns in the current source array.
Configurable Encoder
A configurable encoder is required to allow the DAC to operate in the different
modes. Since the encoder is a digital block, it could have been implemented
using an automated design flow including logic synthesis and automatic place161

Test-Chip Implementations

(a)

output wires

switch transistors

guards

(b)

(c)
Figure 5.21

The switch Pcell instantiated with parameter values (a) transistor length
l = 0.7 m , transistor width w = 5 m , and cell height h = 10 m , (b)
l = 0.7 m , w = 5 m , and h = 15 m , and (c) l = 0.7 m ,
w = 10 m , and h = 10 m . The widths of the output wires are 10 m .

ment and routing. However, the encoder is easy to implement using full-custom
design. Therefore, a Pcell-based approach was used also for the encoder. A few
simple logic gates were required, and these were laid out manually. The encoder
is implemented as a tree of 1-layer encoders, which in turn are implemented as
Pcells, where the main input parameter is the number of input bits. The whole
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A 12-bit Configurable DAC in 0.35 m CMOS

(a)

(b)
Figure 5.22

Instantiations of the Pcell for a sub DAC containing one binary-weighted DAC
and one 1-bit DAC. Each current cell in the sub DACs occupies (a) 4 rows and
(b) 8 rows. In both (a) and (b), the number of input bits to the binary-weighted
DAC is 8.

encoder itself is also a Pcell, where the main parameters are the number of input
bits and the number of layers. The Pcell is illustrated in Fig. 5.23. In Fig. 5.23(a),
the Pcell is instantiated with 5 input bits and 2 layers, and in Fig. 5.23(b), the
Pcell is instantiated with 12 input bits and 4 layers. The encoder shown in
Fig. 5.23(b) is the one that was used in the chip that was fabricated. It has 8 control signals, two for each layer, to control the DACs mode of operation. These
control signals are denoted configuration bits in Fig. 5.23(a).
Configurable DAC
The chip photograph of the configurable 12-bit DAC is shown in Fig. 5.24. It is
composed of 16 sub DACs, each containing one 8-bit DAC and one 1-bit DAC,
and the encoder shown in Fig. 5.23(b). Since only 15 1-bit DACs are required,
the output of one of the 1-bit DACs is connected to the supply voltage. Each of
the sub DACs has its own bias circuit, which is driven by a bias current generated
in a global bias circuit. In the interface between the encoder and the sub DACs,
there are a number of switch drivers of the type outlined in Fig. 5.2(b), that generate proper differential signals for controlling the current switches. The manual

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Test-Chip Implementations

configuration bits

configuration bits

input

output
(a)

(b)
Figure 5.23

Layout of a configurable encoder with (a) 5 input bits and 2 layers and (b) 12
input bits and 4 layers.

layout work in the assembly of the chip is limited to the pad frame, routing of
wires from the core to the pad frame, routing of the power supply and ground
wires from the pad frame to the core, and some minor inter-cell routing. The core
area and the total chip area are approximately 2.5 mm2 and 6.7 mm2, respectively.
Due to the extensive use of Pcells, it is easy to reuse the blocks. For example, if
measurements show that the distortion caused by transistor mismatch is too large,
and that the area of the unit current source should be made larger, a modified layout of the DAC core can be generated in a few seconds by changing the parameter that needs to be modified. Further, since the blocks were parameterized, the

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A 12-bit Configurable DAC in 0.35 m CMOS

Figure 5.24

Chip photograph of the configurable 12-bit DAC.

layout of the circuit could be started before the transistor sizing was finished.
Hence, using the design approach discussed in this section enables parallelization
of the design flow, which has a potential of reducing the overall design time.
5.5.3 Simulation Results
In this section, we present simulation results from transistor-level transient analyses of the test chip. These simulation results were first presented in [91]. The circuit has been simulated with a ramp input in binary-weighted mode, 5-bit
segmented mode, and 4-layer decomposed mode with 50 load resistors and
10 MHz update frequency. The purpose of the simulations was only to verify the
functionality of the circuit. For example, parasitics in wires and packages were

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Test-Chip Implementations

not included, and transistor mismatch was not taken into account. For accurate
performance estimation, these parameters should be included and more realistic
test vectors, e.g., multi-tone signals, should be used. However, the simulations
are time consuming (each ramp takes more than three days to simulate). Therefore, measurements are used to evaluate the performance of the circuit in the different modes of operation. Nevertheless, the simulated ramp responses give an
indication of the differences in glitch behavior between the different modes.
The simulated ramp responses for binary-weighted mode, 5-bit segmented mode,
and 4-layer decomposed mode are shown in Fig. 5.25(a), (b), and (c), respectively. The magnitudes of the glitches shown in these plots are quite large. However, if parasitic capacitances had been included in the simulations, the outputs
would have been lowpass filtered and the glitch magnitudes reduced. Moreover,
image rejection filters are used in actual applications to remove the spectral
images of the signal that appears at multiples of the update frequency. These filters also reduce the glitch magnitudes. The relative differences between the different modes of operation shown in Fig. 5.25 is, however, preserved. From the
plots in Fig. 5.25, it is obvious that the binary-weighted mode suffers from larger
glitches than the segmented and decomposed modes. Enlarged plots around the
middle code transition are included in Fig. 5.25(b) and (c) in order to compare
the glitch behavior between segmented and decomposed modes. The glitch in the
middle code transition is much smaller in the decomposed mode than in the segmented mode. This is not only true for this particular code transition, but also for
14 additional code transitions. For the remaining code transitions in the ramp, the
two modes have the same number of switched unit current sources, and, hence,
approximately the same glitch behavior.
5.5.4 Measurement Results
In this section, we present measurement results and compare the different modes
of operation. The input signal used in the measurements is a dual-tone signal,
where both tones have an amplitude of 2 7 . The signal frequencies are
f 1 = 0.98 MHz and f 2 = 1.11 MHz , and the clock frequency is 10 MHz. This
input signal has most of its samples close to the middle of the DAC input range.
Hence, it belongs to a group of signals for which the behavioral-level simulations
presented in Sec. 3.6 indicate that the decomposed architecture is well suited.
The measured output spectrum from one of the fabricated test chips operating in
binary-weighted mode is shown in Fig. 5.26. Severe nonlinear distortion is
observed for this mode of operation.
The same chip was measured in the different available segmented modes, and the
results are plotted in Fig. 5.27. Applying segmentation clearly improves the linearity compared with the binary-weighted case. An interesting behavior is

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A 12-bit Configurable DAC in 0.35 m CMOS

Binary-weighted DAC
Output voltage [V]

0.5

0
0.1

0.2
0.3
Time [ms]

0.4

(a)
4-layer decomposed DAC

Output voltage [V]

Output voltage [V]

5-bit segmented DAC

0.5
0.5
0.49

0.206

0.1

0.5
0.5
0.49

0.208

0.2
0.3
Time [ms]

0.4

0.206

0.1

0.2
0.3
Time [ms]

(b)
Figure 5.25

0.208

0.4

(c)

Simulated single-ended ramp responses for the test chip in (a) binary-weighted,
(b) 5-bit segmented, and (c) 4-layer decomposed modes. The update frequency
is 10 MHz.

PSD, dBm/Hz

Binary weighted

Figure 5.26

20
30
40
50
60
70
80
90
0

2
3
4
Frequency, MHz

Measured dual-tone output spectrum for one of the DACs in binary-weighted

mode.

167

Test-Chip Implementations

observed from Fig. 5.27. For this particular chip, the nonlinear distortion is actually worse in the 4-bit segmented mode than in the 3-bit segmented mode. This is
due to the stochastic nature of the matching errors. For this particular outcome
(i.e., chip), the matching errors gave less distortion in the 3-bit segmented mode
than in the 4-bit segmented mode. Seen over a large number of chips, however, 4bit segmentation yields less distortion than 3-bit segmentation.
3-bit segmented

PSD, dBm/Hz

PSD, dBm/Hz

2-bit segmented
20
30
40
50
60
70
80
90
0

2
3
4
Frequency, MHz

20
30
40
50
60
70
80
90
0

(a)

2
3
4
Frequency, MHz

PSD, dBm/Hz

(c)
Figure 5.27

5-bit segmented

PSD, dBm/Hz
1

(b)

4-bit segmented
20
30
40
50
60
70
80
90
0

2
3
4
Frequency, MHz

20
30
40
50
60
70
80
90
0

2
3
4
Frequency, MHz

(d)

Measured dual-tone output spectra for one of the DACs in (a) 2-bit segmented,
(b) 3-bit segmented, (c) 4-bit segmented, and (d) 5-bit segmented mode.

The same chip was also measured in the different available decomposed modes.
The resulting output spectra are shown in Fig. 5.28. Using decomposition also
shows a clear improvement in linearity compared with the binary-weighted case.
For the decomposed mode, we find that the distortion is actually worse for the 2layer decomposed mode than for the 1-layer decomposed mode. This is similar to
the nonintuitive behavior for the segmented mode and is due to the same statistical variation. Seen over a large number of chips, 2-layer decomposition results in

168

A 12-bit Configurable DAC in 0.35 m CMOS

less nonlinear distortion than 1-layer decomposition. It is interesting to compare

the results in the segmented modes with the corresponding results in the decomposed modes. As in Chapter 3, we compare M -layer decomposition with
( M + 1 )-bit segmentation. Comparing Fig. 5.27 and Fig. 5.28 we find that,
except for the case M = 2 , the linearity in the decomposed mode is better than
that for the segmented mode. Specifically, the spurious tones at frequencies
2 f 1 f 2 and 2 f 2 f 1 , caused by third order intermodulation, are hidden below
the noise floor for the decomposed mode.
2-layer decomposed

PSD, dBm/Hz

PSD, dBm/Hz

1-layer decomposed
20
30
40
50
60
70
80
90
0

2
3
4
Frequency, MHz

20
30
40
50
60
70
80
90
0

(a)

2
3
4
Frequency, MHz

PSD, dBm/Hz

(c)
Figure 5.28

4-layer decomposed

PSD, dBm/Hz
1

(b)

3-layer decomposed
20
30
40
50
60
70
80
90
0

2
3
4
Frequency, MHz

20
30
40
50
60
70
80
90
0

2
3
4
Frequency, MHz

(d)

Measured dual-tone output spectra for one of the DACs in (a) l-layer decomposed, (b) 2-layer decomposed, (c) 3-layer decomposed, and (d) 4-layer decomposed modes.

The measured SNDR is limited by the noise floor of the spectrum analyzer, so the
SNDR does not vary more than a few dB between the different modes. Therefore,
we instead use the signal-to-distortion ratio (SDR) as a performance metric. We
define SDR as

169

Test-Chip Implementations

P signal
SDR = ---------------,
Pd

(5.2)

where P signal is the signal power and P d is the total power for all spurious tones
visible above the noise floor of 85 dBm/Hz. SDR values for M -layer decomposed and ( M + 1 )-bit segmented modes are plotted as a function of M in
Fig. 5.29. The plotted SDR values are the average values over three different
chips (the averages are computed in linear scale, but plotted in dB scale). Naturally, a more relevant measure than the average SDR would be to use a value of
an SDR specification that results in a specific (e.g., 90 %) yield, as was the case
for the behavioral-level simulations presented in Chapter 3. However, only three
different chips have been characterized, which is too small a number to allow
reliable yield calculations. From Fig. 5.29, it can be concluded that the decomposed architecture suffers from less nonlinear distortion than the segmented
architecture, especially for small values of M . Qualitatively, this agrees well with
the behavioral-level simulation results presented in Chapter 3. The measurement
results indicate that the results from the behavioral-level simulations presented in
Chapter 3 are reasonable and that the decomposed DAC architecture is a viable
alternative to the traditional segmented architecture. As mentioned in Chapter 3,
designers should be aware of the different hardware complexities for the different
architectures and take this into account when choosing the proper architecture for
specific cases.
Dual-tone signal-to-distortion ratio
50
48
SDR [dB]

46
44
42
40
38

M-layer decomposed
(M+1)-bit segmented

36
34
0
Figure 5.29

170

2
M

Measured dual-tone signal-to-distortion ratio for M -layer decomposed and

( M + 1 )-bit segmented modes plotted as a function of M .

6 Conclusions
Selected aspects related to modeling, error correction, and implementation of
current-steering DACs implemented in CMOS technology were discussed in the
work presented in this thesis. Target applications considered were telecommunication applications such as the different DSL applications. As outlined in the thesis, the requirements on linearity for components in the transmit and receive
paths are hard in such applications. Therefore, the linearity properties of currentsteering DACs were of special importance in the presented work.
Behavioral-level models of different nonideal properties of a current-steering
DAC were discussed. Two different models with different computational complexity of signal-dependent settling errors due to finite output impedance in current sources were developed. Another dynamic error modeled in this work was
glitches due to asymmetry in the settling behavior when switching on and off a
current source. Further, a method for estimating the behavior of the modeled
glitches in the frequency domain was developed. Well-known models of static
errors, such as matching errors and the static nonlinearity caused by finite output
resistance in the current sources were also discussed.
The encoding used for the digital control word in a current-steering DAC has a
large influence on the circuit performance, e.g., in terms static linearity and
glitches. Two DAC architectures were developed related to this aspect. These
were denoted the decomposed and partially decomposed architectures and utilized encoding strategies aiming at a high circuit performance by avoiding unnecessary switching of current sources. The developed architectures were compared
with the well-known binary-weighted and segmented architectures using behavioral-level simulations. The number of bits in the control word was used as a simple measure of hardware complexity in the presented comparisons. Using this
measure, the simulation results indicated that the decomposed and partially

171

Conclusions

decomposed architectures yield similar or better performance than the segmented

architecture for the same hardware complexity for the signals used in the simulations. The partially decomposed and the decomposed architectures are especially
well suited in applications where most of the samples in the input lie around the
middle of the DAC input range.
Different techniques for improving the linearity of current-steering DACs were
discussed. DEM techniques use randomization to reduce the nonlinear distortion
due to matching errors. Through the use of DEM, the error in the DAC output is
given more noise-like properties and the error power is spread over a large frequency range. In combination with oversampling, DEM enables an improvement
of the overall SNDR compared with a DAC utilizing a static mapping of the input
to the control word. Well-known DEM techniques were overviewed in the thesis
and a DEM technique for the decomposed architecture was developed.
Distributed biasing is a well-known strategy for limiting the influence of parameter gradients which was used for two of the DACs implemented in this work. This
biasing strategy was also outlined in the thesis.
In DACs utilizing modulation, the quantization error is used in a feedback
loop in order to spectrally shape the quantization noise and reduce the power of
the quantization noise within the signal band. The same principle was used in a
technique proposed for spectral shaping of nonlinear distortion caused by nonideal properties of a DAC. A DAC model was used to estimate the error at the
DAC output, which in turn was used in a feedback loop in order to spectrally
shape the resulting nonlinear distortion. Two different examples where the proposed technique was used were presented. In the first example, one of the models
developed for dynamic errors caused by finite output impedance in the current
sources was used to obtain spectral shaping of the resulting nonlinear distortion.
In the second example, two simple models of matching errors with low computational complexity that could be integrated on the same chip as the DAC at a negligible cost were utilized for enhancing the yield of binary-weighted DACs.
Four current-steering DAC chips were implemented that enabled comparisons
between behavioral-level simulation results using developed models and measurement results and provided platforms for evaluation of different techniques
aiming at improving the linearity. The first circuit presented was a 14-bit DAC
with 5-bit segmentation. Measurement results from the circuit showed good
agreement with simulation results obtained with DAC models that included the
finite output impedance in the current sources. The second chip was a 14-bit
PRDEM DAC. Measurement results from this circuit were compared with simulation results. The model used in the simulation included both static errors due to
mismatch and dynamic errors due to finite output impedance in the current

172

sources. The simulation results and the measurement results showed good agreement and illustrated the limited efficiency of DEM techniques for situations
where dynamic errors dominate. The third circuit presented was a 14-bit dual
DAC with a doubly segmented architecture. The use of distributed biasing efficiently suppressed the influence of linearly graded matching errors and a good
static linearity was obtained. The last chip presented was a 12-bit configurable
DAC capable of operating with different degrees of segmentation and decomposition. This circuit enabled comparisons between the segmented and decomposed
architectures. Measurements performed on the configurable DAC showed the
same trends as the behavioral-level simulations presented earlier in the thesis and
indicated that the decomposed architecture is a viable alternative to the traditional segmented architecture.

173

Conclusions

174

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