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VDD
PMOS
SOURCE
DRAIN I/O
NMOS
VSS
VDD
VSS
INPUT
BUFFER
DIGITAL
INPUT
DRIVER
GND
P-CHANNEL RON
RON ( )
N-CHANNEL RON
COMBINED RESISTANCE
OF PMOS AND
NMOS FETs.
VSOURCE (V)
www.analog.com/analogdialogue
VDD
SOURCE I/O
DRAIN I/O
VSS
VSS
Fault Type
Fault Causes
Overvoltage:
Loss of power
System malfunction
Hot-swap connects and disconnects
Power-supply sequencing issues
Miswiring
User error
Latch-Up:
ESD
Storage/assembly
PCB assembly
User operation
OVERVOLTAGE
What Is an Overvoltage Condition?
VS > VDD
FORWARD
CURRENT
FLOWS
LOAD
CURRENT
FORWARD
CURRENT
S
RS
RL
VS
GND
VSS
VDD
RL
GND
0V
0V
VSS
GND
0V
VDD = 0V
SWITCH
SIGNAL
RANGE
CLIPPING
1
GND = 0V
5V INPUT
SOURCE INPUT:
5V SINE WAVE
VS
RL
DRAIN OUTPUT:
CLIPPED SIGNAL
GND
VSS
CH2 100mV
M200s
T
36.0s
A CH1
3.00V
Figure 7. Clipping.
When no power supplies are present, the switch remains in the off
condition. The switch inputs present a high impedance, limiting
current flow that could damage the switch or downstream circuitry.
This is very useful in applications where analog signals may be
present at the switch inputs before the power is turned on, or
where the user has no control over the power supply sequence. In
the off condition, signal levels up to 16 V are blocked. Also, the
switch turns off if the analog input signal level exceeds V DD by V T.
SX
DX
OV
MONITOR
SX
DX
DIGITAL
INPUT
PS
MONITOR
INX
VDD
LATCH-UP
What Is a Latch-Up Condition?
PMOS
NMOS
NMOS
PMOS
VSS
VDD
I/O
I/O
I/O
I/O
VSS/GND
N+
P+
P+
N+
N+
P+
RW
Q1
Q2
N-WELL
RS
P SUBSTRATE
I/O
VDD
RW
Q1
(b)
Q2
RS
VSS/GND
I/O
VSS
VDD
(a)
VDD
T
R
E
N
C
H
P+
VG
I/O
P-CHANNEL
P+
VG
I/O
T
R
E
N
C
H
N+
N-CHANNEL
I/O
N+
T
R
E
N
C
H
SUBSTRATE (BACKGATE)
ICs can be damaged by the high voltages and high peak currents
generated by an ESD event. The effects of an ESD event on
an analog switch can include reduced reliability over time, the
degradation of switch performance, increased channel leakage,
or complete device failure.
ESD events can occur at any stage of the life of an IC, from
manufacturing through testing, handling, OEM user, and enduser operation. In order to evaluate an ICs robustness to various
ESD events, electrical pulse circuits modeling the following
simulated stress environments were identified: human body model
(HBM), field-induced charged device model (FICDM), and machine
model (MM).
DIGITAL INPUT
PROTECTION
VDD
ESDELECTROSTATIC DISCHARGE
What Is an Electrostatic Discharge Event?
VL
VSS
POWER SUPPLY
PROTECTION
VDD
VDD
VSS
VSS
GND
IN
GND
Conclusion
Author
APPENDIX
Analog Devices Switch/Multiplexer Protection Products:
High-Voltage Latch-Up Proof Switches
Part
Number
Max
On
Number
Analog Charge Leakage
of Switch RON Signal Injection @ 85C
Configuration Functions () Range
(pC)
(nA)
Supply Voltages
Packages
Price @ 1k
($U.S.)
ADG5212
SPST/NO
160
VSS to
V DD
0.07
0.25
CSP, SOP
2.18
ADG5213
SPST/
NO-NC
160
VSS to
V DD
0.07
0.25
CSP, SOP
2.18
ADG5236
SPST/
NO-NC
160
VSS to
V DD
0.6
0.4
CSP, SOP
2.26
ADG5412
SPST/NO
VSS to
V DD
240
CSP, SOP
2.18
ADG5413
SPST/NO-NC
VSS to
V DD
240
CSP, SOP
2.18
ADG5433
SPST/NO-NC
12.5
VSS to
V DD
130
CSP, SOP
2.15
ADG5434
SPST/NO-NC
12.5
VSS to
V DD
130
SOP
3.04
ADG5436
SPST/NO-NC
VSS to
V DD
0.6
CSP, SOP
2.26
RON
Configuration ()
Max
Analog
Signal
Range
On
Charge
On
Leakage
Injection Capacitance @ 85C
(pC)
(pF)
(nA)
Supply Voltages
Packages
Price @
1000 to
4999
($U.S.)
ADG5204
(4:1) 2
160
VSS to
V DD
0.6
30
0.5
2.26
ADG5408
(8:1) 1
14.5
VSS to
V DD
115
133
2.41
ADG5409
(4:1) 2
12.5
VSS to
V DD
115
81
2.41
ADG5404
(4:1) 1
VSS to
V DD
220
132
2.26
Configuration
Number
of Switch
Functions
ADG4612
SPST/NO
ADG4613
SPT/NO-NC
Max
Analog
Signal
Range
5.5 V to
V DD
5.5 V to
V DD
Fault
Response
Time (ns)
Fault
Recovery
Time (s)
3 dB
Bandwidth
(MHz)
Packages
Price @ 1k
($U.S.)
295
1.2
293
SOP
1.84
295
1.2
294
CSP, SOP
1.84
RON
()
ADG438F (8:1) 1
400
ADG439F
(4:1) 2
400
ADG508F (8:1) 1
300
ADG509F
(4:1) 2
ADG528F
(8:1) 1
Part
Number
tTRANSITION
(ns)
Supply
Voltages (V)
Packages
Price @
1000 to
4999
($U.S.)
170
Dual (15 V)
2.6
DIP, SOIC
3.68
170
Dual (15 V)
2.6
DIP, SOIC
3.68
VSS + 3 V to
V DD 1.5 V
200
DIP, SOIC
3.31
300
VSS + 3 V to
V DD 1.5 V
200
DIP, SOIC
3.31
300
VSS + 3 V to
V DD 1.5 V
200
DIP, LCC
3.91
Max Analog
Signal Range
VSS + 1.2 V to
V DD 0.8 V
VSS + 1.2 V to
V DD 0.8 V
Configuration
Channel Protector
Channel Protector
Number
of Switch
Functions
1
8
RON
()
80
62
Max Positive
Supply (V)
20
20
Max Negative
Supply (V)
20
20
Packages
SOIC, SOT
SOIC, SOP
Price @ 1k
($U.S.)
0.84
2.40