ISSCC 2004 / SESSION 17 / MEMS AND SENSORS / 17.

A Very Low Power CMOS Mixed-Signal IC

for Implantable Pacemaker Applications

two CA is used to reduce area and power. Bottom-plate-sampling is

used to minimize input offset variations. The current consumption is
measured at ~150nA @ 1KS/s.

Louis S Y Wong, S. Hossain, A. Ta, L. Weaver, C. Shaquer,

A. Walker, J. Edvinsson, D. Rivas, H. Naas, A. Fawzi, A. Uhrenius,
J. Lindberg, J. Johansson, P. Arvidsson

A low power, monotonic[2], 12b slope ADC is shown in Fig 17.5.4. At

least 4096 clock cycles are required for a 12b conversion. The conversion rate cannot exceed 8S/s as the fastest clock available is
32kHz. In this ADC, a local oscillator is proposed to increase the
rate to 100 S/s. During 1, S1 and S3 are closed, and the input voltage Vin, is stored in CINT. During 2, S4 and S5 are closed to level
shift the CINT by Vref. During 3, S2, S4 and S5 are closed to discharge CINT by a constant current, and the oscillator starts and the
counter measures the time for the CINT to discharge to Vref. When
performing a measurement, two other reference voltages Vref and
Vss are measured to calculate the gain and offset for the ADC. Noise
is the major linearity factor in this design: CINT is chosen for KT/C <
1LSB and local oscillator jitter < 1LSB.

17.5

St. Jude Medical, Sunnyvale, CA

Implantable pacemakers using few transistors were introduced in
the 1950s. Technology advances provide automatic sensitivity and
improves therapy. A block diagram is outlined in Fig. 17.5.1 and
contains amplifiers, filters, ADCs, a battery management system,
high-voltage output generators and logic controls. It is powered by
a primary battery to provide 5-10 year life.
Pacemakers need to sense very small (~V) cardiac signals which are
amplified by an LNA and gain amplifier, BPF and digitized by ADC.
An SC amplifier and BPF are often used for accurate frequency
response and low power consumption (~20nA each). Transistors are
operated in the sub-threshold region to maximize the gm. The cardiac
and respiration signals may vary within 0.01-2Hz. Their SC sampling rate is in tenths of a Hz so transistor leakage may become a
serious issue. Assume the S/H amplifier (SHA) in Fig. 17.5.2, with
Chold=1pF, a S/H period of 100ms, and a 1pA of leakage will drift 0.1V
during the hold period. This is unacceptable when mV or V of resolution is required. It is solved by using a larger capacitor which costs
silicon area and consumes more power. A technique is presented to
reduce the effective leakage current seen by the capacitor[1].
To illustrate the concept, as implemented in Fig. 17.5.2, a self-adjusted current source is added. When the switch is off, a cancellation current Icancel is injected to Vhold to cancel all the leakages (I1, I2, I3). The
effective leakage seen by Chold is virtually zero. Thus, Chold can be kept
very small allowing low power operation and small area. A replica
switch and a current cancellation feedback network are also introduced. The replica switch is identical to the main switch, whereas the
replica capacitor Crep is smaller than the main capacitor Chold. Assume
the leakage cancellation feedback network is temporarily omitted
from the system. When the switches are off, the leakages on the replica switch are the same as the main switch. If leakage currents exist,
the voltage drift on the replica node Vrep is larger than the main mode
Vhold, because Crep < Chold. Now, add back the leakage cancellation feedback to the complete system and close the loop. M1, M4, M5 and M8
are the constant leakage generators with large W/L, and their
sourcing/sinking currents are higher than I1, I2, and I3. By utilizing
the opamp A1, a closed loop system is formed with a push-pull output
stage using the leakage generators. It senses the difference between
Vhold and Vrep, and injects the counter-current Icancel, to cancel the leakages. A quiescent state is reached when Icancel is equal to the switch
leakage, and both Vhold and Vrep do not drift any further. If A1 is ideal
and all transistors are matched, the leakages will cancel perfectly.
However, consider the opamp gain A and offset voltage Voffset, so that
the effective voltage drift is given in (1). The drift can be minimized
by reducing Voffset, increasing A or maximizing (Chold-Crep).
Aout
f(
+ Voffset )
f (V diff )
dV hold
I delta
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=
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dt
Chold Crep Chold Crep
Chold Crep

(1)

An 8b successive approximation register (SAR) ADC is shown in Fig.

17.5.3 in which, the power is typically consumed by SHA, DAC and
comparator. To minimize power, this ADC: (i) utilizes a capacitor
array (CA) for the DAC, (ii) uses a single opamp for both S/H and
comparator, (iii) combines the DAC CA for S/H usage. The operation
is as follows: First, the input is sampled and stored by connecting CA
to Vin, and closing the feedback loop of the S/H-comparator for autozero sampling. Next, the S/H feedback switch is open, and the integrating S/H-comparator turns into a comparator. The SAR conversion begins by sequentially connecting CA (MSB to LSB) to either
VREF_1 or VREF_0 for 8 cycles and to evaluate the digital output. The S/Hcomparator is formed by three class AB amplifiers or inverters. The
S/H output is taken from the first amplifier to provide unity gain stability for auto-zeroing. The comparator output is taken from the third
amplifier for high voltage gain. Transistors are operated in subthreshold region to maximize gm with minimal current. A divide-by-

A 2.8V battery is often used, as its output voltage stays relatively constant but drops steeply when it approaches end-of-life.
Voltage comparators are used to determine the battery status
but may not be very accurate because of the flat characteristics.
A battery charge meter is proposed in Fig. 17.5.5. It consists of a
VCO and a counter. It senses the battery current and integrates
it continuously so the total charge depleted from the battery can
be calculated[3]. The output of the counter is
(2)
Count = FreqVCO dt = KVCO I (t ) R dt
The depleted charge becomes
Count
(3)
Q = Ch arg e = I ( t ) dt =

KVCO R

The system provides ~0.5A of resolution, so the VCO requires

very low input offset voltage. An SC auto-zero VCO is used consisting of an integrator and a comparator. During 2 one end of
the input voltage is sampled with auto-zero and stored on Cs.
During 1 the other end of the input voltage is sampled and Cint
integrates the voltage difference. Depending on the state K, the
integrator output Vramp either ramps up or down. The step size at
each SC sampling is
(V
Vin _ n ) C s
(4)
V ( per _ step ) = in _ p
ramp

int
The total current consumption of the system
is 110nA and input offset is 150V due to a few fF of parasitic mismatch.

To stimulate the heart muscle, e.g., initiate a heart beat, a highvoltage output DAC is used. It delivers a rectangular pulse with
programmable voltage and pulse width as shown in Fig. 17.5.6.
During the pre-charge phase, all pre switches are closed and reference Vref and opamp offset are stored at C1. During the output phase,
all out switches are closed to form a feedback loop and the output is
Vout = Vref * C2/C1. HVCMOS are used at the output stage of the generator. The human heart is modeled by complex R-C networks with
hysteresis so frequency compensation for the HV output stage
needs special attention. A 2-in-1 opamp is designed having a common input stage and two outputs: Vpre and Vout. The HV Vout provides
a low-impedance output stage with dedicated frequency compensation designed for the heart, whereas the low-voltage (LV) Vpre is used
for the auto-zero and requires unity-gain stability. The HV output
has 2-stage amplification whereas the LV output has 1-stage, i.e.,
the input stage polarity is inverted. The HV NMOS that connect to
Vb are to protect the LV NMOS from oxide and channel breakdown.
The 7x7mm2 chip is fabricated in a 0.5m CMOS process, a photomicrograph of which is displayed in Fig. 17.5.7.
Acknowledgements:
Authors thank: R. Lam, D. Tran, A. Krier, T. Kurucz, M. Anvar, P. Kim, D.
Andersen, R. Shahandeh, W. Yang, H. Strandberg, F. Westman, A. Olson,
C. Sorensen and G. Isaac for contributions to this successful silicon.
References:
[1] L. S. Y. Wong, S. Hossain, A. Walker, Leakage Current Cancellation
Technique for Low Power Switched-Capacitor Circuits, patent pending
[2] J. Ryan, K. Carroll, B. Pless, A Four Chip Implantable
Defibrillator/Pacemaker Chipset, Proc. of IEEE Custom Integrated
Circuit Conference, pp7.6.1-7.6.4, May 1989
[3] A. Zadeh, Meter for Measuring Battery Charge Delivered in an
Implantable Device, US Patent number 5,769,873.

2004 IEEE International Solid-State Circuits Conference

0-7803-8267-6/04 2004 IEEE

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2004 IEEE International Solid-State Circuits Conference

0-7803-8267-6/04 2004 IEEE

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2004 IEEE International Solid-State Circuits Conference

0-7803-8267-6/04 2004 IEEE