B.E./ B.Te ch .

D EGREE EXA M I N A TI ON , M A Y/ JUN E 2 0 1 2

Fo u r t h Se m e st e r
Co m p u t e r Sci e n ce a n d En g i n e e r i n g
CS 2 2 5 3 / 1 4 1 4 0 3 / CS 4 3 / CS1 2 5 2 A / 1 0 1 4 4 CS 4 0 4 / 0 8 0 2 5 0 0 1 1 COM PUTER ORGA N I SA TI ON A N D A RCH I TECTURE
( Co m m o n t o I n f o r m a t i o n Tech n o l o g y )
( Re g u l a t i o n 2 0 0 8 )

Tim e : Three hours

Maxim um : 100 m arks

A n sw e r a l l q u e st i o n s.

PART A- ( 10* 2 = 20 MARKS)

1. What is SPEC? Specify t he form ula for SPEC rat ing.
2. What is r elat ive addressing m ode? When is it used?
3. Writ e t he regist er t ransfer sequence for st oring a word in m em ory.
4. What is har d- wired cont rol? How is it different from m icroprogram m ed cont r ol?
5. What is m eant by dat a and cont r ol hazards in pipelining?
6. What is m eant by speculat ive execut ion?
7. What is m eant by an int er leaved m em ory?
8. An addr ess space is specified by 24 bit s and t he corresponding
m em ory space by 16 bit s:
How m m any wor ds are in t he
( a) virt ual m em or y
( b) m ain m em ory
9. Specify t he different I / O t ransfer m echanism s available.
10. What does isochronous dat a st r eam m eans?

PART B- ( 5* 16 = 80 m arks)
11. ( a) ( i) What ar e addressing m odes? Explain t he v arious addressing
m odes wit h exam ples. ( 8)
( ii) Deriv e and explain an algor it hm for adding and sub t r act ing 2
float ing point binary num ber s.( 8)
Or
( b) ( i) Explain inst ruct ion sequencing in det ail. ( 10)
( ii) Differ ent iat e RI SC and CI SC archit ect ures. ( 6)
12. ( a) ( i) Wit h a neat diagram ex plain t he int er nal or ganizat ion of a
processor . ( 6)
( ii) Explain how cont rol signals are generat ed using m icroprogram m ed
cont rol. ( 10)
Or
( b) ( i) Explain t he use of m ult iple- bus or ganizat ion for ex ecut ing a
t hree- operand inst ruct ion. ( 8)
( ii) Explain t he design of har dwir ed cont rol unit . ( 8)
13. ( a) ( i) Discus t he basic concept s of pipelining. ( 8)
( ii) Describe t he dat a pat h and cont r ol considerat ions for pipelining.
( 8)
Or

( b) Describe t he t echniques for handling dat a and inst ruct ion hazards
in pipelining. ( 16)
14. ( a) ( i) Explain synchronous DRAM t echnology in det ail. ( 8)
( ii) I n a cache- based m em or y syst em using FI FO for cache page
replacem ent , it is found t hat t he cache hit rat io H is low.
The following proposals are m ade for incr easing.
( 1) I ncr ease t he cache page size.
( 2) I ncr ease t he cache st orage capacit y.
( 3) I ncr ease t he m ain m em or y capacit y.
( 4) Replace t he FI FO replacem ent policy by LRU.
Analyse each proposal t o det er m ine it s probable im pact on H. ( 8)
Or
( b) ( i) Explain t he var ios m apping t echniques associat ed wit h cache
m em ories. ( 10)
( ii) Explain a m et hod of t ranslat ing v irt ual address t o physical addr ess.
( 6)
15. ( a) Ex plain t he following:
( i) I nt err upt priorit y schem es. ( 8)
( ii) DMA. ( 8)
Or
( b) Writ e an elaborat ed not e on PCI , SCSI and USB bus st andar ds.
( 16)