RSM2011 Proc.

, 2011, Kota Kinabalu, Malaysia

Design of a 5GHz Phase-Locked Loop

Zainab Mohamad Ashari, Anis Nurashikin Nordin, and Muhamad Ibn Ibrahimy
Electrical and Computer Engineering Department
International Islamic University Malaysia
53100 Kuala Lumpur, Malaysia
zainab_ashari@yahoo.com
AbstractNoise or jitter performance is a major concern in the
design of phase-locked loop (PLL). Linearity and speed issues are of
relevance when receiving data at gigahertz speed. The main function
of a PLL circuit is to generate stable higher frequencies (GHz)
output from a lower input frequency signal. PLLs are often used in
communication technology to implement a variety of functions such
as clock recovery, frequency multiplication, and clock
synchronization. This paper presents the design and simulation
results of PLL with low jitter performance. The key goal is to design
and develop an analog PLL circuit for 5 GHz clock data recovery
circuit. The PLL comprises of a phase frequency detector (PFD),
low pass filter, voltage controlled oscillator (VCO), and feedback
divider. In this work, analog mixed-signal architecture of PLL is
simulated using hardware discipline modeling language, VerilogAMS HDL. Multilingual and Mixed-Signal simulator SMASH
software has been used for the Verilog-AMS design. A 5 GHz PLL
with less jitter was successfully designed in this work.
Keywords: Phase-locked loop (PLL), jitter, Verilog-AMS, Phase
Frequency Detector, Low-pass Filter, and Voltage-controlled Oscillator

I.

INTRODUCTION

Phase-locked loop (PLL) is one of the techniques to generate

high frequencies for receivers and transmitters. PLL was
introduced in the communication technology and electronic
devices since early 1930 by De Bellescize, a French Engineer [1,
2]. It started to be popular in industrial applications when it
became an integrated circuit. Different types of PLLs were
developed for different applications and technologies in recent
years. New applications of PLL are in instrumentation,
communication, and electronics devices such as memories, hard
disk drives, and wireless transceivers.
Modern communication demands high speed performance in
data transmission with low power consumption, low jitter, low
cost, and small size. A high speed transceiver is required in
numerous applications and areas such as backplane routing, chipto-chip interconnect integrated circuits and optical devices in
communication systems. The demands of high bandwidth and
high speed input/output (I/O) performance especially in the chipto-chip interconnect applications is extremely increased from time
to time [2, 3].
Another application of the PLL is in the clock data recovery
circuit (CDR). CDR is a major component of the transceiver
which determines its performance [4]. A signal transmission
process is easily distorted for high bandwidth data. The resulting
data and clock signals will be noisy, jittery and difficult to extract.

978-1-61284-846-4/11/$26.00 2011 IEEE

Due to this reason, CDR circuit has become a crucial component

for high speed performance to receive gigahertz data.
In this work, a mixed-signal (PLL) of 5 GHz CDR receiver
circuit was designed. PLL clocks are required to be aligned to the
transitions of the input data stream [4].This paper presents the
design and simulation results of high performance 5GHz PLL
with low jitter performance. The PLL circuit was designed using
hardware modeling language, Verilog-AMS HDL using SMASH
software.
This paper first describes basic architecture of phase lockedloop (PLL). Modeling and simulation of proposed PLL is
discussed next in section III. Finally, the simulation results with
improved jitter performance and conclusion are analyzed.
II.

BASIC ARCHITECTURE OF PHASE LOCKED LOOP (PLL)

The phase-locked loop is generally known as a negativefeedback system with forward gain term and feedback term.
Various PLL architectures have been developed as its popularity
grew in communication systems. Programmable PLL, single and
multi-phase PLL, digital PLL, PLL with lock detector, PLL
frequency synthesizer, PLL FM/AM, single RF/ multi RF PLL,
and super PLL have been reported [5, 6].
The basic design of PLL usually consists of three functional
blocks which are phase detector (PD), loop filter, and voltage
controlled oscillator (VCO) as shown in Fig. 1. This simple
design of PLL is capable to supress noise from the input signal.
For high frequency operations, a PLL should be capable of
operating in both locked and unlocked conditions. The simple
PLL circuit shown in Fig.1 can only operate in the locked
condition .
The PLL technique is capable of generating high frequencies
even from a low-frequency reference. It is really suitable for any
system which requires stable high frequency performance. Fig. 2
demonstrates a basic frequency multiplication architecture which
is typically used for CDR circuits. It consists of PFD, chargepump, low pass filter, VCO and divider. This architecture is quite

Fig. 1. Simple PLL circuit .

167

RSM2011 Proc., 2011, Kota Kinabalu, Malaysia

Fig. 2. Multiplication architecture for PLL [5].

Fig. 4.

Architecture of proposed PLL model.

Fig. 5. PLL circuit design.

Fig. 3. Basic PLL architecture for CDR circuits [7].

popular for PLL design. However, the output signal suffers from
subtantial skew with respect to input data [6] . Most of the clock
drives a large number of transistors and logic interconnects
which causes delay.
Fig. 3 shows the basic architecture of PLL for CDR circuits
which consists of five main blocks; phase detector, charge pump,
low pass filter, voltage controlled oscillator, and decision circuit
[7]. What makes the second PLL different with the first PLL
arcitecture is the divider.
According to [6], the skew effect suffered using the PLL
architecture of Fig.2 and Fig.3 can be reduced by adding a buffer
and a capacitor between the VCO and feedback divider. The
design of proposed PLL in Fig.4 is the advancement from Fig.2
and Fig.3 with additional components and coding using VerilogAMS HDL.
III.

MODELING AND SIMULATION

Many different simulator tools are available for designing and

modeling integrated circuits such as SPICE and analog hardware
description language (HDL). Conventionally, SPICE is one of
the popular tools that support modeling and designing of analog
circuit. However, SPICE is not applicable for analog mixedsignal integrated circuit design [8]. An analog hardware
description language (HDL) allows the modeling of analog and
digital signals simultaneously. One of the advantages of VerilogAMS is that the electrical components are described based on the
mathematical description or behavioral expression. The
description and simulation of analog mixed-signal systems is
obtained from the behavioral to the circuit level [8, 9].

168

It is important to note that the Verilog-AMS is easy to use

since it needs simple expression to make a circuit work. Instead
of using complicated resistor, conductor, and transistor SPICE
models, Verilog-AMS of SMASH software is chosen to design
the PLL circuit.
The proposed PLL architecture is composed of analog mixedsignal blocks. PFD, low pass filter, VCO, feedback divider, and
resistor. The phase frequency detector is a digital block. The low
pass filter and the VCO are categorized as analog block. Fig.4
illustrates the proposed modeling PLL architecture. Fig. 5
illustrates the detailed connection of 5 GHz PLL circuit. This
PLL compares the input signal at PFD with the output signal at
the VCO. Each block was simulated separately before connected
as an overall PLL system.
A. Phase Frequency Detector (PFD)
The phase frequency detector (PFD) is a key component in
PLL system. It compares the phase and frequency different
between the reference signal and internal feedback signal [10,
11]. The performance of a CDR circuit is determined by the
phase frequency detector [11, 12]. The best phase detector should
accomplish three essential functions namely data transition
detection, phase and frequency difference detection and low
noise. Fig. 6 shows the implementation of PFD in a PLL system.

Fig. 5. PFD block.

RSM2011 Proc., 2011, Kota Kinabalu, Malaysia

The output of PFD is proportional to the injected input phase
and frequency signal with low noise. The output voltage of PFD
is dictated by the verilog equation and verilog AMS code. Fig.6
illustrates the verilog AMS code used to design the PFD. Fig.7
illustrates the input signal of the PFD which contains jitter and
Fig.8 shows the clean output signal of PFD. The second input of
the PFD, b is obtained from the feedback divider output and is
shown in Fig.15.

V (out ) < +2.0 * V (src ) * tanh (20.0 * V (in ))

`include "../packages/disciplines.vams"
`include "../packages/constants.vams"
module pfd(in, src, out);
inout
in, src, out;
electrical in, src, out;
parameter real gain = 0.40;
analog
V(out) <+ gain * V(src) * tanh(20.0 * V(in));
endmodule
Fig. 6. Verilog AMS code for PFD.

(1)
Fig. 9. RLC low-pass filter [13].

B. Loop Filter
Based on Fig.4, the second block in the PLL after a phase
detector is a loop filter. The low pass filter with one pole and one
zero is frequently used in designing CDR circuit based on the
PLL approach [11, 14]. The transient response of the loop filter
depends on the magnitude of the pole and zero is slightly
important in designing stable low-pass filter. The circuit design
of RLC low-pass filter is shown in Fig.9.The following formulas
and coding in Fig.10 is used to verify the numerical values of the
RLC low-pass filter. The simulation result shown in Fig.11 is
constantly zero because the loop filter is used to diminish jitter
from the input.

G (s ) =

Fig. 7. Input signal of 50 MHz, (a).

Z=

1
s 2 + Rs

LC
L

+1

(2)

LC

X L = j 2fL

(3)

Xc = 1

(4)

j 2C

( X L + X C )2

+ R2

(5)

The voltage and current of RLC low-pass filter is based on

three equations below.

Fig. 8. Output signal of 50 MHz, (c).

V (b1) < + Re s * I (b1)

(6)

I (b1) < +Cap * ddt (V (b1))

(7)

V (b1) < + Ind * ddt (I (b1))

(8)

169

RSM2011 Proc., 2011, Kota Kinabalu, Malaysia

`include "../packages/disciplines.vams"
`include "../packages/constants.vams"
module rlc(N1, N2);
parameter real res=3e3;
parameter real ind=68e-6
parameter real cap=0.149e-12;
inout N1, N2;
electrical N1, N2;
analog begin
V(N1,N2) <+ res*I(N1,N2);
I(N1,N2) <+ cap*ddt(V(N1,N2));
V(N1,N2) <+ ind*ddt(I(N1,N2));
end
endmodule

Fig. 10. Verilog AMS code for LPF.

Fig. 11. Waveform signal of RLC low-pass filter, (e).

Fig. 13. Output waveform of VCO, (out).

VCO is another part of PLL system shown in between nodes e

and out in Fig.5. It is frequency-controlled device which control
voltage input and creates a frequency proportional to the control
voltage [9]. It will generate high or low output frequency based
on the requirement value. Center frequency and VCO gain are
two important parameters must be determined to design PLL
system. In this work, the VCO is responsible to generate high
output frequency signal compares to its input frequency. The
VCO was programmed using Verilog AMS code as shown in
Fig.12. Fig.13 illustrates the simulation results of the VCO
output at 5 GHz frequency.
D. Divider
The frequency divider is also known as frequency down
scalers was also implemented in the PLL. The additional
feedback divider between out and b in the PLL system is to force
the VCOs frequency to be equal to the reference frequency
signal. The feedback loop indirectly makes the reference
frequency identical with the output frequency of the VCO over N
times. The following equation determines the value of feedback
divider, N. The Verilog AMS code for divider shows in Fig.14.
The output frequency, fout is equal to the N times of reference
frequency, fref. The output waveform shows in Fig. 15 which is
equal with the input frequency of PFD, 50 MHz.

C. VCO
`include "../packages/disciplines.vams"
`include "../packages/constants.vams"
module vco(in, out);
inout
in, out;
electrical in, out;
parameter real gain = 0.40;
parameter real fc = 4.9e9;
analog
V(out) <+ sin(`M_TWO_PI * idtmod(fc + gain * V(in), 0, 1, 0));
endmodule

Fig. 12. Verilog AMS code for VCO.

f out = Nf ref
`include "../packages/disciplines.vams"
`include "../packages/constants.vams"
module divider(in, out);
inout
in, out;
electrical in, out;
parameter real div = 100;
parameter real gain =0.40;
parameter real fc = 4.9e9;
analog
V(out) <+ sin(`M_TWO_PI * idtmod(fc/div + gain * V(in), 0, 1,
0));
endmodule
Fig. 14. Verilog AMS code for divider.

170

(9)

RSM2011 Proc., 2011, Kota Kinabalu, Malaysia

V.

CONCLUSION

This paper presented the design of 5GHz analog mixed signal

PLL using Verilog-AMS SMASH Dolphin Integration software.
The proposed design composed of PFD, RLC lowpass filter,
VCO, feedback divider, and resistor. A 50 MHz input was
successfully applied in this PLL design to generate 5 GHz
frequency signal with less jitter performance.
ACKNOWLEDGMENT
Fig. 15. Feedback waveform of proposed PLL 50 MHz, (b).

This work is funded by the Ministry of Science and Technologys

(MOSTI) Techno Fund Grant TF0409D100.
REFERENCES
[1]
[2]
[3]
[4]
[5]

Fig. 16. Output waveform of proposed PLL 5 GHz, (out).

IV.

DISCUSSION

With reference to the PFD simulation results in Fig.7 and

Fig.8, the output signal of 50 MHz was less noise compares to
the input PFD. This means that the proposed PFD circuit is
capable of handling GHz data and removing jitter. The output of
the PFD circuit is an uncorrupted square wave which is ideal for
clock-handling circuits. RLC low-pass filter is used to ensure the
CDRs stability. The transient response of the RLC low-pass
filter depends on the magnitude of the pole/zero as shown in
Fig.11. The VCO generates a stable high frequency sinusoidal
signal based on the DC voltage output from the RLC. The high
frequency output of the VCO can be utilized. The divider block
divides the output frequency produced by the VCO by a factor of
N in order to be equal to the input frequency signal, 50 MHz.
This is proven in Fig.15. The divider provides a clean low
frequency sinusoidal output which can be compared with the
input reference signal using the PFD. Fig. 16 demonstrates that
the proposed PLL model can generate a clean high frequency
output a hundred times larger than the input frequency.

[6]

[7]
[8]
[9]
[10]
[11]

[12]
[13]
[14]

J.Li and F.Yuan, "A new hybrid phase detector for reduced lock time
and timing jitter of phase-locked loops," Analog Integrated Circuits
and Signal Process (2008), pp. 233-240, 2008.
M.Curtin and P.O'Brien, "Phase-locked loops for high frequency
receivers and transmitters-part1," presented at Analogue Dialogue 333 (1999), 1999.
T.K.Siang, M.S.Sulaiman, C. H. T. M.Reaz, and M.Sachdwv, "A
fully- integrated 5 Gbit/s CMOS clock and data recovery circuit,"
Analog Integr Circ Sig Process 2007, pp. 101-109, 2007.
Y.Liu and H.Yang, High-speed optical transceivers: integrated
circuits design and optical devices techniques, vol. 39, 2006.
Y.-G. Song, Y.-S. Choi, and J.-G. Ryu, "A phase-locked loop of the
resistance and capacitance scaling scheme with multiple charge
pumps," Analog Integrated Circuits and Signal Processing vol. 66,
pp. 155-62, February 2011
S.V.Solanke, "Design and analysis of of novel charge-pump
architecture for phase locked-loop," in Department of Electronics and
Communication Engineering: National Institute Of Technology
Rourkela, 2009, pp. 1-70.
B. Razavi, "A 10-Gb/s CMOS clock and data recovery circuit with a
half-rate linear phase detector," IEEE Journal of Solid-state Circuits,
vol. 36, pp. 761-768, 2001.
S.Kang, Analog hardware description language for a radio frequency
system, 2000.
J.Meyer, "Modeling phase-locked loops using verilog," presented at
39th Annual precise Time and Time Interval (PTTI) Meeting, 2007.
B.Razavi, "Challenges in the design of high-speed clock and data
recovery circuits," in IEEE Communication Magazine, 2002, pp. 94101.
T.Oura, Y.Hiraku, T. Suzuk, and H.Asai, "Modeling and simulation of
phase-locked loop with Verilog-A description for top-down design,"
presented at Circuits and Systems, 2004. Proceedings. The 2004 IEEE
Asia-Pacific Conference on 2004.
B. Razavi, Design of integrated circuit for optical communications:
McGraw-Hill, 2003.
J. W. Nilsson and S. A. Riedel, Electric Circuits, seventh ed: Pearson
Prentice Hall, 2005.
T.K.Siang, M.S.Sulaiman, C.H.Teik, and M.Sachdev, "Design of
high-speed clock and data recovery circuits," pp. 15-23, 2007.

171