AREA-DELAY-POWER EFFICIENT CARRY-SELECT ADDER

ABSTRACT:
In this paper, we made an analysis on the logic operations involved in
conventional carry select adder (CSLA) and binary to excess-1 converter (BEC)-based CSLA to
study the data-dependency and to identify redundant logic operations. We have eliminated all the
redundant logic operations present in conventional CSLA and proposed a new logic formulation
for CSLA. In the proposed scheme, the carry-select operation is scheduled before the calculation
of final-sum, which is different from the conventional approach. Bit-patterns of two anticipating
carry-words (corresponding to Cin=0 and 1) and fixed Cin bits are used for logic optimization of
carry select and generation units. An efficient CSLA design is obtained using optimized logic
units. The proposed CSLA design involves significantly less area and delay than the recently
proposed BEC-based CSLA. Due to small carry-output delay, the proposed CSLA design is a
good candidate for square-root (SQRT)-CSLA. Theoretical estimate shows that the proposed
SQRT-CSLA involves nearly less area-delay-product (ADP) than the BEC-based SQRTCSLA
which is the best amongst the existing SQRT-CSLA designs on average for different bit-widths.
FPGA synthesis result shows that, the BEC-based SQRT-CSLA design involves more Area
Delay Product and consumes more energy than the proposed SQRT-CSLA on average for
different bit-widths.

EXISTING SYSTEM:
Conventional CSLA is a RCA-RCA configuration which generates a pair of sum words
and output-carry bits corresponding the anticipated input-carry (cin= 0 and 1), and selects one

out of each pair for final-sum and final-output-carry. Conventional CSLA has less CPD than
RCA, but the design is not attractive, since it uses dual RCA. Few attempt have been made to
avoid dual use of RCA in CSLA design.
EXISTING SYSTEM TECHNIQUE:

Ripple Carry Adder

EXISTING SYSTEM DRAWBACKS

More area overhead system

More power consumption

PROPOSED SYSTEM
The CBL based CSLA of involves significantly less logic resource than the conventional
CSLA, but it has longer CPD which is almost equals to that of RCA. To overcome this problem,
SQRT-CSLA based on CBL has been proposed. We observe that, logic optimization largely
depends on availability of redundant operations in the formulation, where adder delays mainly
depends on data-dependency.
Proposed Technique:
Binary to Excess-1 Converter
BLOCK DIAGRAM:

SOFTWARE REQUIREMENTS:

ModelSim 6.4c

Xilinx ISE 9.1/13.2

HARDWARE REQUIREMENT:

FPGA Spartan 3

APPLICATIONS:

Its mainly used in Digital signal processing

Area efficient system like satellite, mobile phones

ADVANTAGE:

Less area overhead

Less power consumption

High speed architecture

FUTURE ENHANCEMENT:
In our Base paper they are Implemented 8 Bit, 16 Bit, and 32 Bit Existing and Proposed
adders. Now our proposed architecture converted into 128 bit Adders and analyzes the area
power. This adder will be done by using our verilog and the Adder design will implemented into
FPGA Spartan3.

ALTERNATE TITLES:
Title 1: Implementation of an Efficient Carry-Select Adder on FPGA
Title 2: An efficient realization of 128 Bit Carry-Select Adder
Title 3: Achievement of Carry-Select Adder Using Verilog HDL

PROJECT FLOW:
First Phase:
60% of Base Paper (3 Modules only Simulation)

Second Phase:
Remaining 40% of Base Paper with Future Enhancement (Modification).