Five-level inverter voltage-space phasor generation

for an open-end winding induction motor drive

M.R. Baiju, K. Gopakumar, K.K. Mohapatra, V.T. Somasekhar and L. Umanand
Abstract: A topology for voltage-space phasor generation equivalent to a ve-level inverter for an
open-end winding induction motor is presented. The open-end winding induction motor is fed
from both ends by two three-level inverters. The three-level inverters are realised by cascading two
two-level inverters. This inverter scheme does not experience neutral-point uctuations. Of the two
three-level inverters only one will be switching at any instant in the lower speed ranges. In the
multilevel carrier-based SPWM used for the proposed drive, a progressive discrete DC bias
depending on the speed range is given to the reference wave to reduce the inverter switchings. The
drive is implemented and tested with a 1 HP open-end winding induction motor and experimental
results are presented.

Introduction

Multilevel converters can produce an output voltage

waveform having a large number of steps with low
harmonic distortion [1, 2]. They can also reduce the stress
on the switching devices as higher levels are synthesised
from voltage sources with lower levels. These features have
made them suitable for application in large and medium
induction motor drives. There are three main topologies of
multilevel inverters relevant for large induction motor drive
applications: the extended neutral-point clamped inverters,
series-connected H-bridge inverters, and dual-inverter-fed
open-end winding induction motor drives.
The extended neutral-point clamped inverters experience
neutral-point uctuations as the DC-link capacitors have to
carry the load current [3]. The series-connected H-bridge
topology of multilevel inverters has been suggested for
induction motor drives and it requires separate DC supply
for all three phases, which increases the power circuit
complexity. A ve-level inverter structure using the Hbridge topology will require totally six power supplies [4].
Feeding the open-end winding induction motor from
both ends also results in a multilevel structure [5, 6]. In [5], a
phase-shifted sinetriangle PWM is used for the multilevel
voltage generation for the open-end winding induction
motor drive, and in [6] a space-vector-based PWM
approach is explained for three-level voltage-space phasor
generation for an open-end winding induction motor drive.
The open-end winding structure is realised by opening the
neutral-point of the conventional squirrel cage induction
motor. The open-end winding induction motor is then fed
by two inverters from the two the ends of the winding. This
technique has been used to implement a four-level inverter
using two two-level inverters with asymmetric DC links [7].
In the present work, a multilevel voltage-space phasor
generation, equivalent to a conventional ve-level inverter is

presented for an open-end winding induction motor drive

using two three-level inverters. The three-level topology
used is realised by cascading two two-level inverters. This
ve-level inverter does not experience neutral point uctuation and uses a lesser number of DC sources compared to
the series-connected H-bridge topology. In the multilevel
carrier-based PWM implemented for the drive a progressive
discrete DC bias is given to the reference wave depending
on the speed range, resulting in reduced switching losses and
in reduced switchings of the inverter.
2

Proposed inverter structure

The structure of the proposed drive with open-end winding

induction motor is shown in Fig. 1. The induction motor is
fed by two three-level inverters, inverter A and inverter B.
These three-level inverters are realised by cascading two
two-level inverters. Inverter A is formed by cascading twolevel inverters INV 1 and INV 2 and inverter B is formed by
cascading two-level inverters INV3 and INV4. All four twolevel inverters have a separate DC supply of Vdc/4 where Vdc
is the DC-link voltage of the conventional two-level inverter
fed induction motor drive.

2.1

Operation of three-level inverter

The pole voltages vA2O , vB2O and vC2O of inverter A can

realise three levels 0, Vdc/4 and Vdc/2. Inverter B is also a
three-level inverter and its pole voltages with respect to the
point O0 (vA4O0 , vB4O0 and vC4O0 ) can also independently
realise the three levels of 0, Vdc/4 and Vdc/2. When these
three-level inverters drive the induction motor from both
sides, each phase of the induction motor can attain ve
different levels. To nd the equivalent levels when inverters
A and B are switched independently, we assume that the
points O and O0 are connected. The phase voltages are then
given by

r IEE, 2003
IEE Proceedings online no. 20030659
doi:10.1049/ip-epa:20030659
Paper rst received 6th November 2002 and in revised form 13th May 2003.
Originally published online: 24th July 2003
The authors are with the Centre for Electronics Design and Technology, Indian
Institute of Science, India 560012
IEE Proc.-Electr. Power Appl., Vol. 150, No. 5, September 2003

vA2A4 vA2O  vA4O0

vB2B4 vB2O  vB4O0

vC2C4 vC2O  vC4O0

3
531

Fig. 1

Structure of the five-level inverter: two three-level inverters feeding induction motor from both ends

The ve levels generated in the A-phase when inverters A

and B are switched with different pole voltage levels are
shown in Table 1. The rst two levels Vdc/2 and Vdc/4
(L1, L2) are obtained when inverter A is clamped to zero
and while inverter B is switched between Vdc/2 and Vdc/4.
Hence at the lower speed range only inverter B will be
switching. These levels in any phase can be attained by
turning on a combination of switches in inverter A and
inverter B. Table 2 shows the switches to be turned on to
realise levels in the A-phase winding. Whenever the bottom
switch in any leg of the bottom inverter is on, the top
switch in the same leg of the top inverter is kept off so that
it has to block only the DC-link voltage of Vdc/4. The

conditions to be forced on the top switches of the inverters

to realise these levels are shown in the Table 3. The state of
the bottom switch is complimentary to the condition of the
top switch in the same leg. The bottom switches of the
bottom inverters INV2 and INV4 have to be rated for
Vdc/2, as they will have to block Vdc/2 when the top switches
of INV1 and INV3 are on.
This ve-level topology does not need the
clamping diodes as in the case of neutral-point-clamped
inverters. The DC-link capacitors do not carry the load
current and hence the neutral-point uctuations are absent.
When compared with the series-connected H-bridge, it uses
the same number of switching devices but employs fewer

Table 3: Status of top switches of two-level inverters for

A-phase
Table 1: Levels realised in A-phase for combinations of pole
voltages of inverter A and inverter B

Level of 5-level Status of top switches of 2-level inverters

inverter for
(bottom switches condition are complementary)
A-phase leg
INV 1
INV 2
INV 3
INV 4
(S11)
(S21)
(S31)
(S41)

Pole voltage of
inverter A vA2O

Pole voltage of
inverter B vA4O

Voltage level in
A-phase winding

Level

Vdc /2

Vdc /2

L1

Vdc /2

off

off

on

on

Vdc /4

Vdc /4

L2

Vdc /4

off

off

off

on

L3

off

off

off

off

Vdc /4

Vdc /4

L4

Vdc /4

off

on

off

off

Vdc /2

Vdc /2

L5

Vdc /2

on

on

off

off

Table 2: Switching strategy to realise five levels shown for one pole (A-phase)
Levels in A-phase winding
of 5-level inverter

Switches to be made on in A-phase legs (when top switch of leg is on the bottom switch is off)
INV 1

INV 2

INV 3

INV 4

L1

Vdc /2

S14 (bottom)

S24 (bottom)

S31(top)

S41 (top)

L2

Vdc /4

S14 (bottom)

S24 (bottom)

S34 (bottom)

S41 (top)

L3

S14 (bottom)

S24 (bottom)

S34 (bottom)

S44 (bottom)

L4

Vdc /4

S14 (bottom)

S21 (top)

S34 (bottom)

S44 (bottom)

L5

Vdc /2

S11 (top)

S21 (top)

S34 (bottom)

S44 (bottom)

532

IEE Proc.-Electr. Power Appl., Vol. 150, No. 5, September 2003

DC sources, as the H-bridge topology will need six DC

supplies.
3

space vector is then given by

V s Vsa jVsb

Voltage space phasors of proposed scheme

The combined effect of the three voltages in the three 1201separated phase windings of the induction motor at any
instant could be represented by an equivalent vector in
space Vs given by
V s vA2A4 vB2B4 :ej2p=3 vC2C4 :ej4p=3

where Vsa is the sum of all components of vA2A4 , vB2B4 and

vC2C4 along the a-axis and Vsb is the sum of the
components of vB2B4 and vC2C4 along the b-axis.
Vsa vA2A4 vB2B4a VC2C4a

Vsb vB2B4b VC2C4b

Substituting expressions for the phase voltages as given in

(1) to (3) in (4) gives
V s vA2O  vA4O0 vB2O  vB4O0 :ej2p=3
vC2O  VC4O0 :ej4p=3

"

This equivalent vector can be determined by resolving the

phase voltages along two mutually perpendicular axes, the a
and b axes, of which a is along the A-phase (Fig. 2). The

2
6
6
4

1
0

32
3
1 1
vA2A4
7
2
2
6
7
p
p 7
4 vB2B4 5
5
3  3
vC2C4
2
2

Substituting expressions for the phase voltages as given in

(1) to (3) in the above equation gives
Vsa

6
4
Vsb

Fig. 2 Determination of equivalent space vector from phase

voltages

Vsa

Vsb

Fig. 3

7 6
56
4

1
0

32
3
1 1
vA2O  vA4O0
76
2
2
7
p 7
p
4 vB2O  vB4O0 5
5
3  3
vC2O  vC4O0
2
2

10

The two three-level inverters can take the three levels of pole
voltages independently in any three phases depending on
the condition of the inverter switches, as decided by the
modulation scheme. For each of the different combinations
of their pole voltages, the equivalent voltage space phasor
V s can be determined using (10) along with (6). The
space phasors for all possible combinations of the
pole voltages of the two three-level inverters will occupy
different locations, as in Fig. 3. There are totally 61
locations forming 96 sectors and this structure is identical
to that of a conventional ve-level inverter. The maximum
amplitude of the space phasor generated can be veried to
be Vdc.

Space phasor locations for five-level inverter

IEE Proc.-Electr. Power Appl., Vol. 150, No. 5, September 2003

533

3.1 Effect of common-mode voltage in space

phasor locations

wave of peak-to-peak amplitude of Vc N  1 as

In the foregoing analysis we have assumed that the points O

and O0 are connected. If these points are isolated, as in the
proposed scheme, the actual phase voltages are
vA2A4 vA2O  vA4O0  vO0 O

12

vC2C4 vC2O  vC4O0  vO0 O

13

VO0 O corresponds to the common-mode voltage present in

this balanced three-phase system and is given by
1
vO0 O vA2O vB2O vC2O
3
14

V s vA2O  vA4O0  vO0 O vB2O  vB4O0  vO0 O :ej2p=3

vC2O  vC4O0  vO0 O :ej4p=3
vA2O  vA4O0 vB2O  vB4O0 :ej2p=3
vC2O  vC4O0 :ej4p=3  vO0 O vO0 O ej2p=3
vO0 O0 :ej4p=3
In this equation
vO0 O vO0 O ej2p=3 vO0 O0 :ej4p=3
1
1
vO0 O  vO0 O  vO0 O
2
2
0
and the equation then reduces to
V s vA2O  vA4O0 vB2O  vB4O0 :ej2p=3
vC2O  VC4O0 :ej4p=3
This equation is the same as that derived earlier (5),
assuming that points O and O0 were connected. Hence the
above analysis shows that the common-mode voltage
present between points O and O0 does not change the
space phasor locations. This common-mode voltage will
result only in the multiplicity of space phasors in different
locations, and the system with isolated O and O0 points
generates the same voltage-space phasors.
Modulation scheme for proposed inverter

A multilevel-carrier-based PWM is used for the proposed

inverter scheme. The multilevel-carrier-based PWM for an
N-level inverter uses a set of N1 adjacent, level-shifted
triangular carrier waves with the same peak-to-peak
amplitude Vc and the same frequency fc [8]. If the reference
wave has peak amplitude Vm and frequency fm the
modulation index is dened with reference to a triangular
534

15

The other parameter of multilevel-carrier-based SPWM is

the ratio mf fc =fm which should be kept high to keep
the harmonics to the higher end. For the ve-level inverter,
four triangular waves divide the whole modulating voltage
level into ve regions R1R5. R1 is the region below the
lowest carrier C1, R2 is the region between C1 and C2, R3
between C2 and C3, R4 between C3 and C4 and R5 above
C4. When the modulating signal is in a particular region the
corresponding voltage level is applied across the phase
winding, assigned as follows:

R1 )

Vdc
;
2

R4 )

Vdc
;
4

Substituting these expressions for the phase voltage in (4)

2Vm
Vc N  1

11

vB2B4 vB2O  vB4O0  vO0 O

1
 vA4O0 vB4O0 vC4O0
3

ma

R2 )

R5 )

Vdc
;
4

Vdc
2

R3 ) 0;

16

Three 1201 phase-shifted sinusoids with 20% third

harmonic content are used as the reference waves for
the proposed carrier-based SPWM. The addition of the
third harmonic content increases the maximum fundamental voltage amplitude that can be generated using the
SPWM scheme [9]. For low modulation index such
that Vm0
Vc =2, where Vm0 is the peak value of the
modulating signal, in conventional SPWM the reference
waves are placed at the centre of the carrier set
(Fig. 4a). This will result in a three-level operation as the
modulating signal at different instants could be in R4, R3
or R2 and both the two-level inverters constituting
inverter B (INV3 and INV4) switch to realise these threelevels. In the present work, for this range of modulation
index, the reference wave is centered at the middle of the
lowermost carrier as in Fig. 4b. It will result in only two
levels L1 Vdc =2 and L2 Vdc =4 and switching losses
are due to only INV3. When the modulation index increases
such that Vc =2
Vm0
Vc , the reference wave in the
proposed work is given an additional DC bias of Vc =2
such that it is in the middle of these two carriers and
resulting in three-level operation (Fig. 4c). A similar
condition in conventional SPWM also results in the threelevel operation, as seen in Fig 4d, but the reference waves
are placed at the centre of the carrier set. When
Vc
Vm0
3Vc =2, the modulating wave is shifted to place
it at the centre of the three lower carriers (Fig. 4e). This will
result in a four-level operation with INV2, INV3 and INV4
switching. In conventional SPWM, since the reference
waves are placed at the centre of the carrier set (Fig. 4f), this
condition will result in a ve-level operation and all the twolevel inverters would have switched. When the modulation
index increases such that Vm0  3Vc =2, the reference wave is
shifted to be positioned at the centre of the carrier set as in
Fig. 4h.
Hence in the proposed SPWM scheme, a
progressive DC bias of nVc =2 with respect to the
bottom point of the lowest carrier is given to the
reference waves, where n takes the value from 1 to 4
depending on the range in which the peak amplitude of the
modulating signal falls. The equations for the reference
waves used in the proposed SPWM scheme for the present
IEE Proc.-Electr. Power Appl., Vol. 150, No. 5, September 2003

Fig. 4
a
b
c
d
e
f
g

Reference wave for conventional SPWM during two-level operation

Reference wave for the proposed SPWM during two-level operation
Reference wave for the proposed SPWM during three-level operation
Reference wave for conventional SPWM during three-level operation
Reference wave for the proposed SPWM during four-level operation
Reference wave for conventional SPWM during four-level operation
Maximum reference wave during ve-level operation

work are given by

Va Vm sin ot 0:2Vm sin 3ot n

Vc
2


2p
Vc
Vm sin ot 
0:2Vm sin 3 ot n
3
2


4p
Vc
Vc Vm sin ot 
0:2Vm sin 3ot n
3
2
Vb

17
18
19

When this scheme is employed for variable

frequency operation, for the lowest speed range only
IEE Proc.-Electr. Power Appl., Vol. 150, No. 5, September 2003

INV3 will be switching (two-level mode); in next range

only INV3 and INV4 (three-level mode), and in the
penultimate range INV2, INV3 and INV4 (four-level
mode) will be switching. If conventional SPWM
was used at the two lower speed ranges, INV3 and INV4
have to be switched (as the inverter is in three-level
mode for these ranges) and in the two upper speed ranges
all the inverters have to switch, as the inverter is in the velevel mode for these speed ranges. When the motor
accelerates to the rated speed, this modied PWM will
take the motor through two, three, four and ve-level
operation whereas conventional PWM will result only in
535

three-level and ve-level operation. Therefore this modied

method of progressive discrete shifting of the modulating
signal results in a reduced switching loss in the lower speed
ranges.
5

Experimental results

The proposed dual inverter is implemented and tested with

a 1.5 kW open-end winding induction motor. The openloop v/f controller based on multilevel-carrier-based SPWM
is implemented on a TMS320F240 digital signal processor
platform. The ratio of carrier frequency to modulating
signal frequency is 45 for all ranges of operation.
Experiments are done by running the four inverters
INV1, INV2, INV3, and INV4 with 100 V Vdc =4 so that
the equivalent DC-link voltage is 400 V. Figure 5a shows
the motor phase voltage vA2A4 in the lowest speed range
where the inverter is operating in the two-level mode. In this
case, inverter B is switching in the two-level mode between
Vdc =2 (200 V) and Vdc =4 (100 V) as seen in the pole voltage
waveform vA4O0 (Fig. 5b), and inverter A is clamped to zero.
Figure 6a shows the motor phase voltage in the next speed
range and inverter B is now in the three-level mode,
switching between 0, Vdc =4 (100 V) and Vdc =2 (200 V) as
seen from the pole voltage (Fig. 6b) whereas inverter A is
still clamped to zero. Figure 7a shows the motor phase
voltage in next speed range in four-level operation. The
inverter A is switching in the two-level mode between 0 and
Vdc =4 (100 V) (Fig. 7b), and inverter B is switching in the
three-level mode (Fig. 7c). Figure 8a shows the motor phase
voltage in the nal speed range in ve-level operation, as
inverter A is switching in the three-level mode between 0,
Vdc =4 (100 V) and Vdc =2 (200 V) (Fig. 8b), and inverter B is
switching in the three-level mode (Fig. 8c). Pole voltages are
taken with reference to O or O0 , points which are isolated.
The pole voltage waveforms therefore were taken separately
and hence do not show the phase relation between the two
pole voltages. The simulation result presented in Fig. 8d
shows the phase relation of the pole voltages of the
inverters. Figures 9a9d show the motor current at the four
speed ranges. Figures 10a10d show the A-phase reference
waveforms and the corresponding levels generated by the
controller (taken as DAC outputs from the DSP controller)
during different speed ranges. Figures 11a11d. show the

Fig. 6
a Motor phase voltage during three-level operation
x-axis 1 div 10 ms; y-axis 1 div 100 V
b Pole voltage of inverter B (three-level operation)
x-axis 1 div 10 ms; y-axis 1 div 100 V

Fig. 7
a Motor phase voltage during four-level operation
x-axis 1 div 5 ms; y-axis 1 div 100 V
b Pole voltage of inverter A (four-level operation)
x-axis 1 div 5 ms; y-axis 1 div 100 V
c Pole voltage of inverter B (four-level operation)
x-axis 1 div 5 ms; y-axis 1 div 100 V

Fig. 5
a Motor phase voltage during two-level operation
x-axis 1 div 10 ms; y-axis 1 div 100 V
b Pole voltage of inverter B (two-level operation)
x-axis 1 div 10 ms; y-axis 1 div 100 V
536

triplen content , VO0 O (measured between O and O0 points

in Fig. 1), in each level operation. Figure 12 shows the
harmonic spectrum of the machine phase voltage at the velevel operation.
IEE Proc.-Electr. Power Appl., Vol. 150, No. 5, September 2003

Fig. 9
a Motor phase current during two-level operation
x-axis 1 div 20 ms; y-axis 1 div 1 A
b Motor phase current during three-level operation
x-axis 1 div 10 ms; y-axis 1 div 1 A
c Motor phase current during four-level operation
x-axis 1 div 10 ms; y-axis 1 div 1 A
d Motor phase current during ve-level operation
x-axis 1 div 5 ms; y-axis 1 div 1 A

a Motor phase voltage during ve-level operation

x-axis 1 div 5 ms; y-axis 1 div 100 V
b Pole voltage of inverter A (ve-level operation)
x-axis 1 div 5 ms; y-axis 1 div 100 V
c Pole voltage of inverter B (ve-level operation)
x-axis 1 div 5 ms; y-axis 1 div 100 V
d Pole voltages of inverters A and B (ve-level operation): simulation
results
(i) Inverter A
(ii) Inverter B

ve-level inverter scheme uses the same number of switching

devices but employs fewer DC sources as the H-bridge
topology will need six DC supplies. The proposed inverter
does not experience neutral-point uctuation and the DClink capacitors carry only the ripple current as isolated DC
supplies are used for all the DC links. In the lower speed
ranges, one of the inverters is switching while the other
inverter is clamped to zero. Multilevel-carrier-based SPWM,
where a progressive discrete DC shift is added to the
reference wave depending on the speed range, allowing
operation in all levels including even-numbered levels, is
employed for the proposed work.

Fig. 8

Conclusions

An open-end winding induction motor drive, where the

induction motor is fed by two three-level inverters from
both ends, results in voltage-space phasors identical to a
ve-level inverter. The three-level inverters used are realised
by cascading two two-level inverters. This structure does not
require the neutral clamping diodes and can be easily
realised using conventional two-level power circuits. When
compared with the series connected H-bridge, the proposed
IEE Proc.-Electr. Power Appl., Vol. 150, No. 5, September 2003

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PWM inverter, IEEE Trans. Ind. Appl., 1981, 17, (5), pp. 518523
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10571069
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537

Fig. 11
a Triplen voltage Voo0 (two-level operation)
x-axis 1 div 10 ms; y-axis 1 div 100 V
b Triplen voltage Voo0 (three-level operation)
x-axis 1 div 10 ms; y-axis 1 div 100 V
c Triplen voltage Voo0 (four-level operation)
x-axis 1 div 10 ms; y-axis 1 div 100 V
d Triplen voltage Voo0 (ve-level operation)
x-axis 1 div 5 ms; y-axis 1 div 200 V

Fig. 10
a
b
c
d

A-phase reference wave and levels (two-level)

A-phase reference wave and levels (three-level)
A-phase reference wave and levels (four-level)
A-phase reference wave and levels (ve-level)

5 Stemmler, H., and Guggenbach, P.: Congurations of high-power

voltage-source inverter drives. Proc. EPE Conf., Brighton, UK, 1316
September 1993, pp. 712
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Space vector PWM control of dual inverter-fed open-end
winding induction motor drive, EPE J., 2002, 12, (1), pp. 918
7 Shivakumar, E.G., Somasekhar, V.T., Mohapatra, K.K., Gopakumar,
K., and Umanand, L.: A multilevel space-phasor based PWM strategy
for an open end winding induction motor drive using two inverters
with different DC-link voltages. Proc. IEEE Conf. PEDS, Bali,
Indonesia, 2225 October 2001, pp. 169175
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538

Fig. 12 Harmonic spectrum of machine voltage during five-level

operation: experimental result

8 Appendix

8.1 Motor specification

1.5 kW 400 V 50 Hz 4pole cage motor
J 0.0195 kgm2; Rs 2.08 ohm; Rr 1.9 ohm; Lr 0.28 H;
M 0.272H; Ls 0.28H
IEE Proc.-Electr. Power Appl., Vol. 150, No. 5, September 2003