ECE 614 Fall 2011

Justin D. Butterfield

12-Bit Pipelined ADC Design Project

Justin D. Butterfield
Boise State University
December 15, 2011

1. Introduction
The goal of this project is to design a 12-bit pipeline analog to digital converter (ADC). The pipeline ADC design is to
use 1.5 bits/stage and capacitor error averaging. The ADC will operate with a maximum clock frequency of 100MHz, a
VDD of 1V, and a maximum VREF range from 0V to 1V. The design will be verified using ideal components in Spice
simulation to focus the design effort on the pipeline ADC architecture rather than on the Op-amps and comparators
themselves. Using ideal components will also keep the simulation times reasonable.
The purpose of analog to digital converts is to sample and digitize an analog signal. The more precisely the analog signal
is converted to digital, the more information can be obtained from it. It is also desirable to convert high bandwidth or
high frequency analog signals; thus, ADCs must be capable of a fast sampling rate as well being accurate. The pipeline
ADC is the architecture of choice for applications that require both speed and accuracy and where latency is not concern.
The basic idea behind the pipeline ADC is that each stage will first sample and hold the input then compare this to VREF/2.
If the input is greater than VREF/2, output a 1 for that stage and pass the input voltage directly to the next stage. If the input
is less than VREF/2, output a 0 for that stage and multiply the input voltage by 2 before passing it to the next stage. Figure
1 shows the block diagram for this basic operation.

Figure 1 Pipeline ADC Block Diagram [1]

There are a few challenges with the basic pipeline ADC architecture that this project will attempt to address. Before
looking at the sources of error, it is worth noting that an error in the early stages of the pipeline will propagate through the
pipeline affectively being amplified by 2 by each successive stage. Errors can be created by the comparators not
switching at the correct point. This means that the comparator may have some offset which will result in it making the
wrong decision. The sample and hold may also have some offset causing the wrong voltage to be passed to the
comparator which will result in the same problem of the comparator making a wrong decision. The other source of error
is the multiply by 2 function, because it is difficult to multiply by a gain of exactly 2. These limitations with real op-amps
and comparators will result in integral nonlinearity (INL) and differential nonlinearity (DNL) errors.
This design requires 12-bit resolution. This means that there will be 212 or 4096 possible output bit combinations.
Assuming a VREF of 1V, 1LSB or the level of analog resolution is given by
244

(Eq. 1)

To correct the errors caused by the offsets in the comparators and the sample and hold op-amps, a technique called 1.5
bits/stage will be used. The name 1.5 bits/stage is based on the fact that each stage has an output with three possible cases
consisting of a and b signals, where ab can be 00, 01, or 11. The 1.5 bits/stage algorithm works as follows:
1

ECE 614 Fall 2011

If

Justin D. Butterfield

, then

, then

If
If

00 and

, then

2
01 and

11 and

The ideal transfer curve for the 1.5 bits/stage of vin versus vout is shown in Figure 2. And, the relationship between vin and
vout can be expressed as
.

(Eq. 2)

Figure 2 1.5 Bits/Stage Transfer Curve (Single-ended) [1]

Using 1.5 bits/stage corrects reasonable comparator offsets by building in error correction with the extra half bit
resolution. Only strings of 01 output are valid. For instance, a 00 cannot be followed by another 00 output, and the same
is true for 11 output. This is because the subtraction or addition of VCM is done prior to the multiplication by 2. The
consequence of this error correction is that extra logic is required to take into account the output of the next stage and get
the final digital output code. The logic schematic will be shown in the design considerations section, but it basically does
the following logic functions, where denotes exclusive OR (XOR):
.
.

and

(Eq. 3)

and

and
.

(Eq. 4)

(Eq. 5)

Also note that the output at this point has a word size of N + 1 where bN is given by
.

(Eq. 6)

Finally, the binary output word needs to have the offset of VCM 0.5 LSB subtracted from it where this offset can be
expressed as:
0.5

001111

(Eq. 7)

ECE 614 Fall 2011

Justin D. Butterfield

The simulation results in the Design Considerations section will show that comparator offset is removed by the error
correction of 1.5 bits/stage, but the pipeline ADC still requires a precise multiply by 2. To achieve a more precise
multiply by 2, a technique called capacitor error averaging will be used. This technique uses a modified bottom plate
sampling switched capacitor op-amp circuit with an ideal gain of 2 as is shown in Figure 3. This circuit works by
sampling and holding the input, but instead of sampling again the circuit swaps the positions of the C and C+C
capacitors. The outputs of the amplify and hold phases will then need to be averaged by another bottom plate sample and
hold circuit (not shown in Figure 3). The goal is that any mismatch in the capacitance of capacitors will be averaged out
by using both capacitors for the multiplication and averaging the result.

Figure 3 Capacitor Error Averaging Sample and Hold [1]

The cost of this capacitor error averaging is the added design complexity. There is an extra op-amp and set of switched
capacitors for the averaging stage. This will result in more current draw and increase the noise contribution at each stage;
although, some of the noise may be canceled out by the averaging action. The other drawback is the need for a three
phase non-overlapping clock as shown in the timing diagram at the bottom of Figure 3. This three phase clock must be
generated from the input clock which results in a reduction in the sampling rate to less than the input clock rate.
Although, the stages can share clocks as will be shown later, there is also a latency penalty for using capacitor error
averaging.
An additional goal of this project, beyond the design of the 12-bit ADC, is to investigate whether capacitor error
averaging provides any advantage when using op-amps with low open loop gains. The output error with finite gain will
be derived based on conservation of charge. Simulations will also be performed looking at the effect of finite gain on the
error of the multiply by 2 performed by the sample and hold.

ECE 614 Fall 2011

Justin D. Butterfield

2. Design Considerations
The first step in the design is to setup the comparators and multiplexers for the 1.5 bits/stage operation. Figure 4(a) shows
the schematic of the block that includes the comparators and multiplexers. The inputs to the cell are the differential
sampled analog signal from the previous stage. The outputs of the cell are the a and b digital codes from the output of the
comparators and the VCIP and VCIM voltages that will be added to the input voltage before being multiplied by 2. Note that
the outputs of the comparators are connected to a latch with a delayed clock to prevent comparator metastability from
resulting in a timing error. Figure 4(b) shows the simulation results for this cell when a differential ramp voltage is
applied to the inputs. The simulation results show that at an input differential voltage of -250mV b goes to a 1 and VCIP
and VCIM both go to VCM. At the input differential voltage of 250mV, a goes to a 1, VCIP goes to 2VCM = 1V and VCIM goes
to 0V. Figures 5(a) and (b) show the schematic details of the multiplexer and 2-to-4 decoder which were created for this
design.

Clk

Qi

am

VDD

Clk

Qi

bm

S1
S0

VDD

C1
10p

S0
S1

Vcm
Out

Clk2

Clk

A1

am
bm

VDD

VDD +
Ideal comp.
Clk +

Mux

I3
I2
I1
I0

2Vcm

VDD Clk2

VDD Clk
-

VDD
R1

A2

Clk

C2
10p
Vcim

100

Clk2

V(vcip)

V(vcim)

V(a)

V(b)

1.0V
0.9V
0.8V
0.7V
0.6V
0.5V
0.4V
0.3V
0.2V
0.1V
0.0V

I3
I2
I1
I0

a
b

Out

Mux

VDD +
Ideal comp.
Clk +
Ref

Vcip

VDD

100
VDD

Vinp

R2

VDD

VDD
Vinm

1.0V
0.9V
0.8V
0.7V
0.6V
0.5V
0.4V
0.3V
0.2V
0.1V
0.0V

TD=500ps TD=500ps

500mV
400mV
300mV
200mV
100mV
0mV
-100mV
-200mV
-300mV
-400mV
-500mV
0.0s

V(vinsp)-V(vinsm)

0.2s

0.4s

0.6s

0.8s

1.0s

1.2s

1.4s

1.6s

A1
A0

D3
D2
D1
D0

Decoder
2-4

S1
S0

(a) Comparator and Multiplexer Schematic

(b) Transfer Simulation
Figure 4 1.5 Bits/Stage Schematic and Simulation

I0

I1

VDD

A0

VDD

A1

Out
I2

I3

A5

A1

D0

A6

A2

D1

A3

D2

A4

D3

VDD

VDD

(a) Multiplexer Schematic Detail

(b) 2-to-4 Decoder Schematic Detail
Figure 5 Multiplexer and Decoder Detail

1.8s

2.0s

ECE 614 Fall 2011

Justin D. Butterfield

phih

phih

The next major cell to design is the capacitor error averaging sample and hold with a multiplication by two and the
addition/subtraction of the VCIP and VCIM. Figure 6 shows the schematic of this capacitor error averaging block. The
inputs to this cell are the differential analog voltage from the previous stage and the VCIP and VCIM outputs from the
multiplexers. The output of this stage is the vout from Eq. 2 and is the differential output of a given stage, which will be
the analog input to the next stage. Figure 7(a) shows the simulations results for a vout transfer curve of this single stage
where the differential input is a ramp from 0V to 1V as shown in Figure 7(b). Figure 7(b) also shows how VCIP and VCIM
are changing in relation to the input and output transfer curve. An important consideration for the design of this cell is the
size of the capacitors. The minimum size of the capacitors is determined by kT/C noise which must be less than 0.5 LSB
for the maximum operating temperature. Assuming a maximum operating temperature of 100C, the capacitors must be
larger than 0.35pF for the ADC to be 12-bit accurate. Thus, 1pF capacitors should give some margin while not being too
large.
VDD

phis

phis

VDD

CFT
1.00p
CIT

Vcip

CIB
1.00p

phih

Vinm2

+
Ideal op-amp
+

Vopm

VDD

VDD

CIB1

VDD

CFB

VDD

Vopp
VCM

phia

VDD

+
Ideal op-amp
+

phis

VDD

Vinp1

VDD
Vcim

1p

phih

Vinm1

phia

1.00p

2.00p
CIT1

VDD

VDD
VDD

VDD

VDD

1.00p

Vinm
VDD

phia

CFB1

VDD

2.00p

VDD

Voutp

VDD
Voutm

phih

1.00p

VDD

Vopp2
VCM
Vopm2

phia

VDD

CFT1

Vinp2

phih

VDD

VDD

phih

VDD
Vinp

phia

phia

phia

VDD

phih

VDD
VDD

Figure 6 Capacitor Error Averaging Sample and Hold

V(vinp2)-V(vinm2)

500mV

V(vicm1)

1.0V

V(vcip1)

0.9V
0.8V

400mV

0.7V
0.6V

300mV

0.5V
0.4V

200mV

0.3V
0.2V

100mV

0.1V
0.0V

0mV

V(vinp1)-V(vinm1)

500mV
400mV

-100mV

300mV
200mV

-200mV

100mV

-300mV

-100mV

0mV

-200mV

-400mV

-300mV
-400mV

-500mV
0.0s

0.2s

0.4s

0.6s

0.8s

1.0s

1.2s

1.4s

1.6s

1.8s

2.0s

-500mV
0.0s

0.2s

0.4s

0.6s

0.8s

1.0s

1.2s

1.4s

1.6s

(a) 1.5 Bits/Stage S/H Transfer Curve Simulation

(b) Transfer Curve Simulation Input Stimulus
Figure 7 Single Stage Transfer Curve Simulation

1.8s

2.0s

ECE 614 Fall 2011

Justin D. Butterfield

The results in Figure 7 use an ideal clock from voltage sources, but the ADC system needs a way to take its 100MHz
input clock and convert it to a three phase non-overlapping clock. Figure 8(a) shows the schematic for the three phase
non-overlapping clock generation circuit. Figure 8(b) shows the simulation results for the three phase non-overlapping
clock generation circuit with a 100MHz input clock signal. Note, that the resulting three phase clock is one third the
frequency of the input clock. Thus, the sampling rate of the sample and hold will be one third the clock frequency or
33MS/s for a 100MHz clock. The extra Phi4 clock in Figure 8(a) will be used for the single-ended to differential
conversion.
V(clk)

1.1V
1.0V
0.9V
0.8V
0.7V
VDD

0.6V
0.5V
A3

A16
VDD Q

In1

0.4V
A1

A2

A4

A5

A17

A18

0.3V

Phi1

D
TD=25ps

Qi

Clk
VDD
Clk

0.1V

A6

In2

VDD Q

A7

A9

A10

A19

-0.1V

A20

V(phi1)

1.1V

Phi2
TD=25ps

TD=25psTD=25psTD=25psTD=25psTD=25psTD=25ps

V(phi2)

V(phi3)

1.0V

Qi

VDD
Clk

0.9V
0.8V
A13

0.7V
A11

In3

VDD Q

A12

A14

A15

A21

A22

0.6V
Phi3

TD=25ps

D
Clk

0.0V

A8

D
Clk

0.2V

TD=25psTD=25psTD=25psTD=25psTD=25psTD=25ps

0.5V

TD=25psTD=25psTD=25psTD=25psTD=25psTD=25ps

Qi

0.4V

Clk
In3
In3

A31
A23
A27
A28
A29
A26
A30
A25
TD=25psTD=25psTD=25psTD=25psTD=25psTD=25psTD=25ps
TD=25ps

A32

A24

0.3V
Phi4

TD=25ps

0.2V
0.1V
0.0V
-0.1V
4ns

8ns

12ns

16ns

20ns

24ns

28ns

32ns

36ns

40ns

44ns

VDD

phis1

VDD
R36
200k
VCM
R35
120k

phih1

phih2

phia1

R5

0.01

0.01

R3

R6

phis2

phih1

0.01

phih3

phis3
Rename Clocks
phia3

0.01

Vinp2
Vcip2
Vicm2
Vinm2

CLB1

VDD
Cap Err Avg S/H
Vinp
Vcip
Voutp
Vcim
Voutm
Vinm

VCM VCM

10p

CLT2
R11
R12
100
100

10p

Vinm3
CLB2

R13
R14
100
100

Vos3
Vcm VCM
2Vcm VDD
Ref Ref
Mux
1.5-Bit Comparator
b
Vinm
a
Vinp
VDD

Vcm VCM
2Vcm VDD
Ref Ref
Mux
1.5-Bit Comparator
b
Vinm
a
Vinp
VDD

Vos2

phia3 Clk

VDD
Cap Err Avg S/H
Vinp
Vcip
Voutp
Vcim
Voutm
Vinm

VCM VCM

10p

VDD

Vinp3
Vcip3
Vicm3

VDD

Vcim
Vcip

Vcm VCM
2Vcm VDD
Ref Ref
Mux
1.5-Bit Comparator
Vinm
b
Vinp
a
VDD
0

Vcim
Vcip

R2

R4
0.01

VDD
R9
R10
100
100

10p

Vos1

phia2 Clk

phis1

phia1 Clk

VDD

Vcim
Vcip

VCM VCM

CLT1

phis3 phis
phia3 phia
phih3 phih

VDD
Cap Err Avg S/H
Vinp
Vcip
Voutp
Vcim
Voutm
Vinm
phis2 phis
phia2 phia
phih2 phih

Vcip1
Vicm1

phia1

3Phase Nonoverlapping Clock Generation

VDD

R33
100k

Phi1 phis1
Phi2 phia1
Phi3 phih1

Clk Clk
Ref

phia2

VDD

R34
100k

R1
0.01

phis1 phis
phia1 phia
phih1 phih

VDD

VDD

(a) Schematic
(b) Simulation Results
Figure 8 Three Phase Non-Overlapping Clock Generation

Figure 9 First 3 Pipeline Stages Schematic

Figure 9 shows the first three stages of the pipeline ADC. The capacitor average error averaging sample and hold cells
are the top three blocks, and the comparator and multiplexer cells are the bottom three blocks. This schematic also shows
6

ECE 614 Fall 2011

Justin D. Butterfield

the VCM and Ref = 3VCM/4 generating resistive voltage dividers. The three phase clock generation is also shown. The
clock generation is done once to create one set of three phase clock signals, and those signals are renamed for use in the
subsequent stages of the pipeline. Figure 10 shows each of the three sets of three phase clock signals. The pattern of
clock signals is repeated for the additional stages of the pipeline.
3.3V

V(phih3)+2.2

V(phis3)

V(phia3)+1.1

V(phia2)+1.1

V(phih2)+2.2

V(phis2)

V(phis1)

V(phia1)+1.1

V(phih1)+2.2

1.7V

0.0V
3.3V

1.7V

0.0V
3.3V

1.7V

0.0V
32ns

40ns

48ns

56ns

64ns

72ns

80ns

88ns

96ns

104ns

112ns

120ns

128ns

Figure 10 Single Stage Transfer Curve Simulation

phi3

Another important component of the design is a circuit to take the single-ended analog input of ADC and convert it to a
differential analog signal with a common mode reference of VCM. The circuit shown in Figure 11(a) is one way to convert
the single-ended input to differential. The circuit is a basic bottom plate sample and hold that is modified with one of the
inputs tied to VCM and the other input broken up between the input and VCM. This is to keep the input common mode range
of the op-amp at or near VCM. Figure 11(b) shows the simulations results for this circuit which demonstrate that for an
input ramp of 0V to 1V the common mode voltage on the op-amp does not change. Errors arise with this circuit since it
has gain that is determined by CI/CF that is set to 1 for this application. Thus, there will be some gain error from this
circuit that will show up in the ADC output due to capacitor mismatch. Figure 12 shows the error from the single-ended
input to the differential output for three cases of CIT equal to 0.9pF, 1pF, and 1.1pF. This result shows the effect of the
gain error that will show up on the output of the ADC due to this capacitor mismatch.

phi1

phi2

VDD

VDD
Vin

VDD

CFT

VCM
1p

VDD

phi3

CIT
{CIT}

Vinm

phi3

VDD

VCM

CIB

VDD

CFB

1p

1p

VDD

Voutp
Voutm

phi1

VDD

Vopm

VDD

VDD
phi3

No connection
but to each other

Vopp
VCM

Vinp

VDD

+
Ideal op-amp
+

VDD

(a) Schematic
(b) Simulation Results
Figure 11 Single-Ended to Differential Sample and Hold

ECE 614 Fall 2011

Justin D. Butterfield

Figure 12 Single-Ended to Differential Gain Error Simulation Results

af1p54
b1p54

af1p53
b1p53

af1p52
b1p52

A1
VDD

Cout

c4

bout4

c3

Adderbit
Cin

Cout

S
bout3

c2

VDD

a1p53
BitB
af1p54_b1p54
BitA

A10
VDD

a1p52
BitB
af1p53_b1p53
BitA

VDD

Adderbit
Cin

Cout

Cin

c1

bout2

bout1

VDD

Adderbit
A4

bout0

VDD

a1p51
BitB
af1p52_b1p52
BitA

A3

A2

af1p51_b1p51
A8

A6

af1p50
b1p50
a1p50

af1p51
b1p51

Before cascading the stages of the pipeline together, the design needs to implement the logic specified in Equations 3
through 6. Figure 13 shows how the design implements this logic using basic and full adders. Note that both true and
complement versions of a are required. Figure 13 only shows the first 5 least significant bits of the 13-bit word out of the
logic, but the logic is same for all bits except the first two bits and the last bit. The logic for the last 3 most significant bits
is shown in Figure 14.

Figure 13 Logic to Combine the First 1.5 Bit/Stage Outputs

After the a and b outputs of the 1.5 bits/stage are combined into a binary word, the logic needs to subtract VCM 0.5 LSB
as described in Equation 7 from the digital output code. The equivalent operation is to add the negative value of this to
the binary output. This way, the full adders can be used. The 13-bit binary twos complement of VCM + 0.5 LSB is
1100000000001. The schematic that adds this as a hard coded value to the output word is shown in Figure 15.

VDD
b5 BitA
BitB

S s0

VDD
VDD
Adderbit

Cout
S s10

VDD

Cin

Cout

VDD

S s5

b9 BitA
BitB

Cout
S s9

VDD

Cin

VDD
Cout

Cin

Figure 14 Logic to Combine the Last 1.5 Bit/Stage Outputs

b10 BitA
BitB

Cin

VDD
b4 BitA
BitB

Adderbit

bout12

Adderbit

A16

VDD

VDD

S s6
Cin

Cin

b0 BitA
VDD BitB

Cout

Cout

VDD

S s4

b8 BitA
BitB

VDD

S s1

S s11

Cout

Cin

S s8

VDD
b12 BitA
VDD BitB

Cin

Adderbit

Cout

Cout

Cin

VDD

c11

bout11

bout10

VDD
b6 BitA
BitB

Adderbit

VDD
Adderbit

b1 BitA
BitB

b11 BitA
VDD BitB

VDD
S s2

VDD

Cout

Cout

Adderbit

VDD

a1p511
VDD

VDD

VDD

VDD

S s7
Cin

Cin

Adderbit
c10

Cin

Cout

Cin

Adderbit
c9

VDD
b2 BitA
BitB

Adderbit

A15
a1p510
BitB
BitA af1p511_b1p511

VDD

VDD

BitB a1p59
BitA af1p510_b1p510

A14

Cin

Cout

Adderbit

VDD
b7 BitA
BitB

Adderbit

S s3

Adderbit

Cout

Adderbit

Adderbit

VDD

af1p511
b1p511

VDD
b3 BitA
BitB

VDD

Justin D. Butterfield

af1p510
b1p510

ECE 614 Fall 2011

Cout
S s12
Cin

Figure 15 Subtract VCM Cell Schematic

The design cannot simply take the a and b outputs of each stage and directly apply them to the logic shown in Figures 13
and 14, because the pipeline processes the analog signal stage by stage each on a different clock cycle. The problem is
that the data is available first for the MSB stages and is available many clock cycles later for the LSB stages. The solution
is to add latches to delay the data for each stage of the pipeline to match the data coming out of the last stage. This way,
the data for each stage is available at the same time for the logic perform is function. Since the stages are sharing the
three phase clocks for the capacitor error averaging, the clocking of the data is not 1-to-1. This means that the first stage
does need 12 latched clock delays to match the output of the 12th stage. Table 1 shows the number of flip-flops this
design used to time align the a and b data going into the adder logic.

LSB

1
2
3
4
5
6
7
8
9
10
11
12

#FFDelays
8
8
7
6
6
5
4
4
3
2
2
1

VDD

Vin

12-bit ADC

Stage

Clock
Vrefp
Vrefm

Significance
MSB

Table 1 Logic to Combine the Last 1.5 Bit/Stage Outputs

B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0

Figure 16 Subtract VCM Cell Schematic

The top level design symbol is shown in Figure 16, and the top level design schematic is shown in Figure 17. Although
the details cannot be seen from the schematic, the Figure does show how the different number of flip-flops are connected
to the outputs of each stage. Additionally, it shows how some to the pieces are connected together. The single-ended to
differential conversion stage is first followed by 12 stages of the sample and hold and comparators with multiplexer
blocks. The complete digital logic for combining the a and b outputs of the 1.5 bits/stage comparators is at the bottom
right. The subtraction cell and a final 12-bit register are directly above the digital logic. The purpose of the final 12-bit
register is to synchronize the data to the clock at the final output, which is necessary since real adders will have some
delay.
9

Justin D. Butterfield

R4

R1

VDD

Vrefp

Vrefp

ECE 614 Fall 2011

phis1

phia2

phis1

phih3
0.01

0.01
VDD
R2

VDD

VDD

VDD

phih

phia

phis

Ref

VCM

Ref

Vcm

Vinp

2Vcm

Vinm

VDD

Mux
1.5-Bit Comparator

Vcip

Vcim

VDD

D
Q
a1p50

VDD

Clk

b1p50

Qi

phia2

af1p50

Clk

VDD

Qi

VDD

Ref
Ref

phia1

phis1

phih

VDD

10p

VDD

Q
a1p51

VDD

VDD
bout12
bout11
bout10

VDD

bout9

a1p54

b12

b9
b8
b7

bout6

b6

bout5

b5

bout3
bout2

VDD

b11
b10

bout8
bout7

b4

D12

s12

VDD

Q12

s11

D11

Q11

s10

D10

Q10

D9

s9

Subtract
VCM

Q9

b11
b10
b9

s8

D8

Q8

b8

s7

D7

Q7

b7

s6

D6

Q6

b6

s5

D5

Q5

b5

D4

s4

Q4

b3

s3

D3

Q3

b2

s2

D2

Q2

b1

s1

D1

Q1

b0

s0

D0

Q0

b4
b3
b2
b1
b0

b1p511

af1p511

b1p510

af1p510

b1p59

af1p59

b1p58

af1p58

b1p57

af1p57

b1p56

af1p56

b1p55

af1p55

b1p54

af1p54

b1p53

af1p53

b1p52

af1p52

A15

a1p511

a1p510
BitB

VDD

VDD

VDD

Adderbit

BitA

af1p511_b1p511

A14
a1p59
BitB

VDD

Adderbit

BitA

af1p510_b1p510

A13
a1p58

af1p59_b1p59
BitA

BitB

VDD

Adderbit

VDD

VDD

BitB

VDD

Adderbit

BitA

a1p57

af1p58_b1p58

A12

A9
a1p56
BitB

VDD

VDD

Adderbit

BitA

af1p57_b1p57

A7
BitA

VDD

Adderbit

VDD

BitB

VDD

a1p55

af1p56_b1p56

A5
a1p54
BitB

VDD

Adderbit

BitA

af1p55_b1p55

A1
a1p53
BitB

VDD

VDD

VDD

Adderbit

BitA

af1p54_b1p54

A10
af1p53_b1p53

a1p52
BitB

VDD

Adderbit

BitA

a1p51

af1p52_b1p52
BitA

BitB
A3

A2

VDD

VDD

af1p51_b1p51

A8

A6

a1p50

b1p50

af1p50

b1p51

af1p51

phia2

Clk

b1p54

CLB13

VDD

bout1

VDD

Adderbit
c11

bout12

bout11

bout10

bout9

bout8

bout7

bout6

bout5

bout4

bout3

bout2

bout1

bout0

b1p511

A16

Cin

c10

Cout

Cout

Cin

c9

Cin

c8

Cout

Cout

c7

Cin

Cout

c6

Cin

Cout

c5

Cin

Cout

c4

Cin

Cin

c3

Cout

Cout

Cin

c2

Cin

A4

VDD

Q
a1p510

100

VDD

bout0

Cout

Qi

Qi

Q
b1p510

a1p511

af1p510

Qi

af1p511

Qi

R32
100

phih1

phia

phis

phia3

phis3
VCM

VDD

Vcm

2Vcm

Vinm

VDD
b

Mux
1.5-Bit Comparator

Vinp

phia2

VDD

D
VDD
Q

Qi

Qi

Q
a1p52

Vcim

D
phia2

VDD

phia2

Clk

Clk

VDD

VDD

VDD

Qi

Clk

Qi

phia2

phia2

Clk

VDD

VDD

Clk

phia1

VDD

VDD

c1
Q

af1p54

a1p55

b1p55

af1p55

D
Q
a1p56

VDD

Clk

Clk

VDD

Qi

Qi

phia2

VDD

b1p56

VDD

phia2

af1p56

D
Clk

Q
a1p57

VDD

Qi
af1p57

Clk

VDD
Q
b1p57

Qi

VDD

Qi

phia2

phia2

Clk

VDD

VDD

Q
Q

VDD

Qi

a1p58

Clk

VDD

phia2

Qi

phia2

VDD

Clk

VDD

af1p58

Clk

VDD
Q

Qi

b1p58

VDD
Q
a1p59

VDD

phia2

Qi

phia2

VDD

VDD

Clk

D
Clk

phia2

VDD

phia2

VDD

Qi

VDD

Qi

VDD

Clk

VDD

Clk

VDD

Qi

b1p59

af1p59

Qi

Qi

VDD
Q
D
VDD
Q
D
VDD

VDD

Clk

Clk

VDD

phia2

Qi
VDD

Qi

phia2

phia2

VDD

phia2

VDD

Clk

VDD

Q
VDD
Q

Qi

Qi
D

VDD
Q

Qi
D
Clk

phia2

phia2

phia2

VDD

VDD

Clk

D
VDD

VDD

Clk

Clk

VDD

phia2

Q
D
VDD
Q

Qi

VDD
Q

Qi
D

VDD

Clk

VDD

Qi

phia2

Qi
Clk

VDD

phia2

phia2

Clk

Clk

phia2

VDD

VDD

Clk

VDD

Q
D
VDD
Q

Qi

phia2

Qi

phia2

phia2

VDD

VDD

VDD

D
Clk

VDD

phia2

VDD

Clk

D
Clk

Clk

phia2

VDD

Clk

VDD

Qi
phia2

Voutm

Vinm

VDD

a1p53

D
Q

Qi

VDD

D
VDD
Q

Qi

D
VDD

Qi

D
VDD

Qi

D
D
Clk

VDD

phia2

VDD

Qi

VDD

D
Clk
Clk

VDD

phia2

Qi

phia2

Voutp

Vcim

Vos12

bout4

phia2

R31

Vcip

VCM

VCM

10p

Vcip

Clk

b1p51

Qi
af1p52

phih3

phih

phia

phis

VDD
Q

Vinm12
CLB12

af1p51

VDD

VCM

Ref
Ref

Vcm

Vinp

2Vcm

Vinm

VDD

Ref

Mux
1.5-Bit Comparator

Vcip

phia3

D
Clk

VDD

VDD

Clk
Qi

VDD

VDD

Ref

Vicm12

100

10p

Vinp
Vcip12

R30
100

Vos11

Qi

phia2

phia2

Clk

Clk

VDD

VDD

VDD

b1p52

VDD

Voutm

Vinm

VDD

Voutp

Vcim

CLT13

VDD
Cap Err Avg S/H

Vinp12

10p
R29

Vcip

VCM

VCM

10p

Qi

phia2

phia2

Qi

phia2

phis2

phih
VDD

VDD

D
Qi
af1p53

Vinm11
CLB11

Clk

Vcim

phia2

VCM
Vcm

Vinp

2Vcm

Vinm

VDD

Mux
1.5-Bit Comparator

VDD

Q
VDD
Q

Qi
Clk
Qi

VDD

Q
Q

Vicm11

100

Vos10

D
phia2

VDD

Clk
Clk

VDD

Qi

phia2

phia2

VDD

VDD

Vcip11

R28
100

phih2

phia

phis

phia1

phis1

Voutm

Vinm

Vcip

Vcim

Clk

Ref

Voutp

Vcim

CLT12

VDD
Cap Err Avg S/H
Vinp

Vinp11

R27

Vcip

VCM

VCM

10p

Clk

Clk

phia2

VDD

Clk

VDD

Qi

phia2

phia2

D
VDD

phih1

phih

phis

phia

VDD

VDD

D
VDD

Vinm10
CLB10

b1p53

VDD

Ref

VDD

Q
D
VDD
Q
D
VDD

Qi

Qi

VDD

VDD

VDD
VCM
Vcm

Vinp

2Vcm

Vinm

VDD

Mux
1.5-Bit Comparator

phia2

phia1

Vcim

Vcip

VDD

Vicm10

100

10p

Vinp
Vcip10

R26
100

Vos9

D
phia2

Qi

Qi

VDD
Q
VDD

Voutm

Vinm

VDD

VDD

VDD

D
Clk

Clk

Clk

phia2

VDD

Clk

VDD

phia2

phia2

Qi

phia2

Qi
Clk

VDD

VDD

VDD

Clk

phia2

phia2

Clk

VDD

VDD

Clk

Ref
Ref

VDD
Q

Voutp

Vcim

CLT11

VDD
Cap Err Avg S/H

Vinp10

10p
R25

Vcip

VCM

VCM

10p

Qi

VCM

VDD

Vcm

Vinp

Vinm

2Vcm

Mux

1.5-Bit Comparator

VDD
b

Clk

Vcim

phia3

D
VDD
Q

Qi

Qi

VDD

D
VDD

Qi

Qi

Vicm9
Vinm9
CLB9

Vos8

D
phia2

VDD

VDD

Qi

phia2

Clk

Clk
Clk

VDD

Qi

VDD

phia2

VDD

Qi

Clk

VDD

phia2

phia2

Clk

Clk

phia2

VDD

VDD

Clk

VDD

Vcip

Clk

Vcip9

R24
100
100

phia3

phih

Voutm

Vinm

phis3

phia

phis

phia2

phis2

Voutp

Vcim

CLT10

VDD
Cap Err Avg S/H
Vinp

Vinp9

10p
R23

Vcip

VCM

VCM

10p

Clk

phia2

phia2

D
VDD

Vinm8
CLB8

Qi

VDD

VDD

D
VDD

Vcip8
Vicm8

100

CLT9

VDD
Cap Err Avg S/H
Vinp

Vinp8

R22
100

phih3

Voutm

phih2

phih

phia

phis

phia1

phis1
Ref

VDD

VCM
Vcm

Vinp

2Vcm

Vinm

VDD

phia2

Ref

Mux
Ref
1.5-Bit Comparator

VDD

Vcim

VDD

D
VDD
Q

Qi

Qi

VDD

Qi

Qi

VDD

Ref

Voutp

Vcim

VCM

Vos7

D
phia2

VDD

VDD

Qi

phia2

Clk

VDD

Qi

VDD

Clk

Clk

phia2

VDD

Clk

VDD

VDD

Qi

phia2

phia2

phia2

Clk

Clk

VDD

VDD

VDD

Clk

phia2

phia2

Vcip

Clk

10p
R21

Vcip

Vinm
VCM

10p

Clk

VDD

VDD

D
VDD

Vinm7
CLB7

Qi

VCM
Vcm

Vinp

Vinm

2Vcm

Mux
1.5-Bit Comparator

VDD
b

Vcip

phia1

VDD

Qi

Vcip7
Vicm7

100

CLT8

VDD
Cap Err Avg S/H
Vinp

Vinp7

R20
100

phih1

phih

Voutm

Vos6

Qi

D
VDD

Qi
D
Qi

VDD

VDD

VDD
phia

phis

phia3

phis3

Voutp

Vcim
Vinm

Clk

phia2

Qi

VDD

VDD

Clk

VDD

Qi

Q
VDD
Q

Qi

phia2

10p
R19

Vcip

VCM

VCM

10p

phia2

VDD

Qi

Clk

VDD

phia2

phia2

Clk

phia2

VDD

VDD

Clk

Clk

VDD

D
VDD

Vinm6
CLB6

Clk

Clk

phia2

VDD

phia2

VDD

Qi

Vicm6

100

phih3

phih

phis

Vcim

Clk

Ref

D
VDD

VDD

Qi

phia3

VDD

VDD

Ref

phia2

D
Qi

VDD

VCM
Vcm

Clk

VDD

Vcip6

R18
100

Vos5

Vinp

2Vcm

Vinm

VDD

phia2

Clk

Mux
1.5-Bit Comparator

b
Clk

VDD

D
VDD

Qi

VDD

Voutm

Vinm

Vcip

Clk

phia2

VDD

Vcim

phia2

VDD

Qi

phia2

Q
VDD

Voutp

Vcim

CLT7

VDD
Cap Err Avg S/H
Vinp

Vinp6

R17

Vcip

VCM

VCM

10p

VDD

10p

Vinp
Vcip5
Vicm5

Vinm5
CLB4

Clk

VDD

VDD

phia2

Qi
Clk

VDD

Clk

D
VDD

phia2

Qi

phia2

VDD

D
VDD
Q

Qi

Qi

VDD

Qi

VDD

Clk

Ref

phia2

Qi

phia2

VDD

VDD

Ref

VDD

VDD

Clk

VDD

Qi

VDD

CLT6

VDD
Cap Err Avg S/H

Vinp5

R16
100
100

phis2

phis1
VCM
Vcm

phia2

D
Clk

phia2

VDD

Clk

VDD

Q
VDD

Voutm

Vos4

Vinp

Vinm

2Vcm

Mux

VDD

VDD

1.5-Bit Comparator

phia2

Qi

phia2

Q
VDD

Voutp

Vcim
Vinm

Vcip

Clk

Vcim

phia2

VDD

10p
R15

Vcip

VCM

VCM

10p

Clk

Clk

VDD

Q
VDD

Qi

Vcip4
Vicm4
Vinm4
CLB3

VDD

CLT4

VDD
Cap Err Avg S/H
Vinp

Vinp4

R14
100
100

Clk

phia2

phia2

Q
VDD

VDD

VDD

phia2

VDD

VDD
phih

Voutm

Ref

VDD

VCM
Vcm

Vinp

2Vcm

Vinm

VDD

Mux
Ref
1.5-Bit Comparator

VDD

Clk

Vcim

Vcip
phia2

Qi

phia1

VDD

D
VDD

VDD

Clk

Clk

VDD

phia2

Qi

Qi

phia2

Qi

Qi

D
VDD
Q

Qi

VDD

VDD

Clk

Clk

phia2

D
VDD

Qi

Clk

Clk

Clk

VDD

Qi

phia2

Clk

VDD

Qi

Voutp

Vcim

VCM

Vos3

Clk

Clk

VDD

Qi

Q
VDD

VDD

Clk

phia2

phia2

VDD

Clk

VDD

phia2

Qi

phia2

VDD

VDD

Clk
Clk

VDD

VDD

phia2

Qi

Vinp

Vinm

VDD

Ref

VDD

Ref

phia2

VDD

D
Clk

phia2

VDD

phia2

Qi

phia3

VCM
Vcm

2Vcm

1.5-Bit Comparator

Mux
Vcip

VDD

Clk
Clk

VDD

phia2

Qi

phia2

VDD

10p
R13

Vcip

Vinm
VCM

10p

Vos2

Vcim

Clk

Vinm3
CLB2

Vos1

phia2

Vicm3

100

CLT3

VDD
Cap Err Avg S/H
Vinp
Vcip3

R12
100

phis

Voutm

Vinm
VCM

VCM

phia

phi3

Vinm2

10p

phis

phi2

Voutp

Vcim

CLB1

Vinp3

R11

Vcip

Vicm2

100

VCM

phis2

phi1
phi4

phi4

phih1

Voutm

Vinm
VCM

phia3

0.01

10p

Vinp
Vcip2

R10
100

phia3

Vinm1

10p

Vinp2

10p
R9
Voutp

Vcim

CLB5
VCM

R6

CLT2

VDD
Cap Err Avg S/H

phis3

100

VCM

phis3
0.01

phih3

Vcip

phih

Voutm

Vcip1
Vicm1

phih1

VDD

VDD

Vinp1

R8
100

phia

10p
R7
Voutp

phis

SE2Diff
Fig30_35

phia2

Vin

phia1

phis2

phia

R3
0.01

CLT1

VDD
Cap Err Avg S/H
Vinp

phih2

Vin

Vrefm

Vrefm

VDD

CLT5

VDD

R5
phih2

0.01

phih1

phi4

Clk

phih1

Phi4

phia2

phia1

phia1

Phi3

phih2

phis1

Phi2

phih

Clk

3Phase Nonoverlapping Clock Generationt

Clk

120k

phia

Clock
Ref

R35

100k

phia1

Phi1

200k
VCM

R33

phih1

R36

100k

Qi

R34

Figure 17 Logic to Combine the First 1.5 Bit/Stage Outputs

3. Characterization Results
Figure 18 characterizes the delay or latency of the pipeline ADC. Figure 18(a) shows the simulation stimulus and output
of an ideal digital to analog converter (DAC) that converts the digital output code from the pipeline ADC back to analog
voltage. The input voltage is a step from 0V to 0.8V. Figure 18(b) gives the results of measuring from the time the input
pulses high to the time when the same pulse is seen on the output. These plots show a 300ns latency with an input clock
frequency of 100MHz, which means the latency is 30 clock cycles.
V(vin)

900mV

V(vout)

810mV
720mV
630mV
540mV
450mV
360mV
270mV
180mV
90mV
0mV
-90mV
300ns

360ns

420ns

480ns

540ns

600ns

660ns

720ns

780ns

840ns

900ns

(a) Latency Simulation Waveforms

(b) Latency Measurement
Figure 18 Latency Characterization Simulation Results

Figure 19 shows the simulation results for the ideal pipeline ADC with no comparator offsets, op-amp offsets, or capacitor
mismatches. Figure 19(a) shows the analog equivalent output of the pipeline ADC compared to the input ramp. The
results show that the output closely matches the input and there are no non-monotonicities. Figure 19(b) gives more
detailed perspective of the error between the input and output of the ADC or quantization error. This plot is generated by
subtracting the input from the output and also subtracting the static error due to the latency of the pipeline ADC. This
factor is based on the latency calculated from Figure 18(b) of 300ns and given the input ramp from 0V to 1V over 4us
which translates to about 75mV. Of course, there will always be some quantization error for an ADC since it has a finite
10

ECE 614 Fall 2011

Justin D. Butterfield

The steeper the input ramp voltage the larger difference between input and output, but ideally the peaks high should be at
0V. The results show that the INL and DNL error are good, but that there may be some gain error which is likely coming
from the initial single-end to differential sample and hold. Note that these results cannot be used to determine if the ADC
is 12-bit accurate since the ramp is not exercising all 4096 output word combinations.
V(vout)

1.0V

V(vin)

0.9V

6mV

0.8V

3mV

0.7V

0mV

0.6V

-3mV

0.5V

-6mV

0.4V

-9mV

0.3V

-12mV

0.2V

-15mV

0.1V

-18mV

0.0V
0.8s

1.3s

1.8s

2.3s

2.8s

3.3s

(a) Vout and Vin Plot

3.8s

V(vin)-V(vout)-75m

9mV

4.3s

4.8s

-21mV
0.8s

1.2s

1.6s

2.0s

2.4s

2.8s

3.2s

3.6s

4.0s

4.4s

4.8s

(b) Quantization Error Estimation Plot

Figure 19 Ideal Ramp Simulation

Figure 20 shows the output of the pipeline ADC with all the comparators having an offset on the positive terminal. The
green waveform is the baseline and has a comparator offset of 0V. The blue waveform has a comparator offset of 50mV.
And, the red waveform has a comparator offset of 75mV. Very little difference can be observed between the ideal case
and the offset cases. This proves that the 1.5 bit/stage and error correction logic are able to cancel out these offset levels
to a first order.
V(vout)

1.0V

V(vin)-V(vout)-75m

9mV
6mV

0.9V

3mV

0.8V

0mV
0.7V
-3mV
0.6V
-6mV
0.5V
-9mV
0.4V
-12mV
0.3V
-15mV
0.2V

-18mV

0.1V
0.0V
0.8s

-21mV

1.3s

1.8s

2.3s

2.8s

(a) Vout Plot

3.3s

3.8s

4.3s

4.8s

-24mV
0.8s

1.2s

1.6s

2.0s

2.4s

2.8s

3.2s

3.6s

4.0s

4.4s

4.8s

(b) Quantization Error Estimation Plot

Figure 20 Comparator Offset Simulation

Figure 21 shows the output of the pipeline ADC with all of the op-amps having an offset on the negative terminal. Again,
the green waveform is the baseline and has an op-amp offset of 0V. The blue waveform has an op-amp offset of 50mV.
And, the red waveform has an op-amp offset of 100mV. There are some small differences in the quantization error with
the op-amp offsets, but these are not significant.

11

ECE 614 Fall 2011

Justin D. Butterfield

V(vout)

1.0V

V(vin)-V(vout)-75m

12mV
10mV

0.9V

8mV
0.8V
6mV
0.7V

4mV
2mV

0.6V

0mV
0.5V
-2mV
0.4V

-4mV
-6mV

0.3V

-8mV
0.2V
-10mV
0.1V
0.0V
0.8s

-12mV

1.3s

1.8s

2.3s

2.8s

3.3s

(a) Vout Plot

3.8s

4.3s

-14mV
4.8s
0.8s

1.2s

1.6s

2.0s

2.4s

2.8s

3.2s

3.6s

4.0s

4.4s

4.8s

(b) Quantization Error Estimation Plot

Figure 21 Op-Amp Offset Simulation

Figures 22(a) and (b) show the output of the ADC and the quantization error with capacitor mismatches in all of the
sample and hold cells. Both the CIT and CIT1 capacitors in the sample and hold circuit shown in Figure 6 are varied. Both
capacitors are set to 1pF (displayed in green), 0.9pF (displayed in blue), and 1.1pF (displayed in red). Again, there are
some small differences in the quantization error with the op-amp offsets, but these are not significant.
V(vout)

1.0V
0.9V

6mV

0.8V

3mV

0.7V

0mV

0.6V

-3mV

0.5V

-6mV

0.4V

-9mV

0.3V

-12mV

0.2V

-15mV

0.1V

-18mV

0.0V
0.8s

1.3s

1.8s

2.3s

2.8s

(a) Vout Plot

V(vin)-V(vout)-75m

9mV

3.3s

3.8s

4.3s

4.8s

-21mV
0.8s

1.2s

1.6s

2.0s

2.4s

2.8s

3.2s

3.6s

4.0s

4.4s

4.8s

(b) Quantization Error Estimation Plot

Figure 22 Capacitor Mismatch Simulation

Figures 23(a) and (b) show the output of the ADC and an estimate for the quantization error with comparator offsets in the
first three pipeline stages. The comparator offset is set to 0V (displayed in green), 75mV (displayed in blue), and 150mV
(displayed in red). The 150mV offset case results in significant DNL errors at and around 0V, 250mV, 500mV and
750mV. These points make sense, because these are the points where the first three comparators make their decisions.
The 1.5 bit/stage error correction does help, but cannot completely remove this offset. The 75mV offset makes little
difference as is shown in Figure 20(b) where all the comparators have the same offset. Figures 23(c) and (d) show the
output of the ADC and the quantization error with comparator offsets in the last three pipeline stages. Interestingly, even
the offset of 150mV has little affect on the INL and DNL error when it is present in the last stages only.

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V(vout)

1.0V

V(vin)-V(vout)-75m

56mV
49mV

0.9V

42mV

0.8V

35mV

0.7V

28mV
0.6V
21mV
0.5V
14mV
0.4V
7mV
0.3V

0mV

0.2V

-7mV

0.1V
0.0V
0.8s

-14mV

1.3s

1.8s

2.3s

2.8s

3.3s

3.8s

4.3s

4.8s

(a) Vout Plot for First Three Comparators w/ Offsets

1.2s

1.6s

2.0s

2.4s

2.8s

3.2s

3.6s

4.0s

4.4s

4.8s

(b) Quantization Error Plot for First Three Comparators w/ Offsets

V(vout)

1.0V

-21mV
0.8s

V(vin)-V(vout)-75m

12mV
9mV

0.9V

6mV

0.8V

3mV

0.7V

0mV
0.6V
-3mV
0.5V
-6mV
0.4V
-9mV
0.3V

-12mV

0.2V

-15mV

0.1V
0.0V
0.8s

-18mV

1.2s

1.6s

2.0s

2.4s

2.8s

3.2s

3.6s

4.0s

4.4s

4.8s

-21mV
0.8s

1.2s

1.6s

2.0s

2.4s

2.8s

3.2s

3.6s

4.0s

4.4s

4.8s

(d) Quantization Error Plot for Last Three Comparators w/ Offsets

(c) Vout Plot for Last Three Comparators w/ Offsets
Figure 23 Simulation Results with Different Stage Offsets

Figures 24(a) and (b) show the output of the ADC and the quantization error with sample and hold capacitor mismatches
in the first three stages of the pipeline. Both the CIT and CIT1 capacitors in the sample and hold circuit shown in Figure 6
are varied. They are both set to 1pF (displayed in green), 0.5pF (displayed in blue), and 1.5pF (displayed in red). Both
cases of this high capacitor mismatch (50%) show increases in the INL and DNL error from the ideal case. While,
Figures 24(c) and (d) show the output of the ADC and the quantization error with sample and hold capacitor mismatches
in the last three stages of the pipeline. Both cases with this amount of capacitor mismatch show some increased INL and
DNL error, but both errors are much less significant when the capacitor mismatch is the last few stages.

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V(vout)

1.0V

V(vin)-V(vout)-75m

12mV
9mV

0.9V

6mV

0.8V

3mV

0.7V

0mV
0.6V
-3mV
0.5V
-6mV
0.4V
-9mV
0.3V

-12mV

0.2V

-15mV

0.1V
0.0V
0.8s

-18mV

1.3s

1.8s

2.3s

2.8s

3.3s

3.8s

4.3s

4.8s

-21mV
0.8s

(a) Vout Plot for First Three S/H Cap Mismatch

V(vout)

1.0V

1.2s

1.6s

2.0s

2.4s

2.8s

3.2s

3.6s

4.0s

4.4s

4.8s

(b) Quantization Error Plot for First Three S/H Cap Mismatch
V(vin)-V(vout)-75m

9mV

0.9V

6mV

0.8V

3mV

0.7V
0mV
0.6V
-3mV
0.5V
-6mV
0.4V
-9mV
0.3V
-12mV

0.2V

-15mV

0.1V
0.0V
0.8s

1.3s

1.8s

2.3s

2.8s

3.3s

3.8s

4.3s

4.8s

-18mV
0.8s

1.2s

1.6s

2.0s

2.4s

2.8s

3.2s

3.6s

4.0s

4.4s

4.8s

(c) Vout Plot for Last Three S/H Cap Mismatch

(d) Quantization Error Plot for Last Three S/H Cap Mismatch
Figure 24 Simulation Results with Different Stage Switched Capacitor Mismatch

4. Finite Gain Experiment

Thus far, the analysis and characterization of the design has assumed that the op-amps in the sample and hold circuit have
effectively infinite gain. This section attempts to examine the effects of finite open loop op-amp gain on the performance
of the sample and hold cell. Recall from Equation 2 that to get the vout of a pipeline stage, the vin must be multiplied by 2
and some value is subtracted or added based on the a and b outputs of the comparators. This subtraction or addition is
done with the VCI inputs to the sample and hold shown in Figure 6. The equation that ideally relates vout to vin in terms of
VCI is given by
.

(Eq. 8)

This equation assumes that there is no offset in the op-amps, the capacitors are exactly the same, and the op-amp gain is
sufficiently high. The hand derivations in Appendix A show that there is an error factor when the gain is finite. These
derivations assume that the gain of both op-amps is the same value of AOL, that there is no offset in the op-amps, and that
the capacitors are exactly matched to simplify the equations. The equation for the output of the averaging sample and
hold when the op-amps have finite gain is given by

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(Eq. 9)

This equation shows that the output of the sample and hold will be reduced by some factor that depends on the gain of the
op-amps. If the open loop gain is 100, the output swing of the sample and hold will be 96.1% of its ideal value. If the
open loop gain is 1000, the output swing of the sample and hold will be 99.6% of its ideal value. Figure 25(a) shows the
effect on the single stage transfer curve previously shown in Figure 7(a) when the op-amp gain is swept from 100 (plotted
in green), 1K (plotted in blue), 10K (plotted in red), and 100K (plotted in pink). Figure 25(b) is a zoomed in plot of
Figure 25(a) at the point where the error is at its maximum. These results show the relationship between the open loop
gain and the error on the output as Equation 9 predicts.
V(voutp)-V(voutm)

500mV

V(voutp)-V(voutm)

400mV

-477mV

300mV

-480mV

200mV

-483mV

100mV
-486mV
0mV
-489mV
-100mV
-492mV
-200mV
-495mV

-300mV

-498mV

-400mV

-501mV

-500mV
-600mV
0.0s

0.2s

0.4s

0.6s

0.8s

1.0s

1.2s

1.4s

1.6s

1.8s

2.0s

-504mV
495ns

500ns

505ns

510ns

515ns

520ns

525ns

530ns

535ns

540ns

545ns

550ns

(a) Vout Plot

(d) Zoomed Vout Plot
Figure 25 Capacitor Error Averaging Affect of Finite Op-Amp Gain

The characterization results of the 12-bit pipeline ADC have shown that the design is tolerant to op-amp offset and
capacitor mismatch in the sample and hold. The tolerance to capacitor mismatch is due to using the capacitor error
averaging sample and hold topology shown in Figure 6. The question that also arises is How does the performance of
the capacitor error average compare to a single stage sample and hold when the op-amp gain is low? Figure 26 shows
the topology for the single stage bottom plate sample and hold. This topology uses only one op-amp to do the sample,
hold, subtract and multiply by 2 operations. There is no swapping of the capacitors and no second stage to average two
output values, so this topology will be susceptible to capacitor mismatch error. Although it is not proven in the hand
calculations, it is presumed that since this topology has only one op-amp the error will be the square root of the error term
from Equation 9. This means that for the topology in Figure 26, the vout can be estimated by
.

(Eq. 10)

Figure 27(a) shows the maximum differential error for the single stage sample and hold in Figure 26, while Figure 27(b)
shows the maximum differential error for the capacitor error averaging sampled and hold. In these plots, the op-amp gain
is swept from 100 (plotted in green), 1K (plotted in blue), 10K (plotted in red), and 100K (plotted in light blue). These
results show that the single stage sample and hold topology has less error due to finite op-amp gain. The capacitor
averaging sample and hold has slightly less than twice the maximum error compared to the single stage sample and hold.
This makes sense based on Equations 9 and 10. If AOL is 100, the error term is 96.1% for the capacitor error averaging
case and 98.0% for the single stage case. This means that using capacitor error averaging has more of a decrease in
performance from finite op-amp gain than the standard single stage bottom plate sample and hold.

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Figure 26 Single Op-Amp Bottom Plate Sample and Hold [1]

1-(V(voutp)-V(voutm))

11mV

1-(V(voutp)-V(voutm))

18mV

10mV

16mV

9mV
14mV
8mV
12mV
7mV
6mV

10mV

5mV

8mV

4mV
6mV
3mV
4mV
2mV
2mV

1mV
0mV
0ns

20ns

40ns

60ns

80ns

100ns

120ns

140ns

0mV
0ns

20ns

40ns

60ns

80ns

100ns

120ns

140ns

(a) Single Stage Sample and Hold

(d) Capacitor Error Averaging Sample and Hold
Figure 27 Maximum Error for Finite Op-Amp Gain Sample and Hold

5. References
[1]

R. J. Baker, CMOS: Circuit Design, Layout, and Simulation 3rd ed. Jon Wiley and Sons Publishers, 2010. ISBN
978-0-0470-88132-3.

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A. Hand Calculations
First, consider the simple sample case:

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Next, consider the first stage of the capacitor error averaging sample and hold shown in Figure 6.

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Last, consider the averaging stage of Figure 6.

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22