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Figure1.
I. INTRODUCTION
Due to its simple arithmetic and robust properties, analog
PID controllers are applied in many areas. But nowadays it
can not keep pace with faster, cheaper, more stable and
more flexible requirements dictated by modern
applications. In recent years, digital controllers
implemented with DSP or FPGA have been conceived and
designed to improve performance. Implemented with these
fixed point devices, floating point arithmetic is usually
converted to fixed point format. However fixed point
format can not offer high precision and wide dynamic
range. At the same time, the process of a float-fixed
conversion is complex and the period is long.
In order to improve accuracy and minimize error, and to
reduce speed and complexity of conversion of floating
point format to fixed point, best-precision fixed point
arithmetic is conceived and applied to implementation of
PID controllers by FPGA circuitry because it excels one
with DSP in speed and stability.
This paper describes the process of converting analog
controllers to digital ones, presents both best-precision
fixed point arithmetic and the FPGA implementation details
of a digital PID controller.
u = K p e + K i e dt +K d
de
dt
Figure2.
384
Z2
Z
V i (s ) + 1 + 2 V d (s )
Z1
Z1
Input signal
6
C
1
1
= 2 + 1 +
+ R 2 C 1 s V i (s )
R1 C 2 C 2 R1 s
2.5
3.5
4.5
5
0
-10
0.5
1.5
2.5
3.5
4.5
5
-3
x 10
Figure4.
y ( n) = 0.01333[ vi (n ) - 2.5] + y ( n - 1)
R
C
1
vo (n ) = 2 + 1 vi (n )
[vo 2 (n 1) + Ts vi (n )]
R
C
C2 R1
1
2
III.
v (k ) .
FPGA IMPLEMENTION
(a)input signal
k =0
5
0
R C
1
[vo2(n 1) +Ts vi (n)]
vo(n) = 2 + 1 vi (n)
C2R1
R1 C2
R C
nTv
+1+ 2 + 1 vd C + s d
C2R1
R1 C2
(6)
R
C
nT v
R2C1 [vi (n ) vi (n 1)] + 1 + 2 + 1 vd C + s d
R1 C 2
C2 R1
0.5
1.5
2.5
3.5
4.5
5
-3
x 10
(b)output of the floating-point controller
10
0
-10
0.5
1.5
2.5
3.5
4.5
5
-3
x 10
(c)output of the 22-bit word length with 15 fractional bits fixed-point controller
10
0
-10
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-3
x 10
(d)absolute error of the 22-bit word length with 15 fractional bits fixed-point controller
0
-0.05
-0.1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
-3
x 10
Figure5.
-KR2/R1+C1/C2
-KSaturation
Scope
1/C2/R1
Add 3
Add 2
z
Delay 3
7.5
-K-
Vd +C 1+R2/R1+C1/C2
-KRamp
Figure3.
-5
Ts
1.5
-3
t
R
C
1
v o = 2 + 1 v i
vi d C
C2
C 2 R 1 0
R1
dv i
R
C
t
vd
R 2C1
+ 1 + 2 + 1 v d +
dt
R
C
C
1
2
2 R1
Pulse
Generator
x 10
-K-
0.5
R
C
1
1
+ 1 + 2 + 1 +
+ R 2 C 1 s V d (s )
R 1 C 2 C 2 R1 s
10
1/C2/R1*Vd *Ts
385
Figure6.
B. Basic modules
Adder and multiplier are basic modules in the digital PID
controller. In the design, attributes of operands are s16.5
best-precision fixed point format. The project is
programmed with VHDL, compiled and simulated with
Quartus 7.0, then implemented on a cyclone
EP1C6Q240C8 FPGA chip.
1) Adder: The addition of best-precision fixed -point
operands requires that the binary points of the addends
should be aligned[7]. The addition is then performed using
binary arithmetic. If the exponents are not equal, the binary
point of the smaller exponent should be shifted up by the
difference between the two exponents in order to offer high
precision. The relation of the operands and results can be
written as:
Nx<Ny
Z = [X 2 Ny-Nx + Y]2-Nz
8
Nz=Nx+L
9
Where, Nx Ny Nz are the exponents of X Y Z
separatelyL is the length of redundant sign bits of [X 2
Ny-Nx
+ Y].
Adding two operands in best-precision fixed-point
format can be implemented as follows: Firstly, compute the
difference between the two exponents and set it as zero if
any of two operands is zero. Secondly, send them to
corresponding registers according to the sign of the
difference (the operand whose exponent is smaller will be
sent to register A, another will be sent to register B).
Thirdly, the operand in register B is shifted to the left by
the difference. Fourthly, add the two operands and check
redundant sign bits number of the result and normalize it.
Finally, compute exponent according to Eq.(9). Redundant
sign bits counter designed by dichotomy uses 97 logic
elements with a latency of less than 4 clock cycles. The
Figure7.
Figure8.
386
(27955/28 )(17825/210)=30413/24
0
-5
-10
0.5
1.5
2.5
3.5
4.5
5
-3
x 10
0.01
0
-0.01
-0.02
0.5
1.5
2.5
3.5
4.5
5
-3
x 10
Figure9.
CONCLUSION
REFERENCES
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Beijing, 1988.6.
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[3] K.Shuang, Y.K.Xu, S.Jiang, Converting Analog Controllers to Digital
Controllers with FPGA. 9th International Conference on Signal
Processing, Proceedings [C],Oct. 2008.pp.486-489
[4] R. Cmar, L Rijnders, P Schaumont, S Vemalde, l Bolsens. A
methodology and design environment for DSP ASIC fixed point
refinement. Design Automation and Test in Europe Conference and
Exhibition 1999. Proceedings [C]. 1999. 211 -276.
[5] L B Jackson, On the interaction of roundoff noise and dynamic range
in digital filters. Bell Syst. Tech. J., 1970-02. 159-183.
[6] F Zhou, A floating- fixed conversion method on SoC based on
statistics and analytics. Journal of Circuits and Systems, Vol.12 No.1
2007, pp.124-129.
[7] UweMeyer-Baese, FPGA implementation of digital signal processing,
Tsinghua Press, Beijing, 2007
387