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8085 Microprocessor
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The first 8 lines of address bus and 8 lines of data bus are multiplexed AD AD .
0
8086 Microprocessor
It is a 16-bit p.
8086 has a 20 bit address bus can access up to 220 memory locations (1 MB).
It can support up to 64K I/O ports.
It provides 14, 16 -bit registers.
It has multiplexed address and data bus AD0- AD15 and A16 A19.
It requires single phase clock with 33% duty cycle to provide internal timing.
8086 is designed to operate in two modes, Minimum and Maximum.
It can prefetches upto 6 instruction bytes from memory and queues them in order to speed up
instruction execution.
It requires +5V power supply.
A 40 pin dual in line package
Minimum and Maximum Modes:
The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a single
microprocessor configuration.
The maximum mode is selected by applying logic 0 to the MN / MX input pin. This is a multi
micro processors configuration.
Architecture of 8086
BIU is not full, it has room for at least two more bytes and at the same time the EU is not
requesting it to read or write operands from memory, the BIU is free to look ahead in the
program by prefetching the next sequential instruction.
These prefetching instructions are held in its FIFO queue. With its 16 bit data bus, the BIU
fetches two instruction bytes in a single memory cycle.
After a byte is loaded at the input end of the queue, it automatically shifts up through the FIFO to
the empty location nearest the output.
The EU accesses the queue from the output end. It reads one instruction byte after the other from
the output of the queue. If the queue is full and the EU is not requesting access to operand in
memory.
These intervals of no bus activity, which may occur between bus cycles are known as Idle state.
If the BIU is already in the process of fetching an instruction when the EU request it to read or
write operands from memory or I/O, the BIU first completes the instruction fetch bus cycle
before initiating the operand read / write cycle.
The BIU also contains a dedicated adder which is used to generate the 20bit physical address that
is output on the address bus. This address is formed by adding an appended 16 bit segment
address and a 16 bit offset address.
For example: The physical address of the next instruction to be fetched is formed by combining
the current contents of the code segment CS register and the current contents of the instruction
pointer IP register.
The BIU is also responsible for generating bus control signals such as those for memory read or
write and I/O read or write.
EXECUTION UNIT
The Execution unit is responsible for decoding and executing all instructions.
The EU extracts instructions from the top of the queue in the BIU, decodes them, generates
operands if necessary, passes them to the BIU and requests it to perform the read or write bys
cycles to memory or I/O and perform the operation specified by the instruction on the operands.
During the execution of the instruction, the EU tests the status and control flags and updates
them based on the results of executing the instruction.
If the queue is empty, the EU waits for the next instruction byte to be fetched and shifted to top
of the queue.
When the EU executes a branch or jump instruction, it transfers control to a location
corresponding to another set of sequential instructions.
Whenever this happens, the BIU automatically resets the queue and then begins to fetch
instructions from this new location to refill the queue.
General Registers
The CPU has eight 16-bit general registers. They are divided into two files of four registers each.
They are:
(a) The data register file and
(b) The pointer and index register file
AX, BX, CX and DX registers are the data registers. The upper and lower half of the data
registers is individually addressable. AX register can be addressed as AL and AH registers, BX
register can be addressed as BL and BH register, CX register can be addressed as CL and CH
register, DX register can be addressed as DL and DH. The data registers can be used in most
arithmetic and logic operations. Some instructions however require these registers for specific
use.
The index register file consists of the Stack Pointer (SP), the Base Pointer (BP), Source Index (SI)
and Destination Index (DI) registers all are of 16-bits. They can also be used in most arithmetic
and logic operations. These registers are usually used to hold offset addresses for addressing
within a segment. Offset addressing reduces program size by eliminating the need for each
instruction to specify frequently used addresses. The pointer and index register files are further
divided into the pointer sub-file (containing the Stack Pointer and the Base Pointer registers) and
the index sub-file (containing the Source index and Destination index registers). The Pointer
registers are used to access the current stack segment. The index registers are used to access the
current data. (Stack segment and data segment are specific areas of memory. Their application
will be explained in later chapters). Unless otherwise specified in the instruction, stack pointer
registers refer to the current stack segment while index register refers to the current data segment.
The BP and SP registers are both used to point to the stack, a linear array in the memory used for
subroutine parameters, subroutine return addresses, and the data temporarily saved during
execution of a program.
The implicit register usage is as follows:
Most microprocessors have a single stack pointer register called the SP. 8086 / 8088 has an
additional pointer into the stack called the BP register. While the SP is used similar to the stack
pointer in other machine (for pointing to subroutine and interrupt return addresses), the BP
register is used to hold an old stack pointer value, or it can mark a place in the subroutine stack
independent of the SP register. Using the BP register to mark the stack saves the juggling of a
single stack pointer to reference subroutine parameters and addresses. SI and DI are both 16-bits
wide and are used by string manipulation instructions and in building some of the more powerful
8086/8088 data structures and addressing modes. Both the SI and the DI registers have auto
incrementing and auto-decrementing capabilities.
Flag Register
The Execution Unit has a 16-bit flag register which indicates some conditions affected by the
execution of an instruction. Some bits of the flag register control certain operations of the EU.
The flag register in the EU contains nine active flags
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Six of the nine flags are used to indicate some condition produced by an instruction. These
condition flags are also called status flags of 8086/8088 microprocessor. These are the Carry flag,
Parity flag, Auxiliary carry flag, Zero flag, and Sign flag. The other three Control flags are Trap
Flag, Direction Flag and Interrupt flag.
Condition Flags
Carry Flag (CF)
This flag will be set to one if the addition of two 16-bit binary numbers produces a carry out of
the most significant bit position or if there is a borrow to the MSB after subtraction. This flag is
also affected when other arithmetic and logical instruction are executed.
Parity Flag (PF)
This flag is set, if the result of the operation has an even number of 1's (in the lower 8 bits of the
result). This flag can be used to check for data transmission error.
Auxiliary Carry Flag (AF)
This flag is set, when there is a carry out of the lower nibble to the higher nibble or a borrow from
the higher nibble to the lower. The auxiliary carry flag is used for decimal adjust operation. The
AF flag is of significance only for byte operations during which the lower order byte of the 16-bit
word is used.
Zero Flag (Z)
This flag is set when the result of an operation is zero. The flag is reset when the result is not
zero.
Overflow Flag (O)
This flag is set, when an arithmetic overflow occurres. Overflow means that the size of the result
exceeded the storage capacity of the destination, and a significant digit has been lost.
Sign flag (S)
This flag is set, when an MSB bit of the result is high after an arithmetic operation. When this
flag is set the data in assumed to be negative and when this flag is zero it is assumed to be
positive.
Control Flags
Control flags are used to control certain operations of the processor. The application of these flags
are different from that of six conditional flags. The conditional flags are set or reset by the EU on
the basis of the result of some arithmetic or logic operations. The control flags are deliberately set
or reset with specific instructions included in the program.
Trap flag (T)
This is used for single stepping through a program. It is used for debugging the programs.
(Discusses with interrupts).
Interrupt Flag (I)
It is used to allow / prohibit the interruption of a program. When the flag set, it enables the
interrupt from INTR. When the flag is reset (0), it disables the interrupt.
Direction Flag (D)
It is used for string instruction (Discussed with the specific instructions later in the book). If the
direction flag is set, the pointers are decremented else the pointers are incremented.
Instruction Pointer (IP)
The Instruction Pointer is a 16-bit register. This register is always used as the effective memory
address, and is added to the Code segment with a displacement of four bits to obtain the physical
address of the opcode. The code segment cannot be changed by the move instruction. The
instruction pointer is incremented after each opcode fetch to point to the next instruction.
The segment registers point to the four immediately addressable segments. The four segment
registers are
Code Segment register [points to the instruction opcode]
Data Segment register [points to the data memory]
Stack Segment register [points to the Stack memory]
Extra Segment register [points to the data memory]
Assembler Directives
Assembler directives are the commands to the assembler that direct the assembly process. They
indicate how an operand is treated by the assembler and how assembler handles the program.
They also direct the assembler how program and data should be arranged in the memory. The
important point to be noted here is they do not generate any machine code i.e. they do not
contribute to the final size of machine code. And, they are assembler specific.
.MODEL directive
This directive is used to specify how many code and data segments are necessary for the
program.
The syntax is: .MODEL memory_model. The memory model can be chosen based on our
requirement as follows:
.STACK directive
This directive is optional and is used to define the size of the stack segment.
Syntax: .STACK <size>
For example, we can define a 100 bytes stack segment as .STACK 100d
.DATA directive
This directive is used to define data segment necessary for our program.
Data can be of different types like byte, word, double word or quad word. They can be declared
using directives as follows:
DB Define Byte
DW Define Word
DD Define Double Word
DQ Define Quad Word
DT Define Ten Bytes
There is one special directive to define blocks of larger size. It is DUP.
Syntax: label type size DUP (value to initialize in all locations)
.CODE directive
This directive is used to indicate the beginning of instructions i.e. the assembly code. The
assembly language program is end with END directive
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ASSUME directive
This is specific to MASM Assembler. It is used to give symbolic names to the different
segments.
For example, Assume cs:code, ds:data, ss:stack at the first line of your program indicates there
are three segments in the program and data is the name given to data segment, code is the name of
code segment and stack is the name for stack segment. Remember data, code and stack are user
given names.
SEGMENT and ENDS directives
They are used to mark the beginning and end of the particular segment.
Syntax:
segment_name SEGMENT
.
.
.
segment_name ENDS
For example, data segment can be declared as:
DATA SEGMENT
X DB 10H
Y DB 20H
Z DB ?
DATA ENDS
Eg. POP AX
POP DS
POP [5000H]
XCHG : Exchange byte or word
This instruction exchange the contents of the specified source and destination operands
Eg. XCHG [5000H], AX
XCHG BX, AX
IN:
Copy a byte or word from specified port to accumulator.
Eg. IN AL,03H
IN AX,DX
OUT:
Copy a byte or word from accumulator specified port.
Eg. OUT 03H, AL
OUT DX, AX
Arithmetic Instructions:
The 8086 provides many arithmetic operations: addition, subtraction, negation, multiplication and
comparing two values.
ADD :
The add instruction adds the contents of the source operand to the destination operand.
Eg. ADD AX, 0100H
ADD AX, BX
ADD AX, [SI]
ADD AX, [5000H]
ADD [5000H], 0100H
ADD 0100H
ADC : Add with Carry
This instruction performs the same operation as ADD instruction, but adds the carry flag to the
result.
Eg. ADC 0100H
ADC AX, BX
ADC AX, [SI]
ADC AX, [5000]
ADC [5000], 0100H
SUB : Subtract
The subtract instruction subtracts the source operand from the destination operand and the result
is left in the destination operand.
Eg. SUB AX, 0100H
SUB AX, BX
SUB AX, [5000H]
SUB [5000H], 0100H
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Logical Instructions
AND : Logical AND
This instruction bit by bit ANDs the source operand that may be an immediate register or a
memory location to the destination operand that may a register or a memory location. The result
is stored in the destination operand.
Eg. AND AX, 0008H
AND AX, BX
OR : Logical OR
This instruction bit by bit ORs the source operand that may be an immediate , register or a
memory location to the destination operand that may a register or a memory location. The result
is stored in the destination operand.
Eg. OR AX, 0008H
OR AX, BX
NOT : Logical Invert
This instruction complements the contents of an operand register or a memory location, bit by bit.
Eg. NOT AX
NOT [5000H]
XOR : Logical Exclusive OR
This instruction bit by bit XORs the source operand that may be an immediate , register or a
memory location to the destination operand that may a register or a memory location. The result
is stored in the destination operand.
Eg. XOR AX, 0098H
XOR AX, BX
TEST : Logical Compare Instruction
The TEST instruction performs a bit by bit logical AND operation on the two operands. The
result of this ANDing operation is not available for further use, but flags are affected.
Eg. TEST AX, BX
TEST [0500], 06H
SAL/SHL : SAL / SHL destination, count.
SAL and SHL are two mnemonics for the same instruction. This instruction shifts each bit in the
specified destination to the left and 0 is stored at LSB position. The MSB is shifted into the carry
flag. The destination can be a byte or a word. It can be in a register or in a memory location. The
number of shifts is indicated by count.
Eg. SAL CX, 1
SAL AX, CL
12
Bus
lock
instruction
prefix.
16
17
Immediate
Addressing mode
(for source
operand only)
Register addressing
Memory addressing
Immediate Addressing
Before
Ex1: MOV DX, 1234H
DX ABCDH
CH
After
1234H
Before
After
4DH
23H
Register Addressing
Before
Ex1: MOV CX, SI
After
CX 1234H
5678H
SI 5678H
5678H
Before
Ex2: MOV DL, AH
After
Dl
89H
BCH
AH
BCH
BCH
Memory Addressing
Direct Addressing
Indirect Addressing
Register
Indirect
Based
Based Indexed
Indexed
addressing with
addressing displacement
BX
DS:5634H
DS:5635H
ABCDH
8645H
45H
86H
LS byte
MS byte
Before
Ex2: MOV CL, DS:5634H
CL
F2H
DS:5634H
DS:5635H
45H
86H
Before
BH
After
C5H
After
45H
After
78H
CL
20H
SI
3456H
DS:3456H
DX
F232H
BX
A2B2H
DS:A2B2H
DS:A2B3H
67H
35H
Before
AH
30H
DI
3400H
DS:3400H
78H
78H
Before
After
86H
After
3567H
LS byte
MS byte
After
86H
Only SI, DI and BX can be used inside [ ] from memory addressing point of view. From
user point of view [BP] is also possible. This scheme provides 3 ways of addressing an
operand in memory.
Based Addressing with displacement
Before
Ex1: MOV DH, 2345H[BX]
DH
45H
67H
BX 4000H
DS:6345H
67H
Before
Ex2: MOV AX, 45H[BP]
After
AX 1000H
After
CDABH
BP 3000H
SS:3045H
SS:3346H
ABH
CDH
LS byte
MS byte
Base register can only be BX or BP. This scheme provides 4 ways of addressing an
operand in memory.
Indexed Addressing with displacement
Before
Ex1: MOV CL, 2345H[SI]
CL
60H
85H
SI 6000H
DS:8345H
85H
Before
Ex2: MOV DX, 37H[DI]
After
DX 7000H
After
B2A2H
DI 5000H
DS:5037H
DS:5038H
A2H
B2H
LS byte
MS byte
Index register can only be SI or DI. This scheme provides 4 ways of addressing an
operand in memory.
CL
40H
After
67H
SI 2000H
BX 0300H
2000H + 0300H = 2300H
DS:2300H
67H
Before
CX 6000H
After
6385H
BP 3000H
DI 0020H
2000H + 0300H = 2300H
It is SS when BP is used
SS:3020H
SS:3021H
85H
63H
LS byte
MS byte
This scheme provides 4 ways of addressing an operand in memory. One register must be
a Base register and the other must be an Index register.
For ex. MOV CX, [BX][BP] is an invalid instruction.
Based Indexed Addressing with Displacement
Before
Ex1: MOV DL, 37H[BX+DI]
37H is 8-bit displacement
DL
40H
After
12H
BX 2000H
DI 0050H
DS:2087H
12H
Before
BX 3000H
After
3665H
SI 4000H
BP 0020H
4000H + 0020H +1234 = 5254H
It is SS when BP is used
SS:5254H
SS:5255H
65H
36H
LS byte
MS byte
Base
Register
No
No
Yes
Yes
Index
Register
No
Yes
No
No
Displace
ment
Yes
No
No
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
No
Yes
Addressing mode
Direct Addressing
Register Indirect
Based Addressing with
Displacement
Indexed Addressing with
displacement
Based Indexed Addressing
Based Indexed Addressing
with displacement
Ex. 1:
IN AL, 83H
Before
AL 34H
After
78H
Ex. 2:
IN AX, 83H
Before
AX 5634H
After
F278H
Ex. 3:
OUT 83H, AL
Before
AL 50H
Output port no. 83H 65H
Ex. 4:
OUT 83H, AX
Before
AX 6050H
Output port no. 83H 65H
Output port no. 84H 40H
After
50H
After
50H
60H
IN and OUT instructions are allowed to use only AL or AX registers. Port address in the
range 00 to FFH is provided in the instruction directly.
Variable Port Addressing
I/O port address is provided in DX register. Port address ranges from 0000 to FFFFH.
Data transfer with AL or AX only.
Ex. 1:
IN AL, DX
Before
AL 30H
After
60H
DX 1234H
Input port no. 1234H 60H
Ex. 2:
IN AX, DX
Before
AX 3040H
After
7060H
DX 4000H
Input port no. 4000H 60H
Input port no. 4001H 70H
Ex. 3:
OUT DX, AL
Before
AL 65H
After
DX 5000H
Output port no. 5000H 80H
Ex. 4:
OUT DX, AX
Before
AX 4567H
65H
After
DX 5000H
Output port no. 5000H 25H
Output port no. 5001H 36H
67H
45H
UNIT-3
Pin Configuration
S6: When Low, it indicates that 8086 is in control of the bus. During a "Hold acknowledge"
clock period, the 8086 tri-states the S6 pin and thus allows another bus master to take control of
the status bus.
S3 & S4: Lines are decoded as follows:
generator to form READY. This signal is active HIGH. The 8086 READY input is not
synchronized. Correct operation is not guaranteed if the setup and hold times are not met.
CLK (I): Clock
Clock provides the basic timing for the processor and bus controller. It is asymmetric with 33%
duty cycle to provide optimized internal timing.
MN/MX (I): Maximum / Minimum
This pin indicates what mode the processor is to operate in. In minimum mode, the 8086 itself
generates all bus control signals. In maximum mode the three status signals are to be decoded to
generate all the bus control signals.
Minimum Mode Pins
The following 8 pins function descriptions are for the 8086 in minimum mode; MN/MX = 1. The
corresponding 8 pins function descriptions for maximum mode is explained later.
M/ IO (O): Status line
This pin is used to distinguish a memory access or an I/O accesses. When this pin is Low, it
accesses I/O and when high it access memory. M / IO becomes valid in the T4 state preceding a
bus cycle and remains valid until the final T4 of the cycle. M/ IO floats to 3 - state OFF during
local bus "hold acknowledge".
WR (O): Write
Indicates that the processor is performing a write memory or write IO cycle, depending on the
state of the M / IOsignal. WR is active for T2, T3 and Tw of any write cycle. It is active LOW,
and floats to 3-state OFF during local bus "hold acknowledge ".
INTA (O): Interrupt Acknowledge
It is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3, and
T4 of each interrupt acknowledge cycle.
ALE (O): Address Latch Enable
ALE is provided by the processor to latch the address into the 8282/8283 address latch. It is an
active high pulse during T1 of any bus cycle. ALE signal is never floated.
DT/ R (O): DATA Transmit/Receive
In minimum mode, 8286/8287 transceiver is used for the data bus. DT/ R is used to control the
direction of data flow through the transceiver. This signal floats to tri-state off during local bus
"hold acknowledge".
DEN (O): Data Enable
It is provided as an output enable for the 8286/8287 in a minimum system which uses the
transceiver. DEN is active LOW during each memory and IO access. It will be low beginning
with T2 until the middle of T4, while for a write cycle, it is active from the beginning of T2 until
the middle of T4. It floats to tri-state off during local bus "hold acknowledge".
HOLD & HLDA (I/O): Hold and Hold Acknowledge
Hold indicates that another master is requesting a local bus "HOLD". To be acknowledged,
HOLD must be active HIGH. The processor receiving the "HOLD " request will issue HLDA
(HIGH) as an acknowledgement in the middle of the T1-clock cycle. Simultaneous with the issue
of HLDA, the processor will float the local bus and control lines. After "HOLD" is detected as
being Low, the processor will lower the HLDA and when the processor needs to run another
cycle, it will again drive the local bus and control lines.
Maximum Mode
The following pins function descriptions are for the 8086/8088 systems in maximum mode (i.e..
MN/MX= 0). Only the pins which are unique to maximum mode are described below.
LOCK (O)
It indicates to another system bus master, not to gain control of the system bus while LOCK is
active Low. The LOCK signal is activated by the "LOCK" prefix instruction and remains active
until the completion of the instruction. This signal is active Low and floats to tri-state OFF
during 'hold acknowledge".
RQ / 0 GT and RQ / 1 GT (I/O): Request/Grant
These pins are used by other processors in a multi processor organization. Local bus masters of
other processors force the processor to release the local bus at the end of the processors current
bus cycle. Each pin is bi-directional and has an internal pull up resistors. Hence they may be left
un-connected.
A minimum mode of 8086 configuration depicts a stand alone system of computer where no
other processor is connected. This is similar to 8085 block diagram with the following
difference.
The Data transceiver block which helps the signals traveling a longer distance to get boosted up.
Two control signals data transmit/ receive are connected to the direction input of transceiver
(Transmitter/Receiver) and DEN* signal works as enable for this block.
In the bus timing diagram, data transmit / receive signal goes low (RECEIVE) for Read
operation. To validate the data, DEN* signal goes low. The Address/ Status bus carries A16 to
A19 address lines during BHE* (low) and for the remaining time carries Status information. The
Address/Data bus carries A0 to A15 address information during ALE going high and for the
remaining time it carries data. The RD* line going low indicates that this is a Read operation.
The curved arrows indicate the relationship between valid data and RD* signal.
The TW is Wait time needed to synchronize the fast processor with slow memory etc. The Ready
pin is checked to see whether any peripheral needs more time for data transmission.
This is the same as Read cycle Timing Diagram except that the DT/R* line goes high indicating
it is a Data Transmission operation for the processor to memory / peripheral. Again DEN* line
goes low to validate data and WR* line goes low, indicating a Write operation.
In the maximum mode of operation of 8086, wherein either a numeric coprocessor of the type
8087 or another processor is interfaced with 8086. The Memory, Address Bus, Data Buses are
shared resources between the two processors. The control signals for Maximum mode of
operation are generated by the Bus Controller chip 8788. The three status outputs S0*, S1*, S2*
from the processor are input to 8788. The outputs of the bus controller are the Control Signals,
namely DEN, DT/R*, IORC*, IOWTC*, MWTC*, MRDC*, ALE etc. These control signals
perform the same task as the minimum mode operation. However the DEN is an active HIGH
signal which has to be converted to active LOW by means of an inverter.
Here MRDC* signal is used instead of RD* as in case of Minimum Mode S0* to S2* are active
and are used to generate control signal.
Here the maximum mode write signals are shown. Please note that the T states correspond to the
time during which DEN* is LOW, WRITE Control goes LOW, DT/R* is HIGH and data output
in available from the processor on the data bus.
Request / Grant pin may appear that both signals are active low. But in reality, Request signal
goes low first (input to processor), and then the processor grants the request by outputting a low
on the same pin.
Since there is continuous address map, we can use a decoder to decode the chip select signals.
The inputs for the decoder would be a13, A0 and BHE.
As the table shows, when the decoder output O0 is enabled it selects both even and odd banks in
RAM. Then A0 and BHEcan be used accordingly to select only even or only odd bank.
Similarly, EPROM is selected by O4.
The complete Interface diagram is shown below:
E2: Interface two chips of 16K X 8 EPROMs and two chips of 32 X 8 RAM chips to 8086
microprocessor. Select the starting address of EPROM suitably, but the RAM address
must start at 00000H.
First let us write the memory map. If you observe the memory map, it shows that the address
map is not contiguous. Hence we will use logic gates instead of decoder to design decoding
logic.
E3: It is required to interface two chips of 32K X 8 ROM and four chips of 32K X 8 RAM
with 8086 according to following map.
ROM1 and 2: F0000H FFFFFH, RAM1 and 2: D0000H DFFFFH,
RAM3 and 4: E0000H EFFFFH
The necessary memory map is shown below and Interface diagrams is
input or output ports. Each port (Port A and Port B) uses 3 lines from port C as handshake
signals. The remaining two lines of port C can be used for simple I/O functions. Input and output
data are latched and Interrupt logic is supported.
Mode 2 : Bidirectional Data Transfer
This mode is used primarily in applications such as data transfer between the two computers or
floppy disk controller interface. Port A can be configured as the bidirectional port and Port B
either in mode 0 or mode 1. Port A uses five signals from Port C as handshake signals for data
transfer.
INTERFACING ANALOG TO DIGITAL DATA CONVERTERS
The function of an A/D converter is to produce a digital word which represents the magnitude of
some analog voltage or current. The specifications for an A/D converter are very similar to those
for D/A converter. The resolution of an A/D converter refers to the number of bits in the output
binary word. An 8-bit converter for example has a resolution of 1 part in 256. Accuracy and
linearity specifications have the same meaning for an A/D converter as they do for a D/A
converter. Another important specification for an ADC is its conversion time. This is simply the
time it takes the converter to produce a valid output binary code for an applied input voltage.
When we refer to a converter as high speed, we mean that it has a short conversion time. The
analog to digital converter is treated as an input device by the microprocessor that sends an
initialising signal to the ADC to start the analog to digital data conversation process. The start of
conversion signal is a pulse of a specific duration. The process of analog to digital conversion is
a slow process, and the microprocessor has to wait for the digital data till the conversion is over.
After the conversion is over, the ADC sends end of conversion (EOC) signal to inform the
microprocessor that the conversion is over and the result is ready at the output buffer of the
ADC. These tasks of issuing an SOC pulse to ADC, reading EOC signal from the ADC and
reading the digital output of the ADC are carried out by the CPU using 8255 I/O ports.
The time taken by the ADC from the active edge of SOC pulse (the edge at which the conversion
process actually starts) till the active edge of EOC signal is called as the conversion delay of the
ADC. Or broadly speaking the time taken by the converter to calculate the equivalent digital data
output from the instant of the start of conversion is called conversion delay. It may range any
where from a few microseconds in case of fast ADCs to even a few hundred milliseconds in case
of slow ADCs. A number of ADCs are available in the market, The selection of ADC for a
particular application is done, keeping in mind the required speed, resolution range of operation,
power supply requirements, sample and hold device requirements and the cost factors are
considered.
The available ADCs in the market use different conversion techniques for the conversion of
analog signals to digital signals. Parallel converter or flash converter, Successive approximation
and dual slope integration techniques are the most popular techniques used in the integrated
ADC chips. Whatever may be the technique used for conversion, a general algorithm for ADC
interfacing contains the following steps.
1. Ensure the stability of analog input, applied to the ADC.
2. Issue start of conversion (SOC) pulse to ADC.
3. Read end of conversion (EOC) signal to mark the end of conversion process.
4. Read digital data output of the ADC as equivalent digital output.
It may be noted that analog input voltage must be constant at the input of the ADC right from the
start of conversion till the end of conversion to get correct results. This may be ensured by a
sample and hold circuit which samples the analog signal and holds it constant for a specified
time duration. The microprocessor may issue a hold signal to the sample and Hold circuit. If the
applied input changes before the complete conversion process is over, the digital equivalent of
the analog input calculated by the ADC may not be correct.
ADC 0808/0809
The analog to digital converter chips 0808 and 0809 are 8-bit CMOS, successive approximation
converters. Successive approximation technique is one of the fast techniques for analog to digital
conversion. The conversion delay is 100 s at a clock frequency of 640 kHz, which is quite low
as compared to other converters. These converters do not need any external zero or full scale
adjustments as they are already taken care of by internal circuits. These converters internally
have a 3:8 analog multiplexer so that at a time eight different analog inputs can be connected to
the chips. Out of these eight inputs only one can be selected for conversion by using address
lines ADD A, ADD B and ADD C, as shown. Using these address inputs, multichannel data
acquisition systems can be designed using a single ADC.
The CPU may drive these lines using output port lines in case of multichannel applications. In
case of single input applications, these may be hard wired to select the proper
input.
The 8257 performs the DMA operation over four independent DMA channels.
Each of four channels of 8257 has a pair of two 16-bit registers, viz. DMA address register and
terminal count register.
There are two common registers for all the channels, namely, mode set register and status
register. Thus there are a total of ten registers. The CPU selects one of these ten registers using
address lines Ao-A3. Table shows how the Ao-A3 bits may be used for selecting one of these
registers.
If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is
reached, and it further prevents any DMA cycle on the channel. To enable the channel again, this
bit must be reprogrammed. If the TC STOP bit is programmed to be zero, the channel is not
disabled, even after the count reaches zero and further request are allowed on the same channel.
The auto load bit, if set, enables channel 2 for the repeat block chaining operations, without
immediate software intervention between the two successive blocks. The channel 2 registers are
used as usual, while the channel 3 registers are used to store the block reinitialisation parameters,
i.e. the DMA starting address and terminal count. After the first block is transferred using DMA,
the channel 2 registers are reloaded with the corresponding channel 3 registers for the next block
transfer, if the update flag is set. The extended write bit, if set to 1, extends the duration of
MEMW and IOW signals by activating them earlier, this is useful in interfacing the peripherals
with different access times.
If the peripheral is not accessed within the stipulated time, it is expected to give the NOT
READY indication to 8257, to request it to add one or more wait states in the DMA CYCLE.
The mode set register can only be written into.
Status Register
The status register of 8257 is shown in figure. The lower order 4-bits of this register contain the
terminal count status for the four individual channels. If any of these bits is set, it indicates that
the specific channel has reached the terminal count condition.
These bits remain set till either the status is read by the CPU or the 8257 is reset. The update flag
is not affected by the read operation. This flag can only be cleared by resetting 8257 or by
resetting the auto load bit of the mode set register. If the update flag is set, the contents of the
channel 3 registers are reloaded to the corresponding registers of channel 2 whenever the channel
2 reaches a terminal count condition, after transferring one block and the next block is to be
transferred using the autoload feature of 8257. The update flag is set every time, the channel 2
registers are loaded with contents of the channel 3 registers. It is cleared by the completion of the
first DMA cycle of the new block. This register can only read.
Data Bus Buffer, Read/Write Logic, Control Unit and Priority Resolver
The 8-bit. Tristate, bidirectional buffer interfaces the internal bus of 8257 with the external
system bus under the control of various control signals.
In the slave mode, the read/write logic accepts the I/O Read or I/O Write signals, decodes the
Ao-A3 lines and either writes the contents of the data bus to the addressed internal register or
reads the contents of the selected register depending upon whether IOW or IOR signal is
activated.
In master mode, the read/write logic generates the IOR and IOW signals to control the data flow
to or from the selected peripheral. The control logic controls the sequences of operations and
generates the required control signals like AEN, ADSTB, MEMR, MEMW, TC and MARK
along with the address lines A4-A7, in master mode. The priority resolver resolves the priority of
the four DMA channels depending upon whether normal priority or rotating priority is
programmed.
Signal Description of 8257
DRQo-DRQ3 :
These are the four individual channel DMA request inputs, used by the peripheral devices for
requesting the DMA services. The DRQo has the highest priority while DRQ3 has the lowest
one, if the fixed priority mode is selected.
DACKo-DACK3 :
These are the active-low DMA acknowledge output lines which inform the requesting peripheral
that the request has been honoured and the bus is relinquished by the CPU. These lines may act
as strobe lines for the requesting devices.
Do-D7:
These are bidirectional, data lines used to interface the system bus with the internal data bus of
8257. These lines carry command words to 8257 and status word from 8257, in slave mode, i.e.
under the control of CPU. The data over these lines may be transferred in both the directions.
When the 8257 is the bus master (master mode, i.e. not under CPU control), it uses Do-D7 lines
to send higher byte of the generated address to the latch. This address is further latched using
ADSTB signal. the address is transferred over Do-D7 during the first clock cycle of the DMA
cycle. During the rest of the period, data is available on the data bus.
IOR: This is an active-low bidirectional tristate input line that acts as an input in the slave mode.
In slave mode, this input signal is used by the CPU to read internal registers of 8257.this line acts
output in master mode. In master mode, this signal is used to read data from a peripheral during a
memory write cycle.
IOW :
This is an active low bidirection tristate line that acts as input in slave mode to load the contents
of the data bus to the 8-bit mode register or upper/lower byte of a 16-bit DMA address register or
terminal count register. In the master mode, it is a control output that loads the data to a
peripheral during DMA memory read cycle (write to peripheral).
CLK:
This is a clock frequency input required to derive basic system timings for the internal operation
of 8257.
RESET :
This active-high asynchronous input disables all the DMA channels by clearing the mode
register and tristates all the control lines.
Ao-A3:
These are the four least significant address lines. In slave mode, they act as input which select
one of the registers to be read or written. In the master mode, they are the four least significant
memory address output lines generated by 8257.
CS:
This is an active-low chip select line that enables the read/write operations from/to 8257, in slave
mode. In the master mode, it is automatically disabled to prevent the chip from getting selected
(by CPU) while performing the DMA operation.
A4-A7 :
This is the higher nibble of the lower byte address generated by 8257 during the master mode of
DMA operation.
READY:
This is an active-high asynchronous input used to stretch memory read and write cycles of 8257
by inserting wait states. This is used while interfacing slower peripherals.
HRQ:
The hold request output requests the access of the system bus. In the noncascaded 8257 systems,
this is connected with HOLD pin of CPU. In the cascade mode, this pin of a slave is connected
with a DRQ input line of the master 8257, while that of the master is connected with HOLD
input of the CPU.
HLDA :
The CPU drives this input to the DMA controller high, while granting the bus to the device. This
pin is connected to the HLDA output of the CPU. This input, if high, indicates to the DMA
controller that the bus has been granted to the requesting peripheral by the CPU.
MEMR:
This active low memory read output is used to read data from the addressed memory locations
during DMA read cycles.
MEMW : This active-low three state output is used to write data to the addressed memory
location during DMA write operation.
ADST :
This output from 8257 strobes the higher byte of the memory address generated by the DMA
controller into the latches.
AEN:
This output is used to disable the system data bus and the control the bus driven by the CPU, this
may be used to disable the system address and data bus by using the enable input of the bus
drivers to inhibit the non-DMA devices from responding during DMA operations. If the 8257 is
I/O mapped, this should be used to disable the other I/O devices, when the DMA controller
addresses is on the address bus.
TC:
Terminal count output indicates to the currently selected peripherals that the present DMA cycle
is the last for the previously programmed data block. If the TC STOP bit in the mode set register
is set, the selected channel will be disabled at the end of the DMA cycle.
The TC pin is activated when the 14-bit content of the terminal count register of the selected
channel becomes equal to zero. The lower order 14 bits of the terminal count register are to be
programmed with a 14-bit equivalent of (n-1), if n is the desired number of DMA cycles.
MARK :
The modulo 128 mark output indicates to the selected peripheral that the current DMA cycle is
the 128th cycle since the previous MARK output. The mark will be activated after each 128
cycles or integral multiples of it from the beginning if the data block (the first DMA cycle), if the
total number of the required DMA cycles (n) is completely divisible by 128.
Vcc :
This is a +5v supply pin required for operation of the circuit.
GND :
This is a return line for the supply (ground pin of the IC).
Interfacing 8257 with 8086
Once a DMA controller is initialised by a CPU property, it is ready to take control of the system
bus on a DMA request, either from a peripheral or itself (in case of memory-to memory transfer).
The DMA controller sends a HOLD request to the CPU and waits for the CPU to assert the
HLDA signal. The CPU relinquishes the control of the bus before asserting the HLDA signal.
Once the HLDA signal goes high, the DMA controller activates the DACK signal to the
requesting peripheral and gains the control of the system bus. The DMA controller is the sole
master of the bus, till the DMA operation is over. The CPU remains in the HOLD status (all of
its signals are tristate except HOLD and HLDA), till the DMA controller is the master of the bus.
In other words, the DMA controller interfacing circuit implements a switching arrangement for
the address, data and control busses of the memory and peripheral subsystem from/to the CPU
to/from
the
DMA
controller.
8051 MICROCONTROLLER:
8-bit microcontroller
Architecture of 8051:
Registers in 8051
Math Register
SFR MAP
F8
F0
E8
E0
ACC
D8
D0
PSW
C8
T2CON
TH2
C0
B8
IP
B0
IP3
A8
IE
A0
P2
98
SCON
90
P1
88
TCON
TMOD
TLO
TLO
80
PO
SP
DPL
DPH
SBUF
THO
TH1
T
PCON
Addressing Modes:
Ex: ADD A, #77 (immediate addressing)
A=A + 77(decimal)
1) Immediate Addressing Mode: Where data is available in the instruction itself.
2) Bank Register Addressing: Add A, RO
since it has 4 different banks each bank each having 8 bytes and the register RO of which bank is selected by the SFR PSW.
PSW: RSI and RSO selects which bank is to be selected.
How to latch 1 to P3 X ?
This latching is done in the following process.
Port 1
Port 2 (A8-A15)
RAM CData
8-bit or 16-bit address
If the address is stored in a 8-bit register
then it points to 8-bit address
MOV A,@RO
For 16-bit address
MOV A, @ DPTR
For 8-bit Memory address access, P2 Pins o/p the SFR register contents and helps in memory pages.
The higher order 8-bit address is taken the address available in the P2 SFSR and the lower order 8-bit address is
the data available in register RO.
Timer/Counter in 8051
8051 has two 16-bit Timer/counter registers. 8052 has these two plus one more:Timer 2. All these
can be congured to operate either as times or event counters.
In the Timer function, the register is incremented every machine cycle. Now one can think of it
1
oscillator frequency ( one
as counting machine cycles (instruction cycles) and the clock rate is 12
instruction cycle = 12 clock cycles). In Counter function, the register is incremented in response to
a 1 to 0 transition at its corresponding external input pins, ie. T0, T1 or (in 8052)T2. In this function,
the external inputs is sampled during S5P2 of every machine cycle. When the samples show a high
in one cycle and a low in the next cycle, the count is incremented. The new count value appears in
the register during S3P1 of the cycle following the one in which the transition was detected. Since
it takes 2 machine cycles (24 oscillator periods) to recognize a 1-to-0 transition, the maximum count
rate is 1/24 of the oscillator frequency.
Timer 0 and Timer 1 have 4 operating nodes. Timer 2 in 8052 has 3 modes of operation: Capture,
auto-reload and bandrate generator.
Gate
C/T
M1
M0
Timer - 1
3
Gate
C/T
M1
M0
Timer - 0
-- 12d
to timer
stages
Counter
T1 /0 Input pin
Timer Mode-0
Setting timer x mode bits to 00 in the TMOD register results in using the THX register as a 8-bit
counter and TLX as a 5-bit register (lower bits). The upper 3-bits of TLX are indeterminate and
should be ignored. The timer overow ag in TCON is set whenever THX goes from FFh to 00h.
Pulse
Input
TLX 5 bits
THX 8 bits
TFX
Interrupt
Timer Mode-1
Mode-1 is similar to mode-0 except TLX is congured as a full 8-bit counter. When the mode bits
are set to 01 in TMOD.
Pulse
Input
TLX 8 bits
THX 8 bits
TFX
Interrupt
TF1
TR1
TF0
TR0
3
IE1
IT1
IE0
IT0
TF1 Timer 1 overow ag. Set when timer rolls from all 1s to all 0. Cleared when processor
vectors to execute int. Since routine at 00/Bh
TR1 Timer 1 run control bit. Set to 1 by program to enable time to count. Clear to 0 by program
(TRO - for Timer 0)
Timer Mode-2
(Auto-reload feature) TLX is used as a 8-bit counter only. THX is used to hold a value that is loaded
into TLX everytime TLX overows from FFh to 00h. The time ag is also set when TLX overows.
The mode shows auto reload feature where TLX will be initialized to the content of THX after TLX
overows.
Pulse
Input
Interrupt
TFX
TLX 8 bits
Reload TLX
THX 8 bits
Timer Mode-3
Timer 1 in Mode-3 simply holds its count. The eect is the same as setting TR1=0. Timer 0 in Mode
3 establishes TL0 and TH0 as two sperate counters.
Pulse
I/P
TLO 8 bits
TF0
Interrupt
f/12
TH0 8 bits
TF1
Interrupt
TRI Bit
in TCON
Timer-1 can still be used in Mode-0,1 and 2 but no interrupt will be generated by Timer-1 while
Timer-0 is in Mode-3.
Timer 2
Like Timer-0 and 1, it can operate either as a timer or as a event counter.
T2CON
7
TF2
EXF2
5
RCLK
TCLK
EXEN2
TR2
1
C/T2
0
CP /RL2
This is selected by bits C/T2 in special function register T2CON. It has there operating modes:
Capture, auto-load and band rate generator.
RCLK + TCLK
CP /RL2
TR 2
Mode
16-bit Auto-reload
16-bit capture
Bandrate gen
off
Serial Interface:
The serial port is full duplex.
SBUF Special function Register.
Mode - 0 Shift register mode.
Serial data enters and exists through RXD. 8-bits are transmitted/recieved. Pin TXD is connected to
the internal shift frequency pulse source to supply shift pulses to external circuits. The shift frequency
or bandrate is xed at 1/2 of the oscillator frequency.
Idle state
1
Data bits
Start
Bit
Minimum
one stop bit
t
Bit time =
1
f
SM0
(LSB )
SM1
SM2
REN
TB8
RB8
TI
RI
SM2
Enables multiprocessor communication in Mode 2 and 3.
REN
Enables serial reception.
TB8
9th data bit that will be transmitted in Mode 2 and 3.
RB8
9th data bit that was received. In mode-1, a SM2=0, RB8 is
was received. In mode-0, RB8 is not used.
T1
Transmit interrupt ag
R1
Receive interrupt ag
PCON
3
GF1
SMOD
fband
GF0
PD
IDL
2SM OD
fosc
=
32
12 [256 T H1]
Timer-1 is used to generate band rate for mode-1 using overow ag of the timer to determine the
band frequency. Typically Timer-1 is used in mode-2 as an auto load 8-bit that generates the band
frequency.
If Timer-1 is not run in timer mode-2 then the band rate is
2SM OD
timer 1 overow frequency
Fband =
32
fclock = 11.0592 M Hz
fband = 9600
20
11.0592 106
T H1 = 256
= 253 = 0F DG
32
12 9600
Multiprocessor Communication
Mode 2 and 3 have a special provision for multiprocessor communication. In this mode, 9 data bits
are received/transmitted. The port can be programmed such that when the stop bit is received, the
serial interrupt will be activated only if RB8=1. This feature is enabled by setting bit SM2 in SCON.
A way to use this feature is given here.
Rx
Tx
Rx
Tx
8051
Slave 1
Add 2
Rx
Tx
Master
Add 1
8051
Slave 2
When a master processor wants to send a data byte to a slave, the master sends the address of the
slave rst. There may be many slave processors. An address byte diers from a data byte in that
the 9th bit is 1 in an address byte and 0 in a data byte. An address byte interrupts all slaves when
SM2=1. But a data byte does not interrupt the slaves if they have SM2=1. The address byte is
checked by each slave and the target/addressed slave clears its SM2 so that it can receive the data
byte. The slaves that are not addressed leave their SM2s set and go on with their business, ignoring
the incoming data bytes. SM2 has no eect in mode 0, and in mode 1, it can be used to check the
reliability of the stop bit. In mode 1, if SM2=1, then receive interrupt will not be activated unless a
valid stop bit is received.
Interrupts
8051 provides 5 interrupt sources. The 8052 provides 6.
0
IE0
INT0
IT0
Interrupt
TF0
Interrupt
0
IE1
INT1
IT1
TF1
Interrupt
1
Interrupt
TI
RI
Interrupt
TF2
EXF2
Interrupt
IN T 0 and IN T 1 are external interrupts and can be level triggered or edge triggered (negative) depending upon IT 0/IT 1 in TCON SFR.
IT 0 Set
falling edge triggered for IN T 0
IT 0 Cleared low level triggered for IN T 0
IE0/1E1
Interrupt 0/1 edge ag. Set by hardware when external interrupt edge detected. Cleared
when interrupt processed.
Timer 0 and Timer 1 interrupts are generated by TF0 and TF1, which are set by a rollover in their
respective Timer/Counter register (except Timer 0 in Mode 3). When a timer interrupt is generated,
the ag that generated it is cleared by on chip hardware when the interrupt service routine is vector
to. The serial port interrupt is generated by the logical OR of RI and TI. Neither of these ags is
cleared by hardware when the interrupt service routine is vectored to. These have to be cleared by
software.
All of the bits that generate interrupts can be set or cleared by software, with the same result as
though it had been cleared by hardware. That is, interrupts can be generated or pending interrupts
can be canceled in software.
Each of these interrupts can be individually enabled or disabled by setting or clearing bit in the SFR
IE. IE contains a global disable bit, EA which disable all interrupts at once.
(MSB )
EA
(LSB )
ET2
ES
ET1
EX1
ET0
EX0
EA = 0 no interrupt is acknowledged.
= 1 each int source is individually enabled or disabled
ET2 = 0 disables Timer 2 overow int
= 1 enables Timer 2 overow int
ES = 0 Serial port int is disabled
= 1 Serial port int is enabled
ET1 = 0 Timer 1 overow int is disabled
= 1 Timer 1 overow int is enabled
EX1 = 0 External int 1 (IN T 1) is disabled.
= 1 External int 1 (IN T 1) is enabled.
ET0 = 0/1 Disables Timer 0 OF int
EX0 = 0/1 Disables/enables external int (IN T 0)
Priority structure
Each interrupt source can be individually programmed to one of two priority levels by setting or
cleaning a bit in special function register IP. A low priority interrupt can itself be interrupted by a
high priority interrupt, but not by another low priority interrupt. If two requests of dierent priority
levels are received simultaneously, the request of higher priority level is serviced. If requests of same
priority level are received simultaneously, an internal polling sequence determines which request has
to be serviced. Thus within each priority level, there is a second priority structure determined by the
polling sequence, as follows:
Source
Priority within level
1. IE0
(Highest)
2. TF0
3. IE1
4. TE1
5. RI+TI
6. TF2+EXF2
(Lowest)
How the interrupts are handled Interrupt ags are sampled in S5P2 of each instruction cycle.
The samples are polled during the following instruction cycle (machine cycle). If one of the ags was
in a set condition at S5P2 of the preceding cycle, the polling will nd it and the interrupt system will
generate an LCALL to the appropriate service routine, provided this hardware generated LCALL is
not blocked by any of the following conditions:
1. An interrupt of equal or higher priority level is already in progress.
2. The current polling is not the nal machine cycle of the instruction in progress
3. The instruction in progress is RET1 or any write to IE or IP registers.
If an interrupt ag is a active but not being responded to for one of the above conditions, if the ag
is not still active when the blocking condition is removed, the denied interrupt will not be serviced.
This is because the interrupt ag once active but not serviced is not remembered. Every polling cycle
is new
C1
C2
C3
C4
C5
C6
Int .
goes active
Int
latched
Interrupt
Service
Routine
After a interrupt is vectored to, some interrupt ags are cleared and some are not by hardware.
For example: Serial port and Timer 2 interrupt ags are not cleared automatically. This has to
be done by users software. IEU and IE1 are cleared if the interrupts are transition activated.
TF0 and TF1 are cleared by hardware generated LCALL pushes PC into the stack but not PSW.
Source
Vector address
IE0
TF0
IE1
TF1
RI+TI
TF2+EXF2
0003H
000BH
0013H
001BH
0023H
002BH
External Interrupt
IN T O and IN T 1
Level triggered or Transition triggered
(Low)
(1-to-0 transition)
IT0/IT1=0
IT0/IT1=1
Low or high should be maintained at the pin for at least 12 clock cycles (1 machine cycle).
Special function Register (IP)
Interrupt Priority Register (IP)
(MSB )
(LSB )
PT2
PS
PT1
PX1
PT0
PX0
PT2 Timer 2
1-high priority 0-Low priority
PS
Serial Port Interrupt 1-high priority 0-Low priority
PT1 Timer 1 Interrupt
1-high priority 0-Low priority
PX1 External Int. 0
1-high priority 0-Low priority
PT0 Timer 0 Int.
1-high priority 0-Low priority
PX0 External Int 1
1-high priority 0-Low priority
Software generated interrupts
When any interrupt ag is set to 1 by any means, an interrupt is generated unless blocked. This
means that the program itself can cause interrupts of any kind to be generated by simply setting the
desired interrupt ag to 1 using program instruction.
Example of interrupt Use
Single-Step operation
The following program enables simple step operation
JNB P3.2, FDH
JB
P3.2, FDH
RETI
Reset
Non-maskable Interrupt
Holding RST pin high for at least 2 machine cycles while the osc is running.
After RST is made low
PC 0000H
SP 07H
Postlatches FFH
SBUF XX
All other SFR 00
RAM content is not changed.
Power-on Reset
When power is switched on (Vcc ), the capacitor behaves as a short circuit and RST pin remains high
for considerable amount of time to enable the micro controller to go into RESET mode.
Vcc
10 F
Vcc
RST
8051
8 .2 k
Vcs
XTAL2
XTAL1
Interrupt
Internal Port
TImer Port
osc
Clock
PD
CPU
IN
Idle and power down modes are activated by setting the corresponding bits (IDL and PD respectively)
in PCON special function register.
(MSB )
PCON
87H
SMOD
(LSB )
GF1
GF0
PD
IDL
PD - Power down bits. Setting this bit activates power down operation
IDL - Idle mode bit. Setting this bit activates idle mode operation.
Not bit
addressable
Idle Mode
An instruction that sets P CON0 causes that to be the last instruction executed before going into
the idle mode. In the idle mode, the internal clock signal is gated o to the CPU, but not to the
interrupt, Timer and Serial port functions. The CPU status is preserved entirely. SP,PC,PSW,Acc,
and all other registers maintain thier data during the idle mode. The port pins hold their logical
status they had at the time idle was activated. ALE and P SEN are hold at logic high levels.
There are two ways to terminate idle. Activation of any enabled interrupt will cause PCON0 to be
cleared by hardware, terminating the idle mode. After RET1 is executed, the next instruction starts
from the one following the instruction which enabled the idle mode.
The ag bits GF0 and GF1 can be used to give an indication if an interrupt occurred during normal
operation or during the idle mode. For example, an instruction that activated idle can also set and
or both ags. When idle is terminated by an interrupt, the ISR can examine the ag bits.
The other way of terminating the idle mode is with a hardware reset.(Reset should be high for two machine cycle or 24 clock cycles). The signal at the RST pin clears IDL bit directly and asynchronously.
At this time the CPU resumes the program execution from where it left o; that is , at the instruction
following the one that involved idle mode. Two to three machine cycles should be executed before
the internal reset algorithm takes control.
Power down mode
An instruction that sets PCON.1 causes that to be the last instruction executed before going into the
power down more. In the power down mode, the on-chip oscillator is stopped. With the clock frozen,
all functions are stopped, but the on-chip RAM and special function register are held. The port pins
output the values held by thier respective SFRs, ALE and P SEN output.
The only exit from Power down mode of operation in by a hardware reset. Reset redenes all SFRs,
but does not change the on-chip RAM.
Vcc may be reduced to as low as 2V during Power down mode. However Vcc should be restored to the
rated value and allow clock to stabilize ( 10ms)before the Power down mode is exited, ie, hardware
Reset is pressed.
Arithmetic Instructions
Mnemonics
ADD A,Rn
ADD A,direct
ADD A,@Ri
ADD A,data
ADDC A,Rn
ADDC A, direct
ADDC A,@Ri
ADDC A,data
SUBB A,Rn
SUBB A,direct
SUBB A,@Ri
SUBB A,data
INC A
INC Rn
INC direct
INC @Ri
DEC A
DEC Rn
DEC direct
DEC @Ri
INC DPTR
MUL AB
DIV AB
DA A
Description
A A + Rn
A A + Direct
A A + @Ri
A A+data
A A+ Rn+C bit
A A+(direct)+C bit
A A+@Ri+C bit
A A+data+C-bit
A A-Rn-C-bit
A A-(direct)-C-bit
A A-@Ri-C-bit
A A-data-C-bit
A A+1
Rn Rn+1
direct (direct)+1
@Ri @Ri+1
A A-1
Rn Rn-1
direct (direct)-1
@Ri @Ri-1
DPTR DPTR+1
A lowbyte (A*B)
B highbyte (A*B)
A quotient (A/B)
B remainder (A/B)
decimal adjust acc
Logical Instructions
Mnemonics
ANL A,Rn
ANL A,direct
ANL A,@Ri
ANL A,data
ANL direct,A
ANL direct, data
ORL A,Rn
ORL A,direct
ORL A,@Ri
ORL A,data
ORL direct,A
ORL direct,data
XRL A,Rn
XRL A,direct
XRL A,@Ri
XRL A,data
XRL direct,A
XRL direct,data
CLR A
CPL A
RL A
RLC A
RR A
RRC A
SWAP A
Description
A A.Rn
A A.Direct
A A.@Ri
A A.data
(direct) (direct)A
(direct) (direct).data
A A+Rn
A +(direct)
A A+@Ri
A A+data
(direct) (direct)+A
(direct) (direct)+data
A A Rn
A A (direct)
A A @ Ri
A A data
A direct A
direct direct data
A 00H
AA
Rotate Left
Rotate left through carry
Rotate right
Rotate right through carry
Swap nibbles within the ACC
Bytes
Instruction Cycles
Description
Carry 0
bit 0
Carry 1
bit 1
CC
bit bit
C C.bit
C C.bit
C C+bit
C C + bit
C bit
bit C
Jump if C=1
Jump if C=0
Jump if bit = 1
Jump if bit = 0
Jump if b=1 and b 0
Absolute jump
Long jump
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump
Jump relative to DPTR
Bytes
2
3
Instruction Cycles
2
2
while the three low-order bits identies the bit position within that register.
A Reg
MOVX @ RT
Ext
RAM
R0 or R1
DPTR
DPTR + A
PC + A
Read
Write
Int &
Ext
RAM
MOVX @ DPTR
MOVC A, @ A + DPTR
MOVC A,@ A + PC
Address Range
0000 - 07FF
0800 - 0FFF
1000 - 17FF
1800 - 1FFF
2000 - 27FF
2800 - 2FFF
3000 - 37FF
3800 - 3FFF
4000 - 47FF
4800 - 4FFF
5000 - 57FF
5800 - 5FFF
6000 - 67FF
6800 - 6FFF
7000 - 77FF
7800 - 7FFF
Page
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Address Range
8000 - 87FF
8800 - 8FFF
9000 - 97FF
9800 - 9FFF
A000 - A7FF
A800 - AFFF
B000 - B7FF
B800 - BFFF
C000 - C7FF
C800 - CFFF
D000 - D7FF
D800 - DFFF
E000 - E7FF
E800 - EFFF
F000 - F7FF
F800 - FFFF
It can be seen that the upper 5 bits of the program counter hold the page number and the lower 11
bits of the program counter hold the address within each page. Thus an absolute address is formed
by taking page number of the instruction following the branch and attaching the absolute page range
address of 11 bits to it to form the 16-bit address.
Diculty is encountered when the next instruction (the instruction following the jump instruction)
starts at X800H or X000H. This places the jump or call address on the same page as the next instruction. This does not give rise to any problem on forward jump, but results in error if the branch
is backward in the program. This should be checked by assembler and the user should be instructed
to relocate the program suitably.
Short absolute range jump is also relocatable as the relative jump. Instructions using short absolutes range are
ACALL addr 11
AJMP addr 11
MOV A, 10H
MOV RO, A
ADD A, RO
JNC ADDA
MOV A, 10H
ADDR: ADD A,RO
JNB 0D7H, ADDR
JBC 0D7H, LOOP
Example of External Data
ORG
O
MOV
RO,043H
MOV
A, 12
MOVX @RO, A
MOVX A, 34
MOVX A, @RO
BAUDNUM, 0F3H
DELAY, 0A6H
DLYLSB, 05H
DLYMSB, 00H
0000H
PCON, 7F H
TMOD, 3F H
TMOD, 20H
THI, BAU DN U M
TRI
SCON, 40H
XMIT:
MOV SBUF, A
ACALL XMITTIME
SJMP XMIT
XMITTIME:
SOFTIME:
PUSH 07H
PUSH ACC
ORL A,B
CJNE A, 00H, OK
POP ACC
SJMP DONE
POP ACC
OK:
8031:
8032:
8051:
8052:
8751:
ATMEL
AT 89C51:
EQU
0000H
OVER
ORG
0023H
RECEIVE:
CLR
MOV PI,
RETI
TMOD
Gate
RI
SBUF
Register
C/T
M1
1
OVER:
0F3H
M0
Gate
C/T
M1
M0
ANL
PCON, 7FH
; Set SMOD=0
ANL
TMOD, 0FH
; Alter Timer=1 conf only
ORL
TMOD, 20H
; Timer 1 in mode -2
MOV TH1,
BAUDNUM ; Reload value
SETB TR1,
; Run Timer - 1
MOV SCON, 40H
; Serial Mode - 1
SETB REN,
; Enable serial reception
ORL
IE, 90H
; Enable Interrupt
WAIT:
SJMP WAIT,
; Wait for recieving data
END
Interrupt driven character transmission
BAUDNUM EQU
0F3H
ORG
0000H
SJMP
OVER
SERIAL
OVER:
WAIT:
CLR
MOV
RET1
ANL
ANL
ANL
ORL
MOV
SETB
MOV
ORL
MOV
SJMP
END
TI
SBUF,A
PCON,7FH
PCON,7FH
TMOD,0FH
TMOD,20H
TH1,BAUDNUM
TR1,
SCON,40H
IE,90H
SBUF,A
WAIT,
;
;
;
;
;
;
;
;
;
SMOD=0
SMOD=0
Timer-1 in mode - 2
Reload value
Rum Timer-1
Serial mode-1
Enable serial int
Send data