Workshop on Spoken Language Processing

An ISCASupported Event

ISCA Archive

Mumbai, India
January 911, 2003

http://www.iscaspeech.org/archive

DESIGN AND IMPLEMENTATION OF DIGITAL SPEECH

SECURITY SYSTEM
K. T. V. Reddy, V. Prasad and N. Padmakar
Department of Electronics and Telecommunication Engineering
Fr. C. Rodrigues Institute of Technology, Agnel Technical Educational Complex
Sector 9A, Vashi, Navi Mumbai 400 703, India
E-mail: agnelvox@bom4.vsnl.net.in, ktvr@ee.iitb.ac.in
ABSTRACT
In digital speech security system (DSSS), the
analog signal is converted into pulse code
modulated (PCM) digital form using an
analog-to-digital converter and encrypted before
transmission by a special technique. The
desired party can decipher the message by
treating the received encrypted data with the
same technique. Thus conversation can be
carried out without interception. The digital
signal is combined directly with the output
from a pseudorandom number generator (noise
generator) to obtain an encrypted speech
before transmission. Such a system has the
property that for the interceptor, the received
message appears like noise and thus prevents
him from eavesdropping. However, the desired
party can decipher the message by once again
mixing the received enciphered message with
the local replica of the pseudorandom noise
(PN) available with him.
1. INTRODUCTION
On the verge of next millennium, technology has
reached a stage where present systems can be
revolutionized by digitizing them. Looking at
the numerous advantages they offer, we can
surely say that the future certainly belongs to
digital technology. Also this is what we call
an Information Age. Smooth, efficient and fast
communication or exchange of information is
what we aim for. So it becomes at the most
necessary to keep certain information absolutely
confidential. Digital speech security system
conversation can be carried on between two
persons without the fear of unauthorized
interception. This system has the property that
for the interceptor the received message
appears like noise and thus prevents the
message from eavesdropping.

A communication system that supports many

users can be called a network. Data system
which depends on central switching facility is
referred to as centralized network. Such a
network used in modern communication world
is Telephone Network. Each customer has a
link to the central switching equipment which
interconnects one user with another user as
required. In turn the central exchanges are
interconnected by means of trunk lines and
thus each centralized network becomes a part
of a larger network which can make
interconnection between individual users from
different centralized networks. The central
switch of each centralized network may create
cross talk in communication. The other reason
for cross talk is losses in the telephone lines
such as radiation, conductor heating, dielectric
heating,
electrical
short
circuit
etc.
Conventionally, speech is protected from
unauthorized interception or eavesdropping by
analog techniques using scramblers. There are
time, frequency and band scramblers in
diplomatic use.
In DSSS, the analog signal is converted into
pulse code modulated digital form using an
analog-to-digital converter and encrypted before
transmission by a special technique [1-2]. The
desired party can decipher the message by
treating the received encrypted data with the
same technique. Thus conversation can be
carried out without interception. The digital
signal is combined directly with the output
from a pseudorandom number generator (noise
generator) to obtain an encrypted speech
before transmission. Such a system has the
property that for the interceptor, the received
message appears like noise and thus prevents
him from eavesdropping. However, the desired
party can decipher the message by once again

mixing the received enciphered message with

the local replica of the pseudorandom noise
(PN) available with him. The digital speech
security system is intended to serve the
purpose of data or voice security through
communication channel.
2. DIGITAL SPEECH SECURITY SYSTEM
IMPLEMENTAION
Block diagram digital speech security system is
shown in Fig. 1. The system is divided into
three sections,
viz., Pulse code modulator
(ADC), PN sequence generator with encryptor /
decryptor and Pulse code demodulator.
2.1 Modulator
Fig. 2 shows the block diagram of DSSS
Modulator.
0.3-3.4 KHz
VOICE
INPUT
2 Vp-p

level
shifter

S/H and
ADC

parallel to
serial
converter

Fig. 2 Block Diagram of digital speech security

system Modulator
2.1.1

Level Shifter

A analog voice signal of 0.3 to 3.4kHz is

applied at the input terminal of the level
shifter . Here the diode clamper is used as a
level shifter. It shifts the level of the analog
signal at the zero reference level. The analog
signal which is normally bipolar, is converted
into unipolar using level shifter. This level
shifter is implemented in the circuit by using
an capacitor and a diode. This is used to
convert the bipolar signal to unipolar signal.
2.1.2 Sample and Hold Circuit and ADC
In the sample and hold circuit the continuous
speech waveforms are sampled at regular
intervals and the peak voltages are retained
without losses in a capacitor. This sampled
output is converted into digital signal by
analog to digital converter IC. This ADC
provides 8-bit equivalent of the sampled
speech in the parallel form. The analog-todigital conversion ( PCM ) is realized using an
8-bit ADC chip AD7574 ( IC 5 ) in the unipolar

binary configuration . It has inbuilt sample and

hold circuit and the conversion process starts
with an internal clock of 500 KHz. The
conversion time is only 15microsec. Since our
speech is band limited to 3.4 KHz, the
sampling clock of 8 KHz has to be applied to
pin 15 of AD7574. To convert the original
bipolar speech signal to unipolar signal, a
clamp circuit ( level shifter ) has to be used as
shown. The output code of this ADC is straight
binary and the same is available as a 8-bit
parallel output (at pins through 13 of IC 5 ).
2.1.3

Parallel to Serial Converter

The 8-bit equivalent sampled speech output is

converted into a serial bit stream using a
parallel to serial converter. This is done by
using the IC 74LS165. Depending on the PL
pin of this IC data is either shifted in
parallely or shifted out serially. To convert
this 8-bit digital data into a serial digital bit
stream, a parallel-to-serial converter 74LS165 (
IC 6 ) is used. A 64 KHz clock has to be
applied at pin 2 of this chip. When PL ( pin 1 )
is held low, the input data is parallely loaded
into the respective 8-bit input registers. When
PL signal is high, the parallel data is shifted
out serially in synchronism with positive going
transition of the 64 KHz clock signal. The
serial PCM digital is available at pin 9 of IC
6. For generating proper PL Signal, the 8KHz
clock
is applied
to
the
monostable
multivibrator 74LS122 ( IC 4 ). The required
pulse width of 2sec is obtained at pin 6 by
choosing appropriate value of timing resistor
R3 and capacitor C3.
2.2 Encryptor
2.2.1 Pseudorandom Noise Generator
It consists of 8-bit shift register SIPO. A
logic combination of the 8 outputs is made
and is fed back to the input. A 64KHz clock
is provided to the generator. Thus PRSQ
sequence is generated by this unit. The output
of this unit is fed to the encryptor unit.
A six stage PN (pseudorandom number)
sequence generator acting as a noise generator
is shown in Fig. 3. For this serialin parallelout shift registers 74LS164 ( IC 7 ) is used.
This requires feedback connections from at
least 2 output pins of 74LS164 to its own
serial inputs ( pins 1 and 2 ) through an EX-

Fig. 3
Block
Noise Generator

Diagram of

Pseudorandom

OR gate. But if at the starting instant all the

six stages of the shift registers are filled with
zeros, then the PN sequence generator output
will be all zeros. This is achieved
automatically by using combinational logic
circuits ( IC 8 through IC 11 ). PN sequence
output is available at pin 11 of IC 7 and the
buffered output at pin 6 of inverter N15 of
74LS04 ( IC 11).
2.2.2 Encryptor
The encryptor is basically a two input EX-OR
gate. To one input PRSQ sequences are
applied and to the second input the output of
the PISO is applied. The output of this unit
is the encrypted data. Modulo-2 adder is used
to obtain the enciphered speech. When switch
S1 is closed, the output of the modulo-2
adder will be the encrypted signal (PCM
signal + Noise). If the switch S1 is open, the
output will be PCM signal. The PN sequence
and the digitized serial speech information are
subjected to module-2 addition using EX-OR
gate N11 of 74LS86 ( IC 10 ). The buffered
output at pin no.10 of IC 11 is the required
encrypted speech. If switch S1 is open, then
the PCM signal will be available at pin. 10 of
IC 74LS04 ( IC 11 ). When switch S1 is
closed, the PN sequence input gets added to
the IC 74LS86 ( IC10 ) at pin no. 5 giving a
encrypted output (PCM signal + Noise ) at the
pin no. 6 of N11.
2.3 Demodulator
2.3.1

Decryptor

The decryptor is basically a two input EX-OR

gate. To one input PRSQ sequences are
applied and to the second input is added
encrypted data (PCM signal + Noise).
The
output of this unit is the decrypted data.
Modulo-2 adder is used to obtain the
deciphered speech. When switch S2 is closed,
the output of the modulo-2 adder will be the
decrypted signal (PCM signal). If the switch

S2 is open, the output will be encrypted

speech ( PCM signal + Noise ). If switch S2
is open, the same encrypted speech will be
available at pin 8 of 74LS86 ( IC 10 ). When
switch S2 is closed, the PN sequence input is
present at pin 10 of IC 10 and deciphering
action is completed by this second EX_OR
gate N12. Under this condition, we recover the
original digitized speech at pin 8 of IC10.

Fig. 4 Block Diagram

sequence Decryptor
2.3.2

of

Pseudorandom

SIPO and Digital to Analog Converter

The decrypted PCM is converted to parallel

form by SIPO converter. A clock of 64KHz
is provided to the converter. The output of
SIPO is given to DAC which converts the
signal back to analog form. The DAC used is
DAC0800. The circuit diagram for converting
the serial digital speech information into its
original form is shown in the Fig. 5. The
decrypted speech at pin 8 of IC 10 is fed to
the serial input pins 1 and 2 of an 8-bit
serial-to-parallel converter 74LS164 ( IC 12 ). It
also requires a 64KHz clock of ADC. The 8bit parallel PCM data is then converted to the
analog signal by using latch 74LS374 ( IC13 )
and an 8-bit ADC chip DAC0800 ( IC 14 ).
2.3.3

Filter

This unit is used for reconstruction of the

speech signal, since the output of DAC is in
stair-case form. It has a cut-off frequency of
3.4KHz. The filter used is designed using
IC741. It is a low pass filter. The output at
pin 4 of IC 14 is a staircase current
approximation of the input speech signal to
the system. A low impedance voltage output is
derived from this current output by using
transimpedance amplifier A741 ( IC 15 ). The
output of I to V converter is given to the
second order low pass filter. The gain of the
filter is set by Ri and Rf . While the higher
cutoff frequency is determined by R1 ,R2 ,C1,
C2 .

2.3.4 Power Amplifier

3. CONCLUSION

The reconstructed signal is given to the

power amplification before feeding it to
speaker.
Serial
parallel
converter

Latch

Dac

LPF

Fig. 5 Block Diagram of DSSS Receiver

Clock Generator: Clock generator is the section
which uses a 1MHz crystal for generation of
a 1MHz signal from which other 64KHz and
8KHz
signals
are
generated
for
synchronization.

A digital speech security system has been

designed and implemented. It brings out various
operations involved in the process .It is an
effective tool for maintaining security. Front panel
test panel test point can be provided and can be
used to show waveforms of clocks, PCM signals
,PN sequence ,encrypted speech ,receiver output
waveforms before and after filtering . Depending
upon the switch position noise output or desired
signal output can also be demonstrated . For
demonstration purpose a sinusoidal signal of 2V
p-p is preferred, a speech signal from a
microphone amplifier can also be applied and the
output
can
also be monitored using
a
loudspeaker.
REFERENCES

Divide by 16 and Divide by 8 Counters:

These
blocks
are used to generate
64KHz
and
8KHz
signals
for
synchronization of the shift registers and serial
to parallel converters used in the system. For
this we use binary counters IC74LS93 which
is used to reduce the bit rate or data rate.
Mono flip-flop:This is used for latching the
output of the divide by 8 counter in order
that the shift registers and serial to parallel
converters get synchronized i.e. it is used to
produce a delay till the divide by 64 counter
gives its output to the next stage. It is also
used to provide correct signal to the PL pin
of IC 74LS165 (PISO).
In the circuit
diagram a 1MHz TTL compatible clock is
generated using 74LS04 inverter gates ( IC 1 )
in crystal stabilized astable mode. This system
requires two additional clock frequencies of
64KHz and 8KHz which are obtained by
cascading two 4-bit ripple counters 74LS93 (
IC 2 and IC 3 ).

1 MHz clock
generator

Divide by
16 counter

Divide by 8
counter

MONO
F/F

Fig. 6 Block Diagram of Sync Generator

[1]

[2]

[3]

[4]

Herbert Taub and Donald L. Schilling,

Principles of Communication Systems,
Tata
McGraw-Hill
Publishing
Company Limited, New Delhi, Second
Edition (1991)
Dennis Roddy and John Coolen,
Electronic Communication, PrenticeHall of India Private Limited, New
Delhi, Third Edition (1987).
Albert Paul Malvino and Donald P.
Leach,
Digital
Principles
and
Applications, McGraw Hill Book
Company, New Delhi, Fourth Edition
(1986)
Ramakant A. Gayakwad, OP-AMPS
and
Linear
Integrated
Circuits,
Prentice-Hall of India Private Limited,
New Delhi, Second Edition (1988)

PULSE CODE MODULATED SPEECH

SYSTEM

0.3-3.4 KHz
Voice
Input

Level

2 Vp-p

Shifter

S/H
&
ADC

PN SEQUENCE GENERATOR &

ENCRYPTOR/DECRYPTOR

Parallel
To Serial
Converter

Modulo-2

DDER

XHL

1 Mhz
Clock
Generator

S1

Divide
By
16
Counter

Divide
By 8
Counter

Mono
F/F

Pseudorandom
Noise
Generator

PULSE CODE DEMODULATOR SECTION

Voice
Output

LPF
DAC

Latch

Serial
Parallel
Converter

Fig. 1 Block Diagram of Digital Speech Security System

Modulo-2
Adder