Chapter 9

Overview of Assembly Language

Chapter 9

91 Assembler directives provide information to the assembler that is useful during the assembly process. These are not the processor instructions.

Chapter 9

92 Both statements allocate two bytes of uninitialized contiguous storage. int1 is byte size whereas
int2 is word-size data.

Chapter 9

93 The OFFSET directive gets the address at assembly time. Since the contents of SI are known
only at runtime, it does not make sense to use OFFSET directive here (we should use the lea
instruction instead).

Chapter 9
94 (a) 200 bytes (each word is initialized to 1)
(b) 25 bytes (%%$$$ pattern is repeated five times)
(c) 100 bytes (1122211222112221122211222 pattern is repeated four times)
(d) 2 bytes (initialized to 2300)
(e) 2 bytes (initialized to 40000)
(f) 17 bytes (Finders fee is:,0)
(g) 24 bytes (string as given in the exercise)

Chapter 9

95 Assemblers provide two directivesEQU and =to define constants, numeric as well as literal
constants. The EQU directive can be used to define numeric constants and strings, whereas the =
directive can be used to define numeric constants only. When using the EQU directive, the symbols
that have been assigned a value or a string cannot be reassigned another value or string in a given
source module. Such redefinitions are allowed by the = directive. These two directives can used
to define simple macros.
A more general definition of macros is facilitated with MACRO and ENDM directives. The directives
allow definition of macros that resemble procedures in the sense they can take parameters just like
the procedures.

Chapter 9

96 Just as with procedures, using parameters with macros aids in writing more flexible and useful
macros. For example, the micro
multAX_by_16

MACRO
sal
ENDM

AX,4

always multiplies AX by 16. By using parameters, we can generalize this macro to operate on a
byte, word, or doubleword located either in a general-purpose register or memory. The modified
macro is
mult_by_16

MACRO
sal
ENDM

operand
operand,4

Chapter 9

97 Addressing mode refers to specification of an operand. Several addressing modes are provided to
efficiently access various data structures supported by high-level languages.

Chapter 9

98 Register addressing mode is the most efficient one as the required data are available in processor
registers. There is no need to access the memory for the operands.

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Chapter 9

99 No, we cannot use the immediate addressing mode with the inc instruction, as this instruction
requires only one operand. Immediate addressing is used to specify constant operands.

Chapter 9

11

910 In the direct addressing mode, the address is contained in the instruction. On the other hand, the
indirect addressing mode uses a register to specify the required address.
The direct addressing can be used to access simple variables. The main drawback of this addressing
mode is that it is not useful for accessing complex data structures such as arrays and records that
are used in high-level languages. The indirect addressing mode remedies this deficiency.

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Chapter 9

911 For 16-bit segments, only BX, BP, SI, and DI registers are allowed to hold the offset. By default,
effective address in registers BX, SI, or DI is taken as the offset value into the data segment (i.e.,
relative to the DS segment register). On the other hand, for the BP register, the offset is used to
access a data item from the stack segment (i.e., relative to the SS segment register).

Chapter 9

13

912 OFFSET/mov combination is better if you can use it in the program as the overhead is incurred
only at the assembly time (once per program independent of how many times you run it). The
lea instruction is executed at run time. Thus, you incur overhead every time you run the program.
However, there may be instances where the required information is not available at assembly time
(such as a pointer received as an argument in a procedure call). In which case, you have to use the
lea instruction.

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Chapter 9

913 The first xchg places the AX value in operand1. The third xchg instruction stores this value
back in AX.

Chapter 9
914 Whether the assembler allows or not, the following instructions do not make sense:
(b), (c) different operand sizes
(e) Both operands are in memory
(f) Cannot load a value into IP
(g), (h) Destination operand cannot be a constant
(k) xchg cannot have a constant as one of the operands
All others are valid.

15

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915 (a) 00005571H
(b) 3534H
(c) 00003001H
(d) 3539H
(e) 00000BB8H
(f) 94E0H
(g) 00060720H
(h) 094EH
(i) 00000181H
(j) D5CDH
(k) EF4CH
(l) F942H

Chapter 9

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Chapter 9
916 (a) mov
(b) mov
(c) mov
(d) mov

BX,1
AX,10
AX,10
BX,1

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Chapter 9

917 (a) Changes the sign of the number in AX i.e., converts the number in AX to negative value in 2s
complement representation
(b) Same as (a)
(c) Multiplies contents of AL by 16 and stores the result in the DX register
(d) Multiplies contents of AL by 10 and stores the result in the DX register

Chapter 9
918 You dont need the initial value of AX.
(a) FFH
(b) 00H

19

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Chapter 9

919 Both inc and dec update the value by 1. Therefore, the value always goes through the zero state,
which can be detected by the zero flag.

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Chapter 9

920 The add instruction can be implemented using clc and adc. For example, the add instruction
add

AX,BX

can be implemented as
clc
adc

AX,BX

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Chapter 9

921 We show this by means of an example. The

adc

AX,BX

instruction can be implemented by using add as

jnc
inc

skip
AX

add

AX,BX

skip:

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Chapter 9
922 The following code fragment multiplies the number in AX by 12:
add
add
mov
add
add

AX,AX
AX,AX
BX,AX
AX,AX
AX,BX

;
;
;
;
;

AX
AX
BX
AX
AX

=
=
=
=
=

2*AX
4*AX
4*AX
8*AX
12*AX

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Chapter 9

923 The neg instruction changes sign of a number (negative numbers are in 2s complement representation).

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Chapter 9
924 The following code implements the neg
not
add

AX instruction:

AX
AX,1

A better version is (though it does not use the add instruction)

not
inc

AX
AX

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Chapter 9

925 We can implement logical and by first complementing each input, then applying the logical or operation, and finally the logical not operation. Here is an example that implements and
AL,BL.
not
not
or
not

AL
BL
AL,BL
AL

Does it relate to the digital logic material? Certainly. We have used the de Morgans law from
Chapter 2 (see Table 2.4 on page 55).

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Chapter 9

926 We can implement logical or by first complementing each input, then applying the logical and operation, and finally the logical not operation. Here is an example that implements or
AL,BL.
not
not
and
not

AL
BL
AL,BL
AL

Does it relate to the digital logic material? Certainly. We have used the de Morgans law from
Chapter 2 (see Table 2.4 on page 55).

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Chapter 9

927 The and and or instructions can be used together to cut and paste bits from two or more
operands. The and can be used to isolate selected bitsanalogous to the cut operation. The or
instruction can be used to paste the bits. For example, the following code creates a new byte in
AL by combining odd bits from AL and even bits from BL registers.
and
and
or

AL,55H
BL,0AAH
AL,BL

; cut odd bits

; cut even bits
; paste them together

The first and instruction selects only the odd bits from the AL register by forcing all even bits to
0 by the use of the mask 55H (01010101B). The second and instruction selects the even bits by
using the mask AAH (10101010B). The or instruction simply pastes these two bytes together to
produce the desired byte in the AL register.

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Chapter 9

928 The basic idea is to detect each bit and use either and or or instruction to change the bit. We illustrate this by means an example that complements one bit (the least significant bit). The following
code complements the least significant bit in the AL register:
test
jz
bit_is_1:
and
jmp
bit_is_0:
or
skip1:

AL,1
bit_is_0
AL,0FEH
skip1
AL,1

Using a loop and a shift instruction, we can complement the remaining bits.

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929 shl can be used but not shr because it does not copy the sign bit.

Chapter 9

Chapter 9
930 shl can be used but not shr because it copies the sign bit.

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Chapter 9

931 The code is shown below:

mov
and
and
or

DL,AL
DL,0FH ; lower order 4 bits of AL are in DL
AH,0F0H
DL,AH

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Chapter 9
932 The code is shown below:
mov
shl
shr
rcr
shr
rcr
shr
rcr
shr
rcr

DL,AL
DL,4
AH,5
DL,1
AH,1
DL,1
AH,1
DL,1
AH,1
DL,1

You can also use a loop that iterate four times as shown below:
mov
shl
shr
mov
loop_back:
shr
rcr
loop

DL,AL
DL,4
AH,4
CX,4
AH,1
DL,1
loop_back

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Chapter 9

933 This can be done by using xor instruction as shown below:

xor

AL,55H

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Chapter 9
934 The code is shown below:
mov
loop_back:
shr
jc
shift_1:
stc
jmp
shift_0:
clc
skip1:
rcr
ror
loop

CX,4
AL,1
shift_0

skip1

AL,1
AL,1
loop_back