Combinational

Equivalence Checking:
Virendra Singh
Associate Professor
Computer Architecture and Dependable Systems Lab
Department of Electrical Engineering
Indian Institute of Technology Bombay
http://www.ee.iitb.ac.in/~viren/
E-mail: viren@ee.iitb.ac.in

EE-709: Testing & Verication of VLSI Circuits

Lecture 8 (29 Jan 2015)

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Formal Equivalence Checking

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Combinational Equivalence Checking (CEC)

Currently most prac1cal and pervasive
equivalence checking technology
Nearly full automa1on possible
Designs of up to several million gates veried in a
few hours or minutes
Hierarchical verica1on deployed
Full chip verica1on possible
Key methodology: Convert sequen1al equivalence
checking to a CEC problem!
Match Latches & extract comb. por1ons for EC

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CEC in Todays ASIC Design Flow

RTL Design

CEC

Synthesis &
optimization

Routing

CEC
DFT insertion

CEC
ECO

CEC
IO Insertion

CEC
Placement

CEC
Clock tree synthesis

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Major Industrial Offerings of CEC

Formality (Synopsys)
Conformal Suite (Verplex, now Cadence)
FormalPro (Mentor Graphics)
Typical capabili1es of these tools:
Can handle circuits of up to several million gates at in
up to a few hours of run1me
Comprehensive debug tool to pinpoint error-sources
Counter-example display & cross-link of RTL and gate-
level netlists for easier debugging
Ability to checkpoint verica1on process and restart
from same point later
What if capability (unique to FormalPro)
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Combina1onal Equivalence Checking

Func1onal Approach
transform output func1ons of combina1onal circuits
into a unique (canonical) representa1on
two circuits are equivalent if their representa1ons are
iden1cal
ecient canonical representa1on: BDD

Structural
iden1fy structurally similar internal points
prove internal points (cut-points) equivalent
nd implica1ons

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Func1onal Equivalence
If BDD can be constructed for each circuit
represent each circuit as shared (mul1-output) BDD
v use the same variable ordering !
BDDs of both circuits must be iden=cal
If BDDs are too large
cannot construct BDD, memory problem
use par11oned BDD method
decompose circuit into smaller pieces, each as BDD
check equivalence of internal points
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Func1onal Decomposi1on
Decompose each func1on into func=onal blocks
represent each block as a BDD (par==oned BDD method)
dene cut-points (z)
verify equivalence of blocks at cut-points
star1ng at primary inputs
F

g2

f2
z

z
g1

f1
x

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Cut-Points Resolu1on Problem

If all pairs of cut-points (z1,z2) are equivalent
so are the two func1ons, F,G

If intermediate func1ons (f2,g2) are not equivalent

the func1ons (F,G) may s1ll be equivalent
this is called false nega1ve
F

Why do we have false nega1ve ?

func1ons are represented in terms of
intermediate variables
to prove/disprove equivalence must
represent the func1ons in terms of
primary inputs (BDD composi1on)

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g2

f2
z1

z2
g1

f1
x

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Cut-Point Resolu1on Theory

Let f1(x)=g1(x) !x
if f2(z,y) ! g2(z,y), !z,y then f2(f1(x),y) ! g2(f1(x),y) ! F ! G
if f2(z,y) ! g2(z,y), !z,y !! f2(f1(x),y) ! g2(f1(x),y) ! F ! G
F

G
g2

f2
z

z
g1

f1
x

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We cannot say if F G or not

False nega=ve
two func1ons are equivalent,
but the verica1on algorithm
declares them as dierent.

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Cut-Point Resolu1on

How to verify if nega1ve is false or true ?

Procedure 1: create a miter (XOR) between two

poten1ally equivalent nodes/func1ons
perform ATPG test for stuck-at 0
nd test padern to prove F ! G
eicient for true nega1ve
(gives test vector, a proof)
inecient when there is no test

0, F ! G (false negative)
1, F ! G (true negative)

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Cut-Point Resolu1on

Procedure 2: create a BDD for F ! G

perform sa1sability analysis (SAT) of the BDD

if BDD for F !G = !, problem is not sa1sable, false
nega1ve
BDD for F !G ! !, problem is sa1sable, true nega1ve
G

F ! G =
=

!, F ! G (false negative)

Non-empty, F ! G

Note: must compose BDDs until they

are equivalent, or expressed in terms
of primary inputs

the SAT solu1on, if exists, provides a test vector (proof of non-equivalence) as in

ATPG
unlike the ATPG technique, it is eec1ve for false nega1ve (the BDD is empty!)
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Sequen1al Equivalence Checking

Represent each sequen1al circuit as an FSM
verify if two FSMs are equivalent

Approach 1: Reduc1on to combina=onal circuit

unroll FSM over n 1me frames (aden the design)
x(1)

x(2)

M(t1)
s(1)

x(n)

M(t2)

s(2)

M(tn)
s(n)

Combinational logic: F(x(1,2, n), s(1,2, n))

check equivalence of the resul1ng combina1onal circuits

problem: the resul1ng circuit can be too large too handle

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Sequen1al Verica1on
Approach 2: Based on isomorphism of state transi1on graphs
two machines M1, M2 are equivalent if their state transi1on
graphs (STGs) are isomorphic
perform state minimiza1on of each machine
check if STG(M1) and STG(M2) are isomorphic
1/0
0/0

0
1/0

1/1 1
2

0/1

0/1

State min.

1/0
0

M1

0/1

0/0

M1min

1.2

1/1
1/0

0/1

0/0

M2

1
1/1

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State Minimiza1on
X-Successor If an input sequence X takes a machine
from state Si to state Sj, then Sj is said to be the X-
successor of Sj

Strongly connected:- If for every pair of states (Si, Sj ) of

a machine M there exists an input sequence which
takes M from state Si to Sj, then M is said to be
strongly connected

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State Equivalence
Two states Si and Sj of machine M are
dis1nguishable if and only if there exists at least one
nite input sequence which, when applied to M,
causes dierent output sequences, depending on
whether Si or Sj is the ini1al state
The sequence which dis1nguishes these states is
called a dis1nguishing sequence of the pair (Si, Sj)
If there exists for pair (Si, Sj ) a dis1nguishing
sequence of length k, the states in (Si, Sj ) are said to
be k-dis1nguishable
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State Equivalence
Machine M1

PS

(A, B) 1 Dis1nguishable

NS, z
X=0

X=1

E, 0

D, 1

F, 0

D, 0

E, 0

B, 1

F, 0

B, 0

C, 0

F, 1

B, 0

C, 0

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(A, E) 3 Dis1nguishable

Seq - 111

k-equivalent The states that

are not k-dis1nguishable are
said to be k-equivalent
Also r-equivalent r<k

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State Equivalence
States Si and Sj of machine M are said to be
equivalent if and only if, for every possible input
sequence, the same output sequence will be
produced regardless of whether Si or Sj is the ini1al
state
States that are k-equivalent for all k < n-1, are
equivalent
Si = Sj, and Sj = Sk, then Si = Sk

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State Equivalence
The set of states of a machine M can be
par11oned into disjoint subsets, known as
equivalence classes
Two states are in the same equivalence class if
and only if they are equivalent, and are in
dierent classes if and only if they are
dis1nguishable
Property: If Si and Sj are equivalent states, their
corresponding X-successors, for all X, are also
equivalent
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State Minimiza1on Procedure

1. Par11on the states of M into subsets s.t. all states in same
subset are 1-equivalent
2. Two states are 2-equivalent i they are 1-equivalent and
their Ii successors, for all possible Ii, are also 1-equivalent
PS

NS, z

P0 = (ABCDEF)

X=0

X=1

E, 0

D, 1

P1 = (ACE), (BDF)

F, 0

D, 0

E, 0

B, 1

P2 = (ACE), (BD), (F)

F, 0

B, 0

P3 = (AC), (E), (BD), (F)

C, 0

F, 1

B, 0

C, 0

P4 = (AC), (E), (BD), (F)

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Machine Equivalence
Two machines M1, M2 are said to be equivalent if and only
if, for every state in M1, there is corresponding equivalent
state in M2
If one machine can be obtained from the other by relabeling
its states they are said to be isomorphic to each other
PS
AC -
E-
BD -
F-
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NS, z
X=0
, 0
, 0
, 0
, 0
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X=1
, 1
, 1
, 0
, 0
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State Equivalence - Example

Machine M2
PS
NS, z

P0 = (ABCDEFG)

X=0

X=1

E, 0

C, 0

C, 0

A, 0

P2 = (AF) (BCDG) (E)

B, 0

G, 0

P3 = (AF) (BD) (CG) (E)

G, 0

A, 0

F, 1

B, 0

P4 = (A) (F) (BD) (CG) (E)

E, 0

D, 0

D, 0

G, 0

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P1 = (ABCDFG) (E)

P5 = (A) (F) (BD) (CG) (E)

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Reachability-Based Equivalence Checking

Approach 3: Symbolic Traversal Based Reachability Analysis
Inputs

M1

S0

Outputs
=?

M2

S1

S0
S1

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Product Machine

Build product machine of M1 and M2

Traverse state-space of product machine
star1ng from reset states S0, S1
Test equivalence of outputs in each state
Can use any state-space traversal
technique
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Thank You
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