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7.5 The 555 timer

The 555 integrated circuit is a general-purpose timer that can be configured

to give accurate time delays or oscillation frequencies. It is produced by
several semiconductor manufacturers; for example, National Semiconductor
(LM555), Texas Instruments and Maxim. A CMOS version of the 555 timer
allows working over a wider voltage range and also draws less current. The
CMOS version suffers from increased timing drift with temperature, but is
otherwise identical in performance.
The 555 timer comprises two comparators, a flip-flop (set/reset bi-stable
latch), a switch transistor and an output stage. The reference level of one comparator is fixed at a 1/3Vcc and the other is fixed at 2/3Vcc, these levels are
maintained by three equal resistors in the device which are connected across
the supply voltage Vcc. The comparator outputs are used to set and reset the
flip-flop. The flip-flop, in turn, drives both the output buffer and the switch
transistor. These internal connections are shown in Figure 7.25.
Vcc
8

Threshold
6

Reset
4

R
+
_

Control
5

Output
3

R
+

Trigger
2

Discharge
7

R
Ground
1

Figure 7.25 Schematic of 555 timer

The control voltage terminal (pin 5) allows external control of the upper
and lower comparator trip points. This allows astable circuits to be frequency
modulated. Most circuits do not use this facility. Instead, it is advisable to
have a small capacitor between pin 5 and ground, this reduces the chance
of false triggering to power supply noise.
7.5.1

The 555 timer, astable operation

Figure 7.26 gives the external connections for an astable oscillator. This
circuit allows the duty cycle of the output waveform to be set by selection
of timing resistor values.
An externally connected timing capacitor C is charged up towards the
positive supply voltage through external resistors RA  RB. When the voltage
across the capacitor reaches the reference level of the upper comparator
(2/3Vcc), the comparator forces the state of the flip-flop to change, which
then turns on the switch transistor. The capacitor discharges through resistor

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Comparator, monostable and oscillator circuits 193

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10 V Supply
RA
4
3

7
555 Timer

RB

Output
1

10nF

Ground (0 V)

Figure 7.26 555 timer functional schematic; external connections for freerunning operation
RB until the voltage across it falls to the reference level of the lower
comparator (1/3Vcc). This comparator then forces the state of the flip-flop to
change again, which in turn turns off the switch transistor and the cycle
repeats.
The oscillation frequency is given by:
f

1.44
(RA  2RB) C

The duty cycle of the square wave output is determined by the ratio of RA
and RB:
Duty 

RA  RB
RA  2RB

An accurate 50 per cent duty cycle can be obtained from a modified version
of this circuit, as shown in Figure 7.27.
10 V Supply
10k

8
555 Timer

10 nF

Alternate
Output

Output
R

Ground (0 V)

Figure 7.27 50 per cent duty cycle oscillator using CMOS 555 timer

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In Figure 7.27, the timing capacitor C is charged and discharged from the
555 timer output, through resistor R. The CMOS output swings from Vcc to
ground, so the voltage swing and the trip points are symmetrical about midrail. Discharge pin 7 is not connected to the capacitor, but provides an
alternate output.

7.5.2 The 555 timer, monostable operation

A typical circuit for monostable operation of the 555 is given in Figure 7.28.
The DC voltage at the trigger terminal (pin 2) should be set above the
threshold level of the lower comparator (1/3Vcc); this holds the timing capacitor in the discharged condition (output low). When a negative going pulse
forces the voltage on pin 2 to fall below 1/3Vcc, this triggers the flip-flop.

10 V Supply
R
Reset
4
3
Output

555 Timer
1

Trigger

10 nF

Ground (0 V)

Figure 7.28 Monostable circuit using 555 timer

Once triggered, the flip-flop output state changes, to turn off the switch
transistor that is connected across the timing capacitor. The timing capacitor
then charges up exponentially through R towards Vcc, with the time constant
CR. When the voltage across the timing capacitor reaches the threshold
level of the upper comparator (2/3Vcc), the flip-flop is reset. The switch transistor is turned on, discharging the timing capacitor. The cycle is now
complete.
Once the circuit is triggered it is insensitive to further triggering pulses
until the timing period is complete. The triggering pulse width must be less
than the timing period for proper operation. Connecting the reset terminal
to ground will interrupt the timing period; this action turns on the switch
transistor, which prevents the capacitor from charging. The reset terminal
(pin 4) is normally held at Vcc.
The duration of the timing period T, during which the output level is at
a high state, is given by:
T  ln (0.333)RC
or T 1.1 RC