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ME 7292 Control System Labs

Spring 2014
Week 2

Discretization, Quantization and Sampling

Kirti Deo Mishra


mishra.98

January 30, 2014

Contents
1 Objective

2 Equipments

3 Experiment Procedure
3.1 Assignment 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Assignment 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Assignment 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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4 Results and Analysis


4.1 Assignment 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.2 Assignment 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4.3 Assignment 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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5 Conclusion

6 Appendix

List of Figures
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2
3
4
5

Simulink Screen Shot . . . . . . . . . . . . . . . . . . . . . . .


Control Desk Screenshot . . . . . . . . . . . . . . . . . . . . .
Overall delay for two sampling period - 0.0001s and 0.00002s
Overall Time delay - Close View . . . . . . . . . . . . . . . .
Quantisation effect . . . . . . . . . . . . . . . . . . . . . . . .

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3
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Decimal To Binary Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .


Binary to Decimal Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

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4

List of Tables
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2

Objective
1. To understand data formats and its conversion between fixed-point data and floating-point
data.
2. To evaluate the overall time-delay when implementing a digital controller on dSpace.
3. To investigate quantization error.

Equipments

Equipments used for the experiment mainly were


1. Digital Computer
2. dSpace DS1104 Floating -Point Controller Borad
3. Two BNC cables
4. T-Joint Connector

Experiment Procedure

Overall, experimentation consisted of making of simulink model, converting the model into an
equivalent C code which could be loaded on the controller board and real time control of the
simulink model through control desk (GUI for DSpace board) software. This section talks about
the experimental procedure adopted for assignments and the next section talks about results and
analysis.

3.1

Assignment 1

A matlab code (shown in appendix) was written to make the conversion from the binary to decimal
and vice-versa in an automated manner. Two external m files were used namely f p dec2bin16.m
and f p bin2dec16.m to make the conversion possible.

3.2

Assignment 2

1. A BNC cable was used to connect port ADCH1 to DACH1.


2. A simulink model with a fixed time step of 0.0001(this step was again repeated with a time
step of 0.00002) was built and converted to an equivalent C-code.

Figure 1: Simulink Screen Shot

3. A custom interface in Control Desk environment was created.

Figure 2: Control Desk Screenshot

3.3

Assignment 3

1. The resolution of ADCH1 ADCH5 were calculated and found to be 3.0518X105 and 4.8828X104
respectively(without the gain of 10).
2. DACH1 was connected to both ADCH1 ADCH5 using two BNC cables and a T-joint connector.
3. Changes were made to the previous simulink model to abtain the following (fixed step).
4. Corresponding changes were made in Control Desk interface.
3

Results and Analysis

In this section, results for various assignments and corresponding analysis is presented.

4.1

Assignment 1

1. Following decimal numbers were converted to binary format,


S.No
1
2
3
4
5
6

Decimal Numbers
0
100
1.56
-3.5
-135000
130000

Binary Number
0000000000000000
0101011000111111
0011111000111101
1100001011111111
1111110000011110
0111111111101111

Table 1: Decimal To Binary Conversion


2. Following binary numbers were converted to decimal format,
S.No
1
2
3
4

Binary Numbers
0111010111101101
0100010101101100
1111010101111111
1000010111101001

Decimal Number
24272
5.4219
-22512
-9.0182e-05

Table 2: Binary to Decimal Conversion


3. The maximum value of the 16 bit number can be found out by
(1)sign (1 +

10
X
[di ]21 )X2e15
i=1

For the maximum number we take the sign bit as positive(0), exponent part to be 11110(as
11111 is reserved for infinity) and fraction part to be 1111111111. The bias was found by
e=

4
X

[e4j ]X2j

j=0

Substituting the values we get, 65504.


The minimum number which we can find is -65504 (other possible case is 0 or 214 if we want
minimum positive number).
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4.2

Assignment 2

1. Two different set of data for two different sampling frequencies are shown below. Clearly
from the these curve we can see the delay between the original and the delayed signal. Also
it is evident that delay reduces due to by increasing the sampling frequency of the signal.
Close-ups for these figures is shown next which also suggests the dependency of delay on
sampling period.

Figure 3: Overall delay for two sampling period - 0.0001s and 0.00002s

(a) Sampling - 0.0001 s

(b) Sampling - 0.00002 s

Figure 4: Overall Time delay - Close View


2. From the closer view of the above curves we can say that the delay introduced for the two
cases are 0.0001 sec and 0.00002 sec respectively.
3. Causes of delay for the two cases are as follows:
Sample And Hold delay - This delay is introduced since data in a digital system is discrete(and also quantized). This discrete set of data is a result of sampling process(which
is done at a sampling frequency). This sampled data is held untill the next data point
is encouter. Now when these sampled data points are reconstructed to give back the
analog signal a delay is introduced due to zero-order hold. This delay is generally given
by Tsampling
delay =
2
Calculation/Conversion Delay - This delay is introduced due to the time taken by
the processor to make any calculation if any. In this case even the experiment is pretty
simple but it involves data point conversion from decimal to binary and vice versa. This
delay can be anywhere between very small to sampling time period. As far as conversion
delay is concerned it is 2s for channel 1-4 ADC, 0.8s for channel 5-8 ADC, 10s for
DAC channels.
4. The overall delays are different for the two cases becauses sampling frequency for the two
cases are different as suggested by the expression above. Also they are different from the
theoretical value due to the calculation delay which is dependent on processors speed.

4.3

Assignment 3

1. Below is shown the comparison curve for the two channel ouputs(ADCH 1 ADCH 5) with
the orignial sine wave for the first case when the amplitude is 0.001. Clearly we can see
from the curve below that the black curve which is the output of the 16 bit port (which has a
higher resultion of 3.0518X104 ) is able to follow the original plot(green curve) more closely as
compared to the 12-bit port(which has a resolution of 4.8828X103 ). The resolution basically
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tells us the minimum value a ADC can pick up for quatisation. Since the amplitude for the
sine wave in this case is 0.001, the ADCH 5 is not able to pick anything(as this amplitude is
less than its resolution) and technically should be zero. The spikes seen in the red curve are
possible noises which is also corroborated by their random distribution.

Figure 5: Quantisation effect


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2. In the next case when amplitude of the sine wave is 0.01, the ADCH 5 is able to follow the
original curve as it is able to quantize the input signal(as now the input signal is greater than
the 4.8828X103 value). Again we can see that ADCH 1 is better replication of the sine
wave since its resolution is less and thus is able to quantize to the values closer to the original
signal.

Conclusion

Fundamentals of a digtal controller and practical problems in the implementation were understood.
In particular the inherent properties of a digital controller namely number conversion, overall delay
and quantisation was understood. Moreover the dependency of these properties on the sampling
frequency of the controller and the magnitude of the signals involved were tackled with.

Appendix

%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
%
ME 7292 Control System Labs
%
Week 2
%
Kirti Deo Mishra(# 98)
%
%
The following script coverts binary decimal and processes
%
the data from the control desk environment into meaning figures.
%
%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

clc
clear all
close all
% Assignment 1
% Decimal to Binary Conversion
% Array of decimal values to be converted to binary.
value1 = [0, 100, 1.56, 3.5, 135000, 130000] ;
% Initiating the reults array
results1 =[];
% Displaying results
disp(['Decimal Number ', '
for i=1:length(value1)

Binary Number'])

results1 = [results1; fp dec2bin16(value1(i))];


disp([num2str(value1(i)), '
', results1(i,:)])
end
% Binary to Decimal Conversion
% Array of binary numbers to be converted

value2 = ['0111010111101101'; '0100010101101100'; ...


'1111010101111111'; '1000010111101001'] ;
% Initiating array of results
results2 =[];
% Displaying Results
disp(['Binary Number ', ' Decimal Number'])
for i=1:size(value2)
results2 = [results2; fp bin2dec16(value2(i,:))];
disp([value2(i, :),'
', num2str(results2(i, 1))])
end
% Assignment 2
clc
clear all
% loading data files exported by Control Desk
load part1.mat
load part2.mat
figure('color', [1 1 1])
plot(part1.X.Data, part1.Y(1,2).Data,'r',...
part1.X.Data, part1.Y(1,3).Data,'g')
grid on
xlabel('Time(s)')
ylabel('Signal')
legend('Original Signal', 'Delayed signal')
title('Overall time dalay 0.0001 sec sampling')

figure('color', [1 1 1])
plot(part2.X.Data, part2.Y(1,2).Data,'r',...
part2.X.Data, part2.Y(1,3).Data,'g')
grid on
xlabel('Time(s)')
ylabel('Signal')
legend('Original Signal', 'Delayed signal')
title('Overall time dalay 0.00002 sec sampling')
% Assignment 3
clc
lear all
% Loading Data files exported from the control desk
load assignment 3a.mat
load assignment 3b.mat
figure('color', [1 1 1])
plot(assignment 3a.X.Data, assignment 3a.Y(1,1).Data,'k',...
assignment 3a.X.Data, assignment 3a.Y(1,2).Data,'r',...
assignment 3a.X.Data, assignment 3a.Y(1,3).Data,'g')
xlabel('Time(s)')
ylabel('Signal')
legend('ADCH1(16 bits) signal', 'ADCH5(12 bits) signal', 'Original Signal')

grid on
title('Quantisation effect 0.001 amplitude')
figure('color', [1 1 1])
plot(assignment 3b.X.Data, assignment 3b.Y(1,1).Data,'k',...
assignment 3b.X.Data, assignment 3b.Y(1,2).Data,'r',...
assignment 3b.X.Data, assignment 3b.Y(1,3).Data,'g')
xlabel('Time(s)')
ylabel('Signal')
legend('ADCH1(16 bits) signal', 'ADCH5(12 bits) signal', 'Original Signal')
grid on
title('Quantisation effect 0.01 amplitude')

*************************

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