Professional Documents
Culture Documents
M.MURALI
Email-id: muralimunaswamy@gmail.com
Mobile: 9791105891
Objective:
Seeking a challenging position to deploy and use my technical, academic knowledge and
experience in the best possible method to growth of the organization.
Work experience:
Organization name : Oxford Engineering College.
Designation
Duration
Subjects Handle
Projects Guided
: 2 UG Projects.
1) ASIC Implementation of CORDIC.
2) ASIC Implementation of FIR Filter using DAA.
Other Projects
Duration
Academic records
Degree
B.E(ECE)
College
Institution
passing
Anna university of
College, Trichy.
technology, Trichy.
Athimanjeripet.
Govt. Hr. Sec. School,
SSLC
Year
Oxford Engineering
University/
Athimanjeripet.
2011
% Of Marks
77.5
State board
2007
69.91
State board
2005
80
Technical skills:
Languages
: C, C++.
Mini projects:
Title
Project :
Title
Achievements:
First prize for recitation competition from Andhra Samskrithi Manjari, Athimanjeripet.
Second prize for mini project of Rain water wiper in Oxford engineering college,
Trichy.
Presented a paper on An ATPGA for low power VLSI design using ring counter and
LFSR in Indra Ganesan College of engineering, Trichy.
Undergone In-Plant training in BSNL, Trichy, for five days from 16-06-09 to
20-06-2009.
Attended Soft Skill Development program in Oxford College, Trichy for five days from 2308-2010 to 28-08-2010.
Participated in the two day workshop p on Network On Chip Architectures during 23rd to
25th Feb 2012 at Oxford Engineering College, Trichy.
Attended the six-day Train the-trainer Program on Analog System Design using
ASLKv2010 Starter Kit held at Texas Instruments India, Bangalore during 26-31 March,
2012.
Participated in Staff Development Program on New and Emerging Trends in Image and
Video Processing from 13-24 May 2013, at Jayaram College of Engineering and Technology,
Trichy.
Projects Handle
Project Title
Description
: In this project multiplexer has been proposed for the ASIC implementation of unrolled
CORDIC processor. The efficacy of this approach is studied for the implementation
on FPGA. For this study, both non pipelined and 2 level pipelined CORDIC with 8
stages and using two schemes one using adders in all the stages and another using
multiplexers in the second and third stages.
Project Title
Description
: Input vector monitoring concurrent built-in self-test (BIST) schemes perform testing
during the normal operation of the circuit without imposing a need to set the circuit
offline to perform the test. These schemes are evaluated based on the hardware
overhead and the concurrent test latency (CTL), i.e., the time required for the test to
complete in FPGA tools, whereas the circuit operates normally. The proposed
scheme is shown to perform significantly better than previously proposed schemes
with respect to the hardware overhead and CTL tradeoff.
Project Title
Description
: A new high-speed divide-by-4/5 counter is developed. Based on this divide-by4/5counter, a 3V 2M -1.1 GHz dual-modulus divide-by-128/129 prescaler
designed with 0. 90nm CMOS technology is presented.
Project Title
Description
Project Title
: Self controllable voltage level Circuit for low power high-speed 7T-SRAM cell.
Description
: A low leakage power 7T SRAM is designed in this project, The stand-by leakage
power of 7T sram is reduced by incorporating a newly-developed leakage current
reduction circuit called a Self-controllable Voltage Level (SVL) circuit.
Simulation result of 7t SRAM design using CADENCE tool shows the reduction
in total average power.
Project Title
: Design and Simulation of Low Power Dynamic Logic Circuit Using Footed
Diode Domino Logic.
Description
: In this project, we proposed a new technique to reduce power dissipation for domino
logic circuits. In this proposed circuit we put a diode on the foot of domino logic
circuit which results in power reduction as compared to reported and conventional
domino logic. We are using NMOS as a diode and due to this extra diode (NMOS), in
precharge period leakage current reduce due to stacking effect.
Project Title
Description
Project Title
: Low Power Wallace Multiplier Using Gate Diffusion Input Based Full Adders.
Description
: In this work gate diffusion input technique is used to reduce the leakage power in
4*4Wallace tree multiplier which has been designed by using one bit full adder. The
proposed method replaces all the full adders in 4*4 Wallace tree multiplier by gate
diffusion input technique based full adders. The full adders are the main block of
Description
: In this project we introduce a new dual dynamic node hybrid flip-flop (DDFF) and a
novel embedded logic module (DDFF-ELM) based on DDFF. The proposed designs
eliminate the large capacitance present in the precharge node of several state-of-the-art
designs by following a split dynamic node structure to separately drive the output pullup and pull down transistors.
Personal information:
Full Name
: Murali.M
Date of Birth
: 30.06.1989.
Marital Status
: Single.
Nationality
: Indian.
Languages know
Passport Number
: M0168778
Date of Issue
Valid Until
Permanent Address
Reference:
1.
2. Mr.C.SRINIVASAN, M.E,
CEO, Polenza Technologies,
Singaperumal Kovil,
Trichy-09.
Chengalpattu.
Place: Chennai.
Signature
Date: 12-02-2015
(MURALI.M)