IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO.

10, OCTOBER 2000

1453

A 1.1-GHz CMOS Fractional-N Frequency

Synthesizer with a 3-b Third-Order
Modulator

16

Woogeun Rhee, Member, IEEE, Bang-Sup Song, Fellow, IEEE, and Akbar Ali

16

AbstractA 1.1-GHz fractional-N frequency synthesizer is

implemented in 0.5- m CMOS employing a 3-b third-order
modulator. The in-band phase noise of 92 dBc/Hz at 10-kHz
offset with a spur of less than 95 dBc is measured at 900.03
MHz with a phase detector frequency of 7.994 MHz and a loop
bandwidth of 40 kHz. Having less than 1-Hz frequency resolution
and agile switching speed, the proposed system meets the requirements of most RF applications including multislot GSM, AMPS,
IS-95, and PDC.
Index TermsAnalog integrated circuits, CMOS RF,
deltasigma modulation, frequency synthesizer, phase-locked
loop.

I. INTRODUCTION

HE DEMAND for low-cost universal frequency synthesizers is growing as wireless systems are diversified. Standard frequency synthesizers with integer- dividers have difficulties in meeting various specifications due to their fundamental tradeoffs between loop bandwidth and channel spacing.
The fractional- technique offers wide bandwidth with narrow
channel spacing and alleviates phase-locked loop (PLL) design
constraints for phase noise and reference spur [1], [2]. Since
it uses a lower division ratio and a higher phase detector frequency than the integer divider technique, the low-frequency
phase noise can be suppressed to a higher degree.
modFor fractional- frequency synthesis, two types of
ulators have been used [3], [4]. One is a single-loop modulator, and the other is a cascaded modulator called MASH. The
single-loop modulator has a choice of a single-bit or a multibit
output depending on the quantizer while the MASH architecture
outputs only multibits. For wide-band frequency synthesizers,
the modulator architecture should be carefully selected. In addition to the in-band noise shaping, the out-of-band shaped noise
significantly affects the synthesizer performance by raising the
high-frequency phase noise. The high-frequency noise is difficult to suppress with the finite number of the PLL loop filter
poles. Comparing the output bit patterns of the multibit modulator and the MASH, the former can achieve a more desirable

Manuscript received December 2, 1999; revised May 10, 2000.

W. Rhee was with the Department of Electrical and Computer Engineering, University of Illinois, Urbana, IL 61801 USA. He is now with
Conexant Systems, Inc., Newport Beach, CA 92660-3007 USA (e-mail:
rheew@nb.conexant.com).
B.-S. Song was with the Department of Electrical and Computer Engineering,
University of Illinois, Urbana, IL 61801 USA. He is now with the Department
of Electrical and Computer Engineering, University of California at San Diego,
La Jolla, CA 92093 USA.
A. Ali is with Conexant Systems, Inc., Newport Beach, CA 92660 USA.
Publisher Item Identifier S 0018-9200(00)08701-1.

Fig. 1.

16 modulated fractional-N frequency synthesizer.

noise shaping for frequency synthesis, but the latter offers a simpler high-order architecture with no stability problem [5], [6].
The MASH-type modulators tend to generate wide-spread
high-frequency bit patterns, and impose more stringent requirements on the phase detector design. This work optimizes a noise
shaping function for low-spur frequency synthesis using a 3-b
third-order modulator that generates less high-frequency noise
and makes the system less sensitive to the substrate noise coupling.
In Section II, design issues related to the low phase noise
frequency synthesis are addressed. Section III highlights the
system design features, and experimental results are summarized in Section IV.
II. DESIGN CONSIDERATIONS FOR HIGH SPECTRAL PURITY
The fractional- frequency synthesis system as illustrated
in Fig. 1 obtains a fine frequency resolution by interpolating a
modulator with a
fractional division using an oversampling
modulation technique is simcoarse integer divider [3]. The
ilar to the random jittering method [7], but it does not exhibit a
phase noise spectrum due to its noise shaping property.
modulators with orders higher than two are used, the
When
PLL needs extra poles in the loop filter to suppress the quantization noise at high frequencies.
A. Bandwidth Requirement
[dBc/Hz] of the freIf the in-band phase noise of
quency synthesizer is assumed to be limited within the noise
[Hz] as shown in Fig. 2, the integrated frebandwidth of
[rms Hz] within is approximately [8]
quency noise

00189200/00$10.00 2000 IEEE

(1)

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 10, OCTOBER 2000

Fig. 2.

Dynamic range consideration in oversampled fractional division.

Fig. 3.

Third-order

16 modulator with 3-b quantizer.

Because the quantizer level in the frequency domain is equivwith the frequency
alent to the phase detector frequency
as illustrated in Fig. 2, the dynamic range of the
noise of
th-order
modulator should meet the following condition
[9].
OSR
where the effective oversampling ratio OSR
OSR

(2)

For example, when the phase detector frequency is 8 MHz, the

upper bound of the bandwidth with a third-order
modulator
to meet less than 1 -rms phase error is 195 kHz. In practice,
the required loop bandwidth is narrower than as predicted by
(6) since the quantization noise of the third-order modulator is
tapered off after the fourth pole of the PLL. In this work, the
loop bandwidth is set to 40 kHz with the third pole placed at
160 kHz.

is given by
(3)

Therefore, from (1)(3), we obtain

(4)
[rms rad] is an important factor
An integrated phase error
for synthesizers in digital communications, and it is given by
(5)
From (4) and (5), an approximate upper bound of the bandwidth
is obtained as
(6)
Equation (6) explains the effect of the integrated phase error as a
parameter, which is not included in the previous results [3], [4].

B. Noise Transfer Function

Fig. 3 shows the proposed third-order modulator with
an eight-level quantizer. The eight-level quantizer exto
pands the active division range from
without increasing
the minimum quantizer level. For high-order modulators, it has
been shown that as the number of quantizer levels increases,
the maximum passband gain of the noise transfer function
(NTF) can be increased without causing any nonlinear stability
problem [10], [11]. As the maximum passband gain of the NTF
increases, the corresponding corner frequency increases. For
example, if the input range is set to about 80% of the quantizer,
the maximum passband gain of the NTF can be set to 2.5 for
a 2-bit quantizer, 3.5 for a 3-bit quantizer, and 5.0 for a 4-bit
quantizer. The corresponding corner frequencies of the NTF
are 0.13 , 0.19 and 0.24 , respectively. This implies that
quantization noise of the third-order modulator can be further
suppressed by 16 dB with a 2-bit quantizer, 22 dB with a 3-bit
quantizer, and 25 dB with a 4-bit quantizer [12].

RHEE et al.: CMOS FREQUENCY SYNTHESIZER WITH

MODULATOR

1455

Fig. 5. Architecture comparison: (a) single-bit and proposed, and (b) MASH
and proposed.

Fig. 4.

Proposed modulator: (a) pole-zero plot, and (b) noise transfer function.

The NTF is derived from the high-order topology [10] as

(7)
To avoid digital multiplication, the coefficients of
are used to implement them using shift operations. This constraint slightly modifies the original NTF, but it still maintains
the causality and the stability conditions. The poles of the NTF
are designed to be within the unit circle in the -domain as
shown in Fig. 4(a). Low- Butterworth poles are used to reduce the high-frequency shaped noise energy, which results in
a low spread output bit pattern. As shown in Fig. 4(b), the NTF
of the proposed modulator has the passband gain of 3.1 and the
corner frequency of 0.18 for the clock frequency .
In Fig. 5, the proposed architecture is compared to the highorder modulator with single-bit quantizer and the MASH modulator. The high-order modulator with single-bit quantizer has a

dead-band problem due to the limited input range of the quantizer in synthesizer applications. As shown in Fig. 5(a), the extended input range with the multilevel quantizer helps to reduce
the nonideal effects at the band edges. Either a fourth-order
modulator with a modulus-4 divider or a second-order modulator with a modulus-16 divider may perform well for the purpose. The former has more noise shaping while the latter has
the same performance with a higher corner frequency. Although
the MASH topology with the same order can shape the in-band
noise more sharply, it produces an output bit pattern spread
more widely than the proposed noise shaper does, as shown in
Fig. 5(b). Widely spread output bit pattern makes the synthesizer
more sensitive to the substrate noise coupling since the modulated turn-on time of the charge pump in the locked condition
increases.
Fig. 6 shows the time-domain simulation of the division ratio
for the 1000 sequences generated by the 3-b third-order modulator. The simulation is done with the behavioral model of the
gate-level modulator in PSPICE. The fractional division ratio is
and the 16th bit is used for dithering. That
set to
.
is, the actual fractional division ratio is
Note that this interpolator uses mostly the closely-spaced divi, and
to generate the fractional
sion values of ,
value. The fast Fourier transform (FFT) of the modulator output
is shown in Fig. 7, as predicted from the NTF in Fig. 4(b).
The discrete Fourier transform does not provide the true
power spectrum particularly when the signal is aperiodic or

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 10, OCTOBER 2000

Fig. 6. 3-b third-order modulator output stream for

with dithering in time domain.

N +1=4+1=2

division

Fig. 8. Autocorrelation of 2000 samples with N

+ 1 =2 + 1 =2

division.

Fig. 9. Functional block diagram of the synthesizer.

Fig. 7. FFT of 3-b third-order modulator output for N

with dithering.

+1=4+1=2

division

random. The autocorrelation estimate is used for 2000 output

samples with the fractional division ratio of
as shown in Fig. 8. It is known that the high-order noise shaping
with multibit quantization makes dithering more efficient by
allowing a large dithered signal at the quantizer input.
III. SYNTHESIZER IMPLEMENTATION
Fig. 9 shows the functional block diagram of the proposed
fractional- frequency synthesizer. Since a third-order
modulator is used, a type-2 fourth-order PLL having two additional out-of-band poles is used to filter out the quantization
noise at high frequencies. The system is configured to be compatible with existing integer- frequency synthesizers. The
P/FD and the charge pump are designed to have four different
sets of the phase detector gain and to work with both positiveand negative-gain voltage-controlled oscillators (VCO). The
differential 8/9 prescaler is used with a dual-modulus 4/5
divider and a toggle flip-flop. The bandgap reference circuit

generates a temperature-independent output current for the

charge-pump. It also keeps the PLL bandwidth constant over
temperature. The control logic takes the 3-b output of the
modulator and provides the randomized data to the counters.
is used for
A pseudorandom sequence with a length of
LSB dithering. The fine frequency resolution of less than 0.001
ppm can make the synthesizer compensate for the crystal-frequency drift with a digital word. It can also accommodate
various crystal frequencies without reducing the phase detector
frequency.
Since the counters operate at higher than 120 MHz for the
1.1-GHz output, asynchronous counters are used to save power.
The counter block diagram is shown in Fig. 10 with the timing
diagram. In the example, the modulus data of the main and auxiliary counters are set to 8 and 3, respectively. To absorb the
logic delays in the asynchronous operation and in the differential-to-single-ended conversion, a D-flip-flop is added to each
counter and triggered by the input clock. It also prevents the
jitter from accumulating in the asynchronous counter.
The use of a tri-state charge pump is important to minimize
modulator is on the
the substrate noise coupling when the
same die. By turning it on briefly between the rising and the
falling edges of the reference, the substrate noise coupling can

RHEE et al.: CMOS FREQUENCY SYNTHESIZER WITH

MODULATOR

1457

Fig. 12.

Fig. 10. Frequency divider using asynchronous counters and timing diagram
= 8, A = 3).
example (

Die photograph.

the P/FD can be separated from the falling edge of the clock for
further reduction of the substrate noise coupling. The output
voltage compliance of the charge pump is designed to be larger
than the range of 0.52.5 V with 3-V supply over process and
temperature variations. In fractional- frequency synthesis,
the phase detector linearity is important to lower the in-band
noise and the idle tones.
IV. EXPERIMENTAL RESULTS

Fig. 11.

Programmable charge pump.

be significantly reduced [3], [5]. Fig. 11 shows the schematic

of a programmable charge pump designed to minimize the
turn-on time of the P/FD without creating a dead zone. Having
the switches, M1, M2, M19, and M20, at the source of the
current mirror improves the switching speed while keeping the
switching noise low. Current mirrors, M5M18, are cascoded
to increase output impedance and four different output currents
at each stage. The
can be generated with the control bit
capacitors, MC1 and MC2, are added to reduce the charge
coupling to the gate and to enhance the switching speed. The
control bit PD and the complementary bit PDB force the current
mirrors to be turned off during the power-down mode. Note that
the P/FD and the charge pump are triggered at the falling edge
of the clock to reduce the substrate noise coupling because the
modulator is triggered at the rising edge. The clock for the
modulator is slightly delayed so that the turn-on time of

The prototype synthesizer with second- and third-order

modulators was fabricated in 0.5- m CMOS. The die photo is
shown in Fig. 12. The chip area is 3.16 3.49 mm , including
two other MASH modulators.
Fig. 13(a) shows the measured output spectrum at 900.03
modulators.
MHz with the 3-b second- and third-order
They are compared by switching the output bits of each modulator without changing any loop parameter of the synthesizer.
The third-order modulator case shows less out-of-band noise,
as expected. With the 8-MHz phase detector frequency, a 45
dBc spur appears at about 60-kHz offset and it is suppressed
to 80 dBc with the 3-kHz loop bandwidth. However, no fractional spur was observed when the phase detector frequency
is set to 7.994 MHz. The reference spur at 7.994-MHz offset
was less than 95 dBc. From the experiment, the spur results
from the relation between the output frequency and the phase
detector frequency, and it becomes more significant when the
output frequency approaches the rational multiples of the phase
detector frequency. Even though the spurs are observed, the
overall performance exceeds that of any integer- synthesizers
reported to date. For example, when the output frequency
is programmed in a 200-kHz step with the phase detector
frequency of 6.4 MHz and the loop bandwidth of 15 kHz, the
worst-case spur at 200-kHz offset is below 85 dBc for all
channels and the in-band phase noise is as low as 90 dBc/Hz.
Fig. 13(b) shows the shaped quantization noise seen at the
divider output. The output with the second-order modulator
has idle tones at high frequencies but they can be suppressed
to a negligible level at the VCO output with a 40-kHz
loop bandwidth. The third-order modulator does not exhibit

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 10, OCTOBER 2000

(a)

Fig. 15.

Measured open-loop and closed-loop output phase noises.

TABLE I
SUMMARY OF THE MEASURED PERFORMANCE.

(b)
Fig. 13.
output.

Measured spectrum: (a) at the VCO output, and (b) at the divider

=
=

=
=

*f o 900.03 MHz, f pd 7.994 MHz, and loop BW 40 KHz

**f o 900.03 MHz, f pd 8 MHz, and loop BW 3 kHz

Fig. 14.

Measured output spectrum with 100-kHz span.

high-frequency tones near

. Note that the corner frequency
of the quantization noise is close to that of the NTF shown in
Fig. 4(b).
modulated
Fig. 14 shows the spectrum of the third-order
output with a 100-kHz span. The loop bandwidth is about 40
kHz and no close-in fractional spur is observed. Fig. 15 shows
the synthesizer output phase noise measured at 900.03 MHz.
The phase noise of a free-running external VCO is plotted together. As shown in Fig. 15, the phase noise of 92 dBc/Hz at
10-kHz offset frequency is achieved. The phase noise floor from

200800 kHz is the residual quantization noise of the modulator.

The phase noise is 135 dBc/Hz at 3-MHz offset frequency,
and it can be further suppressed either by increasing the phase
detector frequency or by pushing high-order poles toward the
loop bandwidth, sacrificing the loop phase margin. The settling
time of the synthesizer within a 50-Hz error for the 100-MHz
frequency step is less than 150- s with the natural loop frequency of 18 kHz. The chip works at 1.1 GHz with an input
sensitivity of 15 dBm. The third-order modulator consumes
1.4 mA at 1.5 V. The total current consumption of the synthesizer is 10.8 mA where 5 mA is consumed by the RF input
buffer and 1.9 mA by the prescaler. The measured performance
is summarized in Table I. Having about 3-kHz loop bandwidth,
the prototype synthesizer is useful for AMPS, IS-95, and PDC
applications. It can be also employed for multislot GSM applications with a 40-kHz loop bandwidth. Table II shows the
performance comparison with the previously published works.
Without increasing the phase detector frequency and the oversampling ratio, the noise performance of this work is comparable to that of the synthesizer with the fourth-order MASH

RHEE et al.: CMOS FREQUENCY SYNTHESIZER WITH

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TABLE II
COMPARISON WITH OTHER WORKS

modulator that used a 20-MHz reference on the separate CMOS

die [5].
V. CONCLUSION
A 1.1-GHz CMOS fractional- frequency synthesizer with a
modulator is implemented to achieve better
3-b third-order
in-band phase noise, lower spurs, and faster settling than those
of standard integer- synthesizers. With less than 1-Hz frequency resolution and agile frequency switching, the in-band
phase noise and the spur performance of the proposed system
meets the requirements of most RF applications including multislot GSM, AMPS, IS-95, and PDC.
ACKNOWLEDGMENT
The authors would like to thank D. Tester, T. Truong, and
R. Hlavac at Conexant Systems for their technical support.

[11] P. Ju, K. Suyama, P. F. Ferguson, and W. Lee, A 22-kHz multibit

switched-capacitor sigmadelta D/A converter with 92-dB dynamic
range, IEEE J. Solid-State Circuits, vol. 30, pp. 13161325, Dec. 1995.
[12] P. Ju and D. Vallancourt, Quantization noise reduction in multibit oversampling A/D convertors, Electron. Lett., vol. 28, pp. 11621163,
June 1992.

61

Woogeun Rhee (S93M97) received the B.S. degree in electronics engineering from Seoul National
University, Seoul, Korea, in 1991, and the M.S. degree in electrical engineering from the University of
California, Los Angeles, in 1993, where he was also
advanced to M.A. candidacy in mathematics. He is
currently working toward the Ph.D. degree in electrical and computer engineering at the University of
Illinois, Urbana-Champaign.
Since 1997, he has been with Conexant Systems
(formerly Rockwell Semiconductor Systems), Newport Beach, CA, where he is a Senior Staff Design Engineer in the Wireless
Communication Division. His current interests are in high-speed PLL applications and low-power RF circuits with an emphasis on frequency synthesizers.

REFERENCES
[1] G. C. Gillette, The digiphase synthesizer, Freq. Technol., pp. 2529,
Aug. 1969.
[2] J. Gibbs and R. Temple, Frequency domain yields its data to phaselocked synthesizer, Electronics, pp. 107113, Apr. 1978.
[3] B. Miller and R. Conley, A multiple modulator fractional divider, in
Proc. 44th Annu. Frequency Control Symp., May 1990, pp. 559568.
[4] T. A. Riley, M. Copeland, and T. Kwasniewski, Deltasigma modulation in fractional- frequency synthesis, IEEE J. Solid-State Circuits,
vol. 28, pp. 553559, May 1993.
[5] N. Filiol, T. Riley, C. Plett, and M. Copeland, An agile ISM band
frequency synthesizer with built-in GMSK data modulation, IEEE J.
Solid-State Circuits, vol. 33, pp. 9981008, July 1998.
[6] M. Perrott, T. Tewksbury, and C. Sodini, A 27-mW CMOS fractional- synthesizer using digital compensation for 2.5-Mb/s GFSK
modulation, IEEE J. Solid-State Circuits, vol. 32, pp. 20482060,
Dec. 1997.
[7] V. Reinhardt and I. Shahriary, Spurless fractional divider direct digital
synthesizer and method, U.S. Patent 4 815 018, Mar. 21, 1989.
[8] K. Feher et al., Telecommunications Measurements, Analysis, and
Instrumentation. Englewood Cliffs, NJ: Prentice Hall, 1987, pp.
366372.
[9] J. C. Candy and G. C. Temes, Oversampling DeltaSigma Data Converters. New York, NY: IEEE Press, 1992, pp. 129.
[10] K. Chao, S. Nadeem, W. Lee, and C. Sodini, A higher-order topology
for interpolative modulation for oversampling A/D converters, IEEE
Trans. Circuits Syst., vol. 37, pp. 309318, Mar. 1990.

Bang-Sup
Song
(S79M83SM88F99)
received the B.S. degree from Seoul National
University, Seoul, Korea, in 1973, the M.S. degree
from the Korea Advanced Institute of Science,
Taejon, Korea, in 1975, and the Ph.D. degree from
the University of California, Berkeley, in 1983.
From 1975 to 1978, he was a Research Staff
Member with the Agency for Defence Development, Korea, working on fire-control radars and
spread-spectrum communications. From 1983 to
1986, he was a Member of Technical Staff at AT&T
Bell Laboratories, Murray Hill, NJ, and was also an Adjunct Professor in the
Department of Electrical Engineering, Rutgers University, Piscataway, NJ.
From 1986 to 1999, he was a Professor in the Department of Electrical and
Computer Engineering, University of Illinois, Urbana. He currently holds
the Powell Endowed Chair in Wireless Communication in the Department of
Electrical and Computer Engineering, University of California, San Diego.
Dr. Song received a Distinguished Technical Staff Award from AT&T Bell
Laboratories in 1986, a Career Development Professor Award from Analog Devices in 1987, and a Xerox Senior Faculty Research Award in 1995. His IEEE
activities have been in the capacities of Associate Editor and Guest Editor of
the IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS and the IEEE JOURNAL
OF SOLID-STATE CIRCUITS, and a Program Committee Member for the IEEE
International Solid-State Circuits Conference and the IEEE Symposium on Circuits And Systems.

1460

Akbar Ali received the B.S. degree in electrical engineering from the University of Engineering and Technology, Lahore, Pakistan, in 1984, and the M.S. degree in electrical engineering from Oregon State University, Corvallis, OR, in 1986.
He is currently employed with Conexant Systems, Inc., Newport Beach, CA, as a Director of
Engineering in RFIC Design. Formerly, he was
with Rockwell International, Newport Beach, CA,
Nokia Corporation, San Diego, CA, and National
Semiconductor Corporation, Santa Clara, CA. His
primary interest is in communications and control circuits and systems with
current focus on RF frequency synthesizers and VCOs. He holds a patent and
various prestigious awards from Conexant Systems, Rockwell International,
and National Semiconductor.

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 35, NO. 10, OCTOBER 2000