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OVERSAMPLING DELTA-SIGMA ADC FOR METROLOGY APPLICATIONS

D. Georgakopoulos2, J.R. Pickering', J.M. Williams2 and P.S. Wright2
1 Metron Designs The Old Rectory, Alderford, Norwich NR9 5NF, UK
2National Physical Laboratory, Teddington, Middlesex TW 11 OLW, UK
Abstract

A-1; ADC performance and limitations

The performance of a A-; ADC is limited by both the
analogue and the digital circuits of the system. The
biggest source of error is the noise introduced by the
feedback DAC, because this noise is only affected by the
oversampling and not the A-2 modulation. The noise of
the quantiser in the forward path and the integrators

This paper focuses on the performance of the A-2 ADC

for metrology applications and presents a quantum based
A-X: ADC under development by Metron Designs and the
National Physical Laboratory which is suitable for DC
and low frequency spectrum analysis, voltage and power
measurements.

reduce further the accuracy of the converter, although are

modified by the A-E modulation. The aperture jitter and
stability of the switching mechanism (i.e. the uncertainty
in time that the switching action occurs) also reduces the
accuracy of the converter. To achieve high signal-toquantisation noise ratio (SQNR), the digital filters are
required to have sharp transition band, hence, higher order
filters must be employed. However, higher order filters
decrease the overall analogue-to-digital conversion rate
and, when the number of bits of the registers used in the
calculation is relatively small, numerical effor can enter
the calculation. The jitter of the clock used to
downsample the signal after digital filtering introduces
error in the decimation process. The effect of the clock
jitter on the accuracy of the A-X ADC can be reduced by
using a synchronous system. The phase shift introduced
by the A-E modulation and the digital filters affect the
phase shift of the input signal. Change in the phase shift
of the input signal can be a disadvantage when the phase
shift of the input signal is of interest, such as in power

Introduction

The oversampling delta-sigma analogue to digital

converters (A-E ADC) can be of high resolution (up to 24
bits). Compared with other high accuracy ADC
techniques, the A-E ADC requires fewer high precision,
low drift analogue electronic components and a low order
anti-aliasing filter at its input, at the expense of an
increased digital computational load [1].
The analogue part of the A- ADC consists of an
integrator(s), a quantiser and a digital-to-analogue
converter (DAC) (figure 1). The biggest error sources of
the A-E ADC are the noise, stability and linearity of the
reference voltage of the feedback DAC. By using the
Josephson effect Voltage Standard (JVS), stable
references with accuracy better than 1 part in 108 can
easily be obtained (see for example [2]). Therefore, a A-2
ADC employing a JVS as its DAC, can be of high
accuracy (sub-parts per million, ppm). This accuracy level
is needed to address the current challenges in metrology
and scientific research involving spectrum analysis,
voltage and power measurements.
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measurement.

Most of these limitations can be overcome by increasing

the number of the integrators and/or the oversampling
ratio. Nevertheless the design of higher order integrators
is difficult, they are more prone to oscillations. In
practical converters, the number of integrators is limited
to seven. From simulation it was found that there is little
or no practical advantage of using more than four

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integrators in metrology applications.

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Fig. 1 Oversampling A-X ADC

Ouantum based A-Y. ADC

The uncertainty in the value the DAC and switching
process (which can be of the form of noise, linearity
and/or thermal and time drift) is the biggest error source

0-7803-8493-8/04/$20.00 2004 British Crown Copyright

656

in the system. While the spectrum of this noise is

unaffected by the noise transfer function the oversampling
can reduce the RMS value of this noise by a factor up to
k"2, where k is the oversampling ratio. However, this
noise reduction method is not practical (in terms of the
computational load required) for measuring voltage with
accuracy of 1 part in 108. A JVS generates voltage levels
with accuracy of 1 part in 108 and fast operation of the
SLNIS type of arrays is now possible which effectively
allows their use as DACs.

oversampling ratio 128, four integrators, 10 bits for the

quantiser in the forward path and 4 bits for the DAC. The
results show that a physically realisable A-1 ADC with
these characteristics can achieve a resolution
corresponding to an effective number of bits (ENOB) 22.
The system can settle to this resolution within 400 clock
counts. The linearity of the quantum based A-; ADC can
be better than 1 part in 107. From the simulated results it
was found that the quantisation noise can be considered as
random, which is in agreement with the discussion of
Candy [4]. These results are correlated with the results
obtained from PSPICE simulations.

A pulse width modulated (PWM) waveform is applied to

the JVS bias source eliminating the need of a separate
modulation switch (as in the case of a PWM DAC), thus
the errors due to switching of the feedback voltage are
reduced. Therefore, when a JVS is used as the reference
voltage of the A-l ADC, the accuracy of the voltmeter
based on such a converter will be high (sub-ppm) [3] and
is limited mainly by the noise of the analogue circuits of
the converter and the precision of the switching.

Future work

In the future this A-2 ADC will be used in the

instrumentation of the National Physical Laboratory for a
number of applications including precision AC
measurement, AC/DC transfer, harmonic analysis and
power measurements. Research activities will include the
replacement of analogue circuitry with digital, improving
the conversion rate and the DAC linearity, which are
expected to be the main performance limiter.

System description and evaluation

Metron Designs and the National Physical Laboratory are
developing a quantum-based A-E ADC aiming at sub-ppm
accuracy suitable for: (a) sub-ppm DC and low frequency
measurements, (b) spectrum analysis and (c) power
measurements. The system employs a fourth order
modulator, a 10-bit quantiser and a 4-bit DAC. The DAC
is selectable as either a JVS or a 16-count PWM DAC.
The PWM DAC was chosen because of its linearity
(better than 1 part in 107 of the full-scale) and was
designed to ensure that the imperfection of the modulation
switches contribute only to an offset error. The resolution
of the PWM DAC is limited to 4-bits because of the high
clock rates required for higher resolution. Because of the
limited PWM resolution, only the five most significant
bits of the quantiser are used for the DAC. The reduced
resolution of the DAC is forced to track the higher
resolution quantiser in the forward path over a number of
cycles by using an interpolator. The decimation consists
of a number of moving average filters and the
downsampling proceeds in two stages. Optional filtering
of 50/60/400 Hz interference is provided. To eliminate the
effect of the clock jitter during downsampling, a
synchronous system is used. The interpolation,
decimation and the PWM stages are implemented on an
FPGA. The data from the converter can be transmitted to
a PC (using a USB interface) for further processing.

Acknowledeements
This work was supported within the UK DTI National
Measurement System Policy Unit's Program for Electrical

Metrology.

References:
[1] Candy J.C. and Temes G.C. (editors), Oversampling
Delta-Sigma Data Converters, NJ, IEEE Press, 1992.

[2] Kohlmann J., Berh R. and Funck T., Josephson

voltage standards, Meas. Sci. Technol., v.14,
pp.1216-1228, 2003.
[3] Pickering J.R., Developing the Sigma-Delta A-D for
precision DC&LF metrology, in 4th ADDA, Prague,
Czech Republic, pp. 27-30, 2002.

[4] Candy J.C., A use of double integration in sigma

delta modulation IEEE Trans. Commun., Vol COM33, pp. 249-258 1985.

To demonstrate the resolution that can be achieved by the

converter under development a number of simulations
(based on difference equations) were conducted using an

657