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560 mV for VBE produces the best practical relationship between IL and IP.
Inverting the transistorthat is, swapping Q1s collector and emitter connections produces a more abrupt conduction-threshold voltage of approximately
500 mV but decreases the slope of IP versus IL. In this example, inverting the transistor requires lowering the value of R2
to approximately 7.5 k.
The inverted-transistor circuit provides
a sharper threshold and thus more realistic simulation, even though it may require some experimentation with resistor
values for optimal performance. You can
use almost any PNP bipolar-junction
transistor for Q1, such as a ZTX502, and
decreasing R2 by 30% renders IP within
5% of the desired nominal value of IP.
Note that laser diodes characteristics
vary widely, even within a batch, so using preferred-value resistors for R1 and R2
makes little practical difference in performance. Laser diodes exhibit a typical
forward-voltage drop of about 2V, and
the simulator circuit should thus drop no
more voltage at full current. Also, the
simulator circuit responds more slowly
than a laser diode, but, if the feedback circuitry operates even more slowly, as it
usually does, the simulators slow response presents no problem.
A simulator for an N-type laser diode
requires an NPN transistor and reversal
of connections. More complex laser
diodes may require more elaborate circuitry that includes current mirrors and
additional connections. If adequate power-supply voltage is available for currentsource compliance, you can connect an
LED in series with the IL lead to provide
a visual indication of circuit operation.
Connecting an oscilloscope across R1 allows monitoring laser-drive and modulation currents. (In this context,N- and
P-type refer not to laser-diode-device
diffusions but to the polarity of the common terminal.)
January 6, 2005 | edn 63
design
ideas
Figure 2
Figure 3
design
ideas
R3
2k
5V
C1
2.2 F
RS
50
R1
1k
3
8 +
5
IC1
2
AD8137
1 _
4
6
C4
C2
0.1 F
2.2 F
(2)
PULSE
GENERATOR
(3)
RT
50
C5
22 pF
C3
0.1 F
VO
R5
280
VD
TO PIN
DIODES
R6
280
VD
VO
C6
22 pF
5V
R2
1.02k
R4
2k
VREF
1.75V
CURVES A AND C
RESISTANCE
B
LINEAR-RESOLUTION CURVE
C
PSUEDOLOGARITHMIC
RESPONSE
D
PSUEDOLOGARITHMIC
RESOLUTION
A
RUST
TEMPERATURE
Figure 1
These resistance-versus-temperature curves highlight the improved resolution available in a pseudologarithmic circuit.
2
sistance range crowds
0.1 F
into a small span
Figure 2
of temperatures at
R1
R2
24.9k
the lower limit of the
100k
1%
VREF
1%
range. As Curve B in Fig2.5V
ure 1 shows, the change
R4
of resistance per degree
24.9k
IC1
1%
of temperature change
+
looks exaggerated at low
THERMISTOR
temperatures. As temperR3
ature increases, the resoC1
33.2k
0.1 F
lution diminishes and
1%
may become inadequate
at the upper end of the
temperature scale.
In contrast, the signal- This pseudologarithmic thermistor signal conditioner uses a sinconditioning circuit in gle operational amplifier and a few passive components.
Figure 2 mitigates the
thermistors inherent nonlinearity by selection of this value optimizes resolugenerating a compensating, pseudologa- tion in the middle of the measurement
rithmic response function thats Curve C range, the thermistors nominal resistin Figure 1 represents. The following ance is relatively noncritical. You can also
equation relates the circuits 10V out- select a different value of reference voltput span for an ADC 10V input span to age, VREF, to shift the 10V output span
thermistor resistance: Thermistor resist- to meet other requirements. For best performance, you can share the same referanceR4(VO10)/(102VO).
Curve D in Figure 1 shows the result- ence source for VREF and for the measant resolution curve. Maximum resolu- urement systems ADC, which makes
tion occurs at a temperature that corre- measurements ratiometric and thus insponds to a thermistor resistance equal to sensitive to reference-voltage drift.
In addition to resolution, span, and
R4 and an output voltage of 0V. Although
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reference-drift considerations, thermistorsand, for that matter, all temperature sensorsexperience self-heating effects. The excitation current produces
ohmic power that causes these effects.
The limited thermal mass of miniature
thermistors provides limited heat dissipationoften only a few microwatts per
the smallest thermistors, this level of selfheating produces acceptably low fractional-degree errors.
Reference
1. Woodward, Steve,Optimize linearsensor resolution, EDN, March 7, 2002,
pg 131.
drift operational amplifier, connects directly across the bridge. (Note that the value of the remaining resistors in the bridge
depends on the application.)
To yield a ratiometric conversion, the
voltage applied to the bridge, VCOMP,
varies with power-supply voltage and
equals the difference between the two
threshold voltages of a Schmitt-trigger
circuit. In Figure 1, the Schmitt trigger
comprises a Maxim MAX9075 comparator, IC2; a CMOS inverter, IC3A; and the
positive feedback network comprising R1,
R2, and C1. Equations 1 and 2 define the
Schmitt triggers high, VTH, and low, VTL,
threshold voltages:
(1)
(2)
VCOMP
L
180 nH
C6
SPIRAL
ANTENNA
6.8 nF
R1
100k
VDD
_
+
RX
VOI
R3
330
IC1
IC2
IC3A
VCOMP
RT
C1
15 pF
IC3B
C2
100 pF
VINV
R4
PPM
OUT
VPPM
C5
_
1 nF
IC3C
C3
18 pF
VDD
4V
C4
18 pF
R2
VINV
Figure 1
Thise RF-telemetry transmitter and strain-gauge amplifier use only three ICs.
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VBATTERY
VINT
VIN
VOUT
IC4
LT1790
GND
VINT
LCOM
VOLTAGE
REGULATOR
D6
VCC
PROGRAMMING
RESISTORS
LED DISPLAY
ON
VOLTAGE SENSE
CURRENT SENSE
LCOM
IC5
LTC1477
VBATTERY
DISP
IC1
SB BQ2010
SR
EMPTY
ON/OFF
CURRENT SENSE
R4
0.1
GND
GAS-GAUGE
IC
Figure 1
HIGH-SIDE
SWITCH
VBATTERY
VLOAD
EMPTY
VLOAD
R6
VBATTERY
VOLTAGE SENSE
RESISTOR
NETWORK
TO LOAD
J1
BATTERY
EMPTY
LCOM
VBATTERY
VLOAD
CURRENT
COMP
+ IC
3B
R7
S2
S1
ON LOGIC
OFF
VLOAD
ON
TLC2262
TIMER
R36
CURRENT SENSE
CURRENT
COMPENSATION
This circuit improves the BQ2010s current-spike immunity in several ways and adds several useful features.
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design
ideas
VLOAD
R33
24.9k
TIMER
VBATTERY
OUTPUT
CONNECTOR
VLOAD
VBATTERY
R25
499k
J1
C5
0.1 F
VLOAD
2
1
C6
0.1 F
+
_
3
14
VCC COM RC
ASTABLE
12 RETRIGGER
TIMEOUT
VLOAD
CLOCK
OUT 10
IC7
CD4047B
R34
100k
OUT 11
OSC 13
9 RESET
OFF
VLOAD
CURRENT
SENSE
CD4002B
CURRENT
COMPENSATION
4 CURRENT
SENSE
R23
R24
100k
71.5k
CURRENT
SENSE
LOGIC
14
9
10
11
12
13
IC2B
VBAT
VBATTERY
D6
20CJQ030
SWITCH
VSS
VLOAD
1
S2
VLOAD
16
16
VDD Q1
Q2
Q3
10 INPUT Q4
Q5
IC9 Q6
Q7
Q8
11 RESET
Q9
Q10
Q11
VSS Q12
EMPTY
9
7
6
5
3
2
4
13
12
14
15
1
8 CD4040B
3
2
ON
R35
100k
VLOAD
VLOAD
VDD Q1 9
Q2 7
Q3 6
10 INPUT Q4 5
CLOCK
Q5 3
IC8 Q6 2
Q7 4
Q8 13
11
RESET Q9 12
Q10 14
Q11 15
R32
VSS Q12 1
100k
8 CD4040B
IC3B
R20
10.5k
1
2
EXT C EXT R
ASTABLE
6 TRIGGER
8 + TRIGGER
TLC2262
6 _
CON2
CURRENT
COMPENSATION
8
5
C7
0.047 F
VLOAD
3
4
5
2
14
IC2A
7
VOUT1
VINS
VOUT2
7 VIN2
IC5
LTC1477
ON
VLOAD
D7
BAV74
VIN1
3
6
1
8
VIN3 EN GND
C2
10 F
+ C3
10 F
CD4002B
ON/OFF
R30
100k
Figure 2
You can customize this circuit for a batterys chemistry, capacity, internal resistance, cell count, and timer and display
options.
design
ideas
ersatile switched-capacitor
charge-pump voltage converters
8
5
VOUT
VIN
OUT
IN
can provide a negative supply volt4 TO 5.5V
4 TO 5.5V
6
C2
age from a positive-voltage source or
C3
LV
1 F
1 F
double a positive sources voltage. How1
IC1
FSEL
ever, certain applications that consist enMAX1681
7
tirely of ECL (emitter-coupled-logic)
SHDN
circuits provide only a negative-voltage
2
CAP+
supplyfor example, 5.2V. Figure 1
3
C1
GND
shows how you can use a switched1 F
F
i
g
u
r
e
1
capacitor converter to obtain a posCAP
4
itive power-supply voltage suitable for
powering ECL-to-TTL (transistor-totransistor-logic)-level translators and
The backwards switched-capacitor converter converts 5V to 5V.
other circuits.
Although connections to IC1 may ap5.2
pear to be reversed, the bilateral characVIN=5V
teristics of IC1s internal switches allow
5
use of IC1s output pin as its power in4.8
put. Capacitor C1 acquires a charge
when IC1s internal switches connect the
OUTPUT 4.6
VOLTAGE
CAP pin to ground and CAP to the
(V)
4.4
negative-voltage power source via the
output pin, OUT. During the next half4.2
cycle, IC1 connects CAP to
F
i
g
u
r
e
2
ground and CAP to IN
4
(normally used as the input), transfer3.8
ring C1s positive charge to output ca0
20
40
60
80
100
120
140
pacitor C3 and the load. With FSEL connected to OUT, an internal oscillator sets This load-voltage-versus-current graph shows the effects of the converters nonzero output impedthe charge-discharge cycles frequency to ance on output regulation.
approximately 1 MHz.
As Figure 2 shows, IC1s switches pres- lower than the input voltage and subject performance, use low-ESR capacitors
ent internal resistances that affect the to less-than-ideal regulation as output- for C1, and input and output bypass caoutput voltages magnitude, which is load current increases. For optimum pacitors C2 and C3.
tion zone in the small-signal regime using an infinite input impedance and a
current source that the gate-source voltage controls. The following equation determines the small-signal transconductance of the transistor:
design
ideas
VDD
VDD
VDD
Figure 1
Figure 2
Figure 3
Q1
Q1
Q1
C1
L3
VIN (t)
C2
VOUT (t)
RG
RS
L1
VOUT (t)
RS
VOUT (t)
C3
L2
RS
Gate resistance RG provides the necessary connection from the gate to ground.
Its typical value is in the low-megaohm
range to provide the needed high impedVOUT
ance of the amplifier structure. Resis(V)
tance RS biases the transistor; the
following equation determines reFigure 4
sistance:
The necessary condition on the capacitors so that the circuit can oscillate is:
TIME
(nSEC)
With C1 having a value of 50 nF and C2 having a value of 114 nF, the circuit oscillates.
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PIN 4, 6,
19, OR 20
RED WIRE
5V
C2
0.1 F
C1 +
100 F
R1
22.1k
1%
4
D1
1N4148
C3 +
100 F
Figure 1
PIN 3, 5, 7,
13, 15, 16, OR 17
BLACK WIRE
COM
R2
22.1k
1%
6
2
8
VCC
RST
DIS
PB1
PB2
IC2
HSR312L
IC1
TLC555CP
6
OUT
THRES
MB1
TO MOTHERBOARD
POWER PUSHBUTTON
SWITCH
5
2
TRIG
GND
CON
6
C4
0.1 F
FROM CHASSIS
POWER PUSHBUTTON
SWITCH
MB2
R3
820
An inexpensive CMOS 555 timer generates power-on-switch closures upon restoration of ac power.
nlike legacy PC motherboards, an TLC555 CP IC1 functions as an astable er-on signal. Depending on the motherATX-style motherboard controls its oscillator and delivers pulses at approxi- boards design, an immediate start-up
power supplys on/off state. If ac mately 4-sec intervals to MOSFET-out- signal may cause the motherboard to lock
power fails, many ATX motherboards do put optoisolator IC2. The output of IC2 up. Connecting C3 as shown eliminates
not automatically restart when power re- connects in parallel with the PCs front- the initial start-up pulse.
When the power supply switches on,
turns, and that behavior is unacceptable panel power-on switch and in effect
primary 5V power becomes available at
for a server system that must provide pushes the power switch every 4 sec.
In most astable-oscillator designs pins 4, 6, 19, and 20, driving diode D1
near-continuous service. Although some
PCs provide BIOS configuration selec- based on the generic 555 timer, timing into conduction and biasing Pin 7 of IC1
tions for wake-on-LAN or wake-on- capacitor C3 connects from pins 2 and 6 to a level that stops oscillation. Although
modem operation, these options depend to ground. Upon initial application of IC1s output (Pin 3) can directly drive a
on another computer to provide the power, IC1s output goes low, activating motherboards power-on input, MOSwake-up call. A few ATX motherboard IC2 and generating an immediate pow- FET-output optoisolator IC2 removes the
need to trace the polarity of the
chip sets offer an always-on
power-on switchs connections. In
BIOS option, but chances are, the
11
ORANGE
3.3V
ORANGE 1
3.3V
12
BLUE
12V
ORANGE 2
3.3V
addition, IC2 eliminates any posmotherboard thats available for
3
13
BLACK
COM
BLACK
COM
sibility
of incompatible logic levyour server system isnt one of
4
14
GREEN
/PS_ON
RED
5V
els that some 3.3V motherboards
these.
5
15
BLACK
COM
BLACK
COM
6
16
impose.
The circuit design in Figure 1
BLACK
COM
RED
5V
7
17
BLACK
COM
BLACK
COM
You can assemble the start-up
offers a reliable method of recov8
18
WHITE
5V
PWR_OK GRAY
circuit
on a small section of protoery from a power interruption.
19
RED
5V
PURPLE 9
5VSB
typing board and splice its conUpon restoration of ac power, an
20
12V
RED
5V
YELLOW 10
nections into the power supplys
ATX power supply delivers a
NOTES: 5VSB = 10 mA MAXIMUM.
wiring harness and power-on
standby voltage of 5V dc at a
SHORT /PS_ON TO COM TO TURN ON.
pushbutton wiring. Variants of
maximum of 10 mA via Pin 9 of
ATX connectors exist, so verify
its power connector (Figure
This view of an ATX power supplys connecFigure 2
wiring before connecting the start2). With standby power availtor shows color codes. Pinouts may differ
up circuit.
able, low-power CMOS timer slightly from manufacturer to manufacturer.
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JITTER/WANDER[UI p-p]
DPM/180, (3)
where DPM has units of radians in communications theory, but, for convenience,
most signal generators specify units of
degrees instead.
For FM, the phase (t) in Equation 1 is
proportional to the integral of modulating
signal.
and it is:
for FM.
IC1, serves multiple functions as a temperature sensor, quad-setpoint, programmable analog temperature monitor
and controller. Resistors R1, R2, R3, R4, and
R5 adjust desired temperature at setpoints
SETP1, SETP2, SETP3, and SETP4,
which IC1 compares with the actual temperature from its internal sensor. The
5V
VCC
11
14
VREF
HYST
VCC
HEATER
13
R1
10.2k
15
SETP4
OUT4
10
SETP3
OUT3
16
4 PTA3
5 PTA2
R6
475
1
1
VCC
IC4
R1
221
R2
475
IC1
ADT14
SENSOR
R3
475
7
SETP2
PTA3
IC2
68HC908QT
OUT2
6 PTA1
1 IC
3A
74LS06
PTA3
ZEROCROSS
CIRCUIT
TIC263M
MOC3043
AC
POWER
R4
475
2
SETP1
OUT1
R5
20k
7 PTA0
AC
POWER
GND
8
Figure 1
Q1
GND
VPT
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design
ideas
ing 1 contains commented assembly-language software. When you load it into the
microcontrollers flash memory, the software provides the time-proportional
control algorithm. When IC1s OUT1,
OUT2, OUT3, and OUT4 outputs are inactive, IC2 switches its output PTA4 to a
totally on-state, 100% duty cycle for maximum heating. Listing 2 at the Web version of this Design Idea contains an assembled version of the software, and
Listing 3 presents the hex code for programming IC2.
When IC1s OUT1 output is active, IC2
produces a 75%-duty-cycle output on
PTA4. In similar fashion, when IC1s
OUT2 output goes active, IC2 produces
a 50%-duty-cycle output on PTA4,, and
when IC1s OUT3 output goes active, IC2
produces a 25%-duty-cycle output on
PTA2
1
1
1
0
0
PTA1
1
1
0
0
0
On (%)
100
75
50
25
0
PTA4. When IC1s OUT4 output goes active, IC1 disables the output on PTA4 to
produce a totally off state (0% duty cycle). Table 1 summarizes the relationship
of IC2s inputs and output duty cycle.
To minimize component count, IC2s
internal oscillator generates a 12.8-MHz
clock that divides to produce a sample
pulse whose basic width is 0.1 sec for each
1% of output on-time. One cycle of output comprises 100 samples for a total duration of 10 sec. Thus, for a 25% duty cy-
Off (%)
0
25
50
75
100
On (sec)
10
7.5
5
2.5
100
Off (sec)
0
2.5
5
7.5
10
design
ideas
TOTAL
NOISE
NOISE
GND
original ratio of noise voltage to dc refC1
C2
C3
erence voltage thus divides in half.
100 F
0.1 F
0.1 F
12V
12V
Figure 1 illustrates a method of adding
IC2
multiple references to produce a single,
2.5V
IN
REFERENCE
IC OUT
less noisy reference voltage. The resistors
GND
are parts of a highly stable metal-film
C4
network, and buffer amplifier IC5 offers
0.1 F
R1
low noise, low input-offset voltage, and
4.99k
IC3
low offset-temperature coefficients.
2.5V
IN REFERENCE IC OUT
Tables 1 and 2 present the noise voltGND
ages that result from stacking four each
C5
0.1 F
of two types of 2.5V references. Each
IC5
table shows the 0.1- to 10-Hz noise voltMAX4236A
IC4
age for each of the four references,
2.5V
2.5V
Figure 1
IN REFERENCE IC OUT
IC1 through IC4, and for the comREDUCEDR2
NOISE
4.99k
bination. Note that the dispersion in the
GND
REFERENCE
C
OUTPUT
6
ratios of rms to peak-to-peak values re0.1 F
lates to subjectivity in the method of
measuring the values. In addition to lower 0.1- to 10-Hz noise, the circuit also re- Four 2.5V references, IC1 through IC4, produce 10V. Resistors R1 and R2 form a voltage divider that
duces long-term drift of the reference reduces the 10V output to 2.5V and lowers the output-noise voltage by half. Buffer amplifier IC5
isolates the reference circuit from the load.
voltage.
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design
ideas
12V
IC1
4010
C1
0.1 F
R1
6.8k
14
1
IC1A
40106
2
C2
1 nF
11
10
IC1
401
13
12
IC1
4010
C3
0.1 F
R2
10k
DRIVE LEVEL/SENSITIVITY
IC1C
40106
5
12V
Figure 1
R3
100k
R6
10k
R4
10k
TOUCH
PAD
Q1
2N5457
TOUCH
IC1B
40106
D1
1N4148
R7
1M
TOUCH
C4
1 nF
R5
10M
A low-cost touch-switch interface uses three Schmitt trigger hex inverters and a single JFET per channel.
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C4
68 F
C2
0.1 F
2
L1
47 H
V+
5
D1
1N5817
REF
C3
0.1 F
Q1
IRF530
4 SHDN
C1
0.1 F
CS
AGND
5V
1 INC
S2
R2
10k
2
5V
R6
10k
U/D
IC1
MAX5160
CS
FB
3 H
L 6
W 5
GND
R7
0.1
VDD 8
3
R3
33k
GND
7
R4
4.7k
A digital potentiometer, IC1, and two pushbutton switches, S1 and S2, let you adjust the regulated output voltage of boost converter IC2 over a 10V range.
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VOUT
5 TO
16V
MAX1771
VIN
5V
S1
C6
200 F
IC2
VIN
5V
R1
100k
EXT
R5
10k
Figure 1
design
ideas
Connecting IC1s wiper via 10-k resistor R5 to IC2s FB (feedback) node sets
IC2s voltage-feedback level. Although
inclusion of feedback resistors R3, R4,
and R5 and digital potentiometer IC1
complicates the precise calculation of
IC2s output voltage, you can simplify the
math by calculating the output voltages
or VMAX16.84V.
With IC1s wiper set to 5V, you can attempt to calculate the minimum output
voltage by summing voltages into the
feedback node:
(3)
R1
C1
and holds off Q1, a state that
easier to implement alternaV
10 F
1.3
it maintains indefinitely until
tive. If a product includes a mi
8
you cycle the circuits power
crocontroller, only two spare
off and then on.
pins are necessary for motor
The control program, in asprotection.
sembly language for the MCFigure 1 shows a dedicated NOTE: D , A LITE-ON LTL-4223-R2, INCLUDES A BUILT-IN RESISTOR.
1
68HC908, features a straightprotection circuit based on a
forward algorithm adaptable
small microcontroller and a Controller for dc brushless fan motor features minimal parts count.
to other microcontrollers that
power FET. This project uses an
eight-pin flash-memory MC68HC- that in turn controls the motor. Current include an A/D converter. A 2.5-sec de908QT2 from Freescale and an IRF520A through the motor develops a voltage, V, lay routine prevents the motor from
FET from Fairchild to control a dc brush- thats proportional to the motor current starting until the systems power-supply
less-fan motor rated for 0.72A at 12V dc. across sense resistor R1. A lowpass filter voltage stabilizes. You can download the
A high or low output voltage on output comprising R2 and C1 reduces noise on listing from the online version of this
PA5 of IC1 controls Q1, an N-channel FET the sense voltage you apply to input PA4 Design Idea at www.edn.com.
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design
ideas
CURRENT FLOW
CURRENT FLOW
(a)
S1
S2
S1
S2
Figure 2
S1
S2
(b)
Conventional solder
pads offer two choices
for Kelvin connections: on the pads inner
edges (a) or outer corners (b).
Figure 1
design
ideas
and adds approximately 10W to the power budget. To reduce wasted power, it uses
an active pulldown circuit (inside the
dashed line in Figure 2). As long as switch
S1 remains closed, PNP transistor Q1s
base voltage exceeds its emitter voltage
due to diode D1s forward voltage drop.
Thus, Q1 doesnt conduct, and the control circuits input voltage rests at
VCC0.7V (D1s forward voltage drop).
Opening S1 reverse-biases D1, and the
base current flowing through resistor R1
turns on Q1, which saturates and pulls the
VCC
R1
10k
S1
I
VCC
Q1
D1
S1
I
D2
R1
500
R2
2.2k
ENABLE
D2
R2
2.2k
D1
ENABLE
Q1
R1
10k
S2
VDD
Figure 2
Figure 1
A conventional network
requires a low-value pulldown resistor.
Figure 3
log or a digital signal to drive the switching device. The circuit also requires only
a few components: a diode, a switching
transistor or a MOSFET, an inductor or
a transformer, and a capacitor. Further,
the designs circuit losses are low, and the
switching device experiences minimal
stress during operation. Figure 1 shows
the basic circuit, and Figure 2 illustrates
(continued on pg 86)
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design
ideas
VOLTAGE
ACROSS
CAPACITOR
VCC
GROUND
DRAIN
CURRENT
GATE
DRIVE
TRANSISTOR
OFF INTERVAL
Figure 2
The circuit in Figure 1 produces these waveforms.
TRANSISTOR Q
CONDUCTION
INTERVAL
design
ideas
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R1
VBR(t)
IC1
R2
R5A
R5B
X
C3
VIN(t)
IC2
R4
Z
IC3
C1
R3
VOUT(t)
C2
R5C
R5D
(1)
This bandpass active filter features adjustable Q and maximum gain in the
passband and consists of a twin-T cell with Q adjustment and a differential
output stage. You can also extract a frequency-notch output from the voltage-follower stage.
Figure 1
where K represents the filters gain constant.When the input frequency equals O,
the filters gain,AMAX, is proportional to the
product, KQ. Thus, modifying the quality
factor alters the gain and vice versa.
This Design Idea describes a filter
structure in which K is inversely proportional to Q. Altering Q also modifies K,
producing a magnitude-plot set in which
the curves maintain the same maximum
gain at the central frequency 0that is,
KQ remains constant. Figure 1 shows the
filter, which comprises a twin T cell with
an adjustable quality factor and a differential stage. The differential stage comprises op amp IC3 and resistors R5A
through R5D. This stage outputs the difference between the filters input signal
and the twin-T networks output. Capacitors C1 and C2 are of equal value,
CC1C2, capacitor C3 equals 2C, resistors R1 and R2 are also equal and of value RR1R2, and R3 equals R/2. Equation 2 describes the twin-T circuits
transfer-function response as a notch filter producing output VBR(t):
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(4)
(2)
(3)
design
ideas
0
PHASE
MARGIN
()
40
(6)
80
VdB (VNOTCH)
100
(7)
GAIN
(dB)
0
100
100 Hz
Figure 2
300 Hz
1 kHz
FREQUENCY
3 kHz
10 kHz
10
PHASE
MARGIN
()
20
30
VdB (VNOTCH)
100
GAIN
(dB)
100
100 Hz
Figure 3
300 Hz
1 kHz
FREQUENCY
3 kHz
10 kHz
Magnitude and phase Bode plots at the bandpass output, VOUT(t), show
effects of varying twin-T-cell feedback factor, m, from 0.1 to 0.9.
minal for its internal circuitry. In operation, IC1s output current, IOUT, equals
VSENSE/100V, where VSENSE is the voltage
across RSENSE1.
This Design Idea uses IC1 rather than
the many current-sense amplifiers available because it provides a separate supply-voltage terminal for the internal circuitry, whereas other devices take power
from the current you are measuring. In
this application, a full-scale current of 1A
develops 1V across RSENSE1, which IC1
converts to a maximum output current
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design
ideas
RSENSE1
of 10 mA that produces a maximum
OPERATINGMEASURED
1
SUPPLY
voltage of 1V across R1. Operational amCURRENT
RANGE
1
2
0 TO 100 mA
plifier IC2 and transistor Q1 form a volt0 TO 32V
RS+
RS
age-controlled current sink that draws
5V INSTRUMENT SUPPLY
8
V+
current through meter M1. A full-scale
reading of 15 mA develops 1V across
IC1
M1
MAX4172
66 resistor RSENSE2. You can adjust the
METER
FULL-SCALE
FULL-SCALE
resistors value to calibrate the meter or
=1V
6
15 mA
OUT
to alter the full-scale current range.
7
3
This circuit also allows separation of
+
R1
Q1
IC2
6
1k
BC182
the measurement point and meter locaMAX495
5
2 _
tion. Moving-coil meters are not intend4
GND
ed for applications that require precision
measurement, and you can use relaxedaccuracy passive components.
RSENSE2
Figure 1
66
Bypass the instrument-supply
voltage with decoupling capacitors that
the electrical-noise environment re- This circuit displays current on a moving-coil meter that consumes a substantial fraction of the current you are measuring.
quires.
MOSFET enhances
voltage regulators overcurrent protection
Herb Hulseman, Eagle Test Systems, Mundelein, IL
Resistors R5 and R6 set IC1s output Diodes D1 and D2, respectively, protect
he classic LM317 adjustable-output
linear voltage regulator offers a rela- voltage, as the LM317s application notes against capacitive-load discharge and potively high, if package-dependent, describe. By varying the value of R1, you larity reversal. Depending on the circuits
current-handling capability. In addition, can adjust the circuits limiting current requirements, IC1 and Q1 may require
the LM317 features current limiting and from milliamperes to the LM317s heat dissipators.
thermal-overload protection. With the maximum current-handling capability.
addition of a few components, you can
enhance an LM317-based voltage reguD1
lator by adding a high-speed
1N4002
Figure 1
short-circuit current limiter
(Figure 1). Under normal operation, reQ1
sistors R2 and R3 apply VGS bias to power
IC1
IRF4905S
R1
,
an
IRF4905S,
which
fully
MOSFET Q1
LM317
18VOUT
24VIN
1
3
2
S
D
conducts and presents an on-resistance
IN
OUT
ADJ
of a few milliohms. The voltage drop
1
R2
across current-sampling resistor R1 is
G
Q2
R5
+ C1
+ C2
20k
2N3906
proportional to IC1s input current and
240
1 F
1 F
provides base drive for bipolar transisR3
20k
D2
tor Q2.
1N4002
As load current increases, the voltage
R6
across R1 increases, biasing Q2 into conR2
3.3k
20k
duction and decreasing Q1s gate bias. As
Q1s gate bias decreases, its on-resistance
increases, limiting the current into IC1,
according to IMAXVBEQ2/R1, or approximately 0.6V/1.
A few added components extend this linear regulators overcurrent protection.
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design
ideas
(2)
J1
12V
12V
C1
100 nF
C2
100 nF
R1B
6.49k
0.1%
R1A
1M
Figure 1
13
5
DIGITAL
INPUTS
B2
B3
8
9
B4
10
11
12
14
15
V
B1
IOUT
B5
IC1
DAC08
B6
8
IC2A
2 OP270
4
Q2
MMBT2222A
C4
100 nF
B7
COMP 16
B8
R3
1k
Q1
STD8N06L
R4
100k
C5
100 nF
VR
VR
V
VLC
R5
6.2k
3
R6
3.92k
0.1%
3
C3
100 nF
IOUT
J2
C6
10 nF
12V
R7
3.9k
5
+
IC2B
OP270 6
_
R8A
10
0.1%
R10
30.1k
0.1%
C7
100 nF
12V
R8B
10
0.1%
R11
1k
0.1%
This digitally programmable resistor features low component count and inexpensive parts.
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Power up a microcontroller
with pre-power-down data
Stephan Roche, Santa Rosa, CA
t is sometimes necessary to retrieve
data at power-up in the same way that
they were at the last power-down, so
that the product wakes up in the state it
had before shutdown or to retrieve some
measurement. One approach is to save
critical variables into EEPROM or flash
memory as soon as they change. This approach is generally not a good idea, because flash is typically limited to 100,000
write cycles, and EEPROM is typically
limited to 1 million cycles. These numbers may seem large, but a product can
easily reach them during their lifetimes.
Another approach is to use a battery to
keep the microcontroller supplied so that
it doesnt lose its RAM contents. This Design Idea presents an alternative option:
detecting a power-down and triggering
an interrupt routine that saves all the parameters in EEPROM or flash before the
microcontroller supply falls below the
operating threshold. Figure 1 implements such an approach for a PIC18F6720 microcontroller.
One of the many features of this microcontroller is its low-voltage detection,
which can trigger an interrupt when its
LVD input goes below a threshold. You
can set the threshold at 2.06V to 4.64V.
Power up a microcontroller
with pre-power-down data ..........................91
VIN
0.1 F
R1
0.1 F
PIC18F6720
R2
10k
LVDIN
Figure 1
The PIC18 microcomputer ceases functioning when its voltage supply is less
than 4.2V. Because the EEPROM/flashsaving cycle is fairly time-consuming, the
tactic is to monitor the voltage at the input of the 5V regulator to detect the power drop even before the microcomputers
supply starts to drop.
Select the LVD trip point inside the
PIC18F6720 to be 1.22V, and calculate
the required value of R2/R1 with the following equation:
where VIN_THRESHOLD is the trip point below which a data-save function triggers.
You should select this trip point to be as
high as possible but not too high to avoid
VIN
VIN_THRESHOLD
5V
4.2V
10 F
0.1 F
VSS
VCC
78L05
VCC
PIC18 CEASES FUNCTIONING
Figure 2
The VCC and VIN waveforms at power-down indicate the relationships in the sequence of events.
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design
ideas
VOUT 5
K1
IOUT
LOAD+
Q2
IRF150
R2
10k
3
1
2
RA
270k
VFEED
D1
1N4007
FEED 1
CURRENT/VOLTAGE
REGULATION
R1
470
3
2
Q1
R3
10k
VCC
Q3
IRF150
2N2222A
VCC
C4
100 nF
+ 3
8
1
CA3240/
DIP8
IC1A
RB
10k
R4
1k
VREF
LOAD
R5
1k
C5
1 F
R9
47k
VCC
8
7
CA3240/
DIP8
RSHUNT
0.33
50W
IC1B
4
R6
1k
R7
1k
VREF
Figure 1
R8
47k
C3
100 nF
Using MOSFETs and a relay, this electronic load can operate in both current- and voltage-regulation modes.
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design
ideas
3
Figure 1
design
ideas
700
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design
ideas
Figure 3
Figure 2 shows an alternative circuit
that provides a precision gain of one-half
300
with low offset, low drift, and low input200
bias currents and that uses an AD8221
instrumentation amplifier.
100
GAIN ERROR
The amplifiers output, VO, equals the
0
(V)
difference between the two inputs, VIN
100
and VIN: VO(VIN)(VIN). Connect200
ing the amplifiers output to its inverting input and substituting VO for VIN
300
13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
2
3
4
5
6
7
8
9 10 11 12
yields: VO(VIN)(VO), or VO(V IN).
VIN (V)
Thus, the circuit provides a precision
gain of one-half with no external com- The circuit in Figure 2 introduces a full-scale gain error of less than 300 V over a 26V inputponents and, in this configuration, is un- voltage range.
conditionally stable. The performance
plots of figures 3 and 4, respectively, show a gain error of less
than 300 V and a maximum
Figure 4
nonlinearity error of about 1
2
ppm over a 26V input-voltage
range.
1
To introduce an offset voltage,
VOS, that equals half of a refer0
NONLINEARITY ERROR
ence voltage (VOSVR/2), con(PPM)
nect the AD8221s reference in1
put (Pin 6) to voltage VR. To bias
the attenuators output at half of
2
the positive- or negative-power13 12 11 10 9 8 7 6 5 4 3 2 1 0
1
2
3
4
5
6
7
8
9 10 11 12 13
VIN (V)
supply voltage, connect the reference pin to the appropriate
The circuit in Figure 2 introduces a maximum nonlinearity error of about 1 ppm over a 26V input-voltage range.
power supply.
13
design
ideas
R2
10M
C1
100 pF
5V
6
6
4
IC1
LTC485
8
R5
100
7
3
R3
100k
1000 FEET
TWISTED-PAIR
CABLE
R6
1k
IC2
7 LTC485
2
5V
3
VCC
R7
10k
5V
R3
3.3M
C2
10 pF
Y1
C3
10 pF
C4
15 pF
CONTRAST
ADJUST
Figure 1
D7
D6
D5
CONTRAST D4
EN
RW
RS
GND
LCD1
19
17
16
15
14
13
12
11
28
27
26
25
24
23
22
21
7
6
5
4
3
2
VDQ 28
RC7
C5
RC6
0.1 F
RC5
RC4
OSC1 9 10 MHz
RC3
Y2
RC2
RC1
10
OSC2
RC0
5V
1
RB7
MCLR
R8
RB6
10k
RB5
IC3
D1
RB4 PIC16F73
BAV74LT1
RB3
RB2
RB1
RB0
RA5
RA4
RA3
RA2
8
RA1
18
RA0
A quartz-crystal temperature sensor provides Celsius-temperature readouts accurate to 2% over a 40 to 85C range.
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design
ideas
Calculator program
evaluates elliptic filters..................................76
5V
R7
470
R8
220
C1
100 F
R9
100k
_
+
IC1
R12
27k
LMC7211
6
4
R10
1k
R1
10k
0.5%
+ C
4
C2
1 nF
4.7F
R11
2M
C3
10 nF
R14
10k
0.5%
8
VCC
4
R
3
Q
IC2
7
DIS
LMC555
5
CV
6
THR
GND
1
2
R2
10k
0.5%
C5
100 nF
R15
100k
R13
4.99k
0.5%
TR
TO
MICROCONTROLLER
EXTERNAL
INTERRUPT
PIN
R3
30k
0.5%
R6
10k
0.5%
C6
10 nF
1%
R4
30k
0.5%
R5
30k
0.5%
KEYPAD
Figure 1
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Two ICs form a pulse-width-modulated keypad interface that uses only one microcontroller-input pin.
March 31, 2005 | edn 75
design
ideas
H(j)
(dB)
AMAX
AMIN
n=5
C S 1
Figure 1
The characteristics of an
elliptic filters amplitude response include inband ripple, passband-attenuation and stopband frequencies, and stopband attenuation.
Reference
1. Darlington, Sidney, Simple Algorithms for Elliptic filters and Generalizations Thereof, IEEE Transactions on Circuits and
Systems, Volume CAS-25, No. 12, December 1978, pg 975.
2 (RAD/SEC)
(e)
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design
ideas
USER-ACCESSIBLE
TERMINALS
9V
VOUT
VIN
LTC1798
GND
MODULATOR
2.5V
R2
237k, 1%
0.110V
R3
10k, 1%
0.010V
R4
1k
1%
NC
NC
IC2A
LTC6943
7
6
S1
12
11
10
NC
S2
USER-ACCESSIBLE
TERMINALS
An elementary model of
a batterys internal
impedance includes resistive and capacitive elements, but the capacitive elements introduce
errors in ac-based impedance measurements.
For improved accuracy, analyze the batterys
voltage drop at a frequency near dc.
Figure 1
SYNCHRONOUS
DEMODULATOR 9V
FORCE C2 R
5
1 F 10k
1
SENSE
BATTERY
UNDER
TEST
SENSE
R10 R1
10k 0.1
1%
D3
BAT-85
C6
10 F
NC
9V
R6
10k
IN
OUT
IN
CLKOUT
CLKIN
7
9V
9V
16
9 7 6 5 3 2 4 13 12 14 15
1
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12
VDD
CLK RST
11
10
Figure 2
FREQUENCY DIVIDER
VSS
R8
100k
NC
S4
13
NC
TO PIN 14
15
5
S3
16
FORCE C
3
1 F
14
C4
1 F
IC2B
LTC6943
CHARGE PUMP
D2
C7
BAT-85
10 F
INTERNAL
RESISTIVE AND
CAPACITIVE
IMPEDANCE
TERMS
IC5
LTC1150
OUTPUT
AMPLIFIERS
0 TO 1V
0 TO 1
OUTPUT
8
APPROXIMATELY
1-kHz SQUARE WAVE
V
4 V
1
SUPPLY
C5
200 pF
Q2
2N3904
R7
200k
This circuit determines a batterys internal resistance by repetitively applying a calibrated discharge current and measuring the
resultant voltage drop across the batterys terminals.
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design
ideas
R5
10M
R2
10k
SI4435
R1
1M
9V
IC1A
2 MC14093
IC1B
6 MC14093
C2
100 F
R4
16V
1k
14
8
IC1C
9 MC14093
7
R3
100k
C1
0.01 F
S1
C3
0.33 F
D1
1N4148
10
12
TO LOAD
IC1D
13 MC14093
R6
3.9M
11
C4
0.022
F
Figure 1
An improved power-off circuit automatically disconnects the battery after a preset on period.
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design
ideas
VDDEXT
2.7 TO 3.6V
C4
4.7 nF
GPIO PIN
TO HIBERNATE
7
SHDN
SW
VIN
2.7 TO 3.6V
L1
10 H
+
C5
10 F
IN
IC1
ADP3051
6
+
C1
10 F
VLG
8
VDD
FB
PGND
2
C2
270 pF
GND
8
R4
2.2k
SCL
5
1
GND
1
5k
SDA
IC2
AD5258
GND
A
10
SDA
I2C
INTERFACE
R2
10k
Figure 1
R3
2.2k
SCL
COMP
R1
47k
C3
27 pF
VDDINT
0.8 TO 1.32V
AD1
AD0
ADSP-BF531
Under control of its host processor, digital potentiometer IC2 adjusts the processors core power-supply voltage.
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designideas
erence diode. A voltage of 3.3V appearing at the LT1300s feedback-input terminal, Pin 4, indicates that the circuits
output is within regulation.
In applications that require a series
string of LEDs to operate with its low side
connected to ground, current sensing
must take place in the strings high side.
You can use either a rail-to-rail op amp
and a handful of passive components or
a dedicated current-sensing IC, such as
Maxims MAX4073T, to accomplish
high-side sensing. However, adding a
current-sensing IC increases circuit cost.
To complicate matters, in this applica-
High-side current-sensing
switched-mode regulator provides
constant-current LED drive ..........................95
Microcontrollers DAC provides
code analysis ..................................................96
Two gates and a microprocessor
form digital PLL ..............................................98
Simple sine synthesizer generates
19-kHz pilot tone for FM baseband
signal ..............................................................100
Publish your Design Idea in EDN. See the
Whats Up section at www.edn.com.
9V
LED
D3
R1
10k
C1
120 F
5
3
8
1
VCC 6
I-LIM
SHDN
P-GND
GND
LED
D4
L1
22 H
IC1
LT1300
SW
SENSE
SEL
D1
1N5817
7
4
LED
D5
R4
15
1
C2 +
10 F
R2
Q1
100k 2N4402
R5
1k
LED
D6
LED
D7
9V RETURN
C3
1 F
D2
1N5248
18V
LED
D8
R3
1k
3
LED
D9
LED
D10
Figure 1
S1
ON/OFF
design
ideas
References
1. LT1300 data sheet, Linear Technology Corp.
2. Application Note 59, Linear Technology Corp.
3. Caldwell, Steve, 1.5V battery powers white-LED driver, EDN, Sept 30,
2004, pg 96.
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design
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fCLK
INPUT
fIN
(2)
PRESCALE
+
ONE, TWO,
FOUR,
OR EIGHT
8-BIT
TIMER 1L
(COUNTER
MODE)
+2
design
ideas
14
15
CC
CC
4A
4B
CC
5A
13
10
11
12
5B
CC
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M
1
Figure 1
A typical keypad provides a limited number
of numeric keys and two
symbolsthe asterisk (*)
and the octothorpe (#).
0
adapt a configurable seri*
alizer/deserializer such as
D0
D1
D2
National Semiconductors LM2501.
Figure 2
The device typically
In a matrix keypad, pressing a key
finds use in adapting
creates a connection between a
video buses, such as wide,
row wire and a column wire.
low-voltage CMOS-video
interfaces for portable
MICROCONTROLLER
V
CAMERA
INTERFACE
YUV[7:0]
PCLK
MC
H
YUV[7:0]
PCLK
CAMERA
MD
MODE0
MODE1
MG
MODE0
WC
MCLK
MODE1
PD
MODE[1:0]=00'B
Figure 3
I2C
MODE[1:0]=00'B
WCLKOUT
WCLKIN
PD
In a typical application, a pair of LM2501s converts multiconductor video data to serial data and restores the data to multiconductor format.
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design
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LM2501 MPL DESERIALIZER
MICROCONTROLLER
VCC
R1
V
CAMERA
INTERFACE
D[7:0]
MC
H
D[7:0]
PCLK
PCLK
MD
MODE0
MG
SCAN PULSE
PULLUP
RESISTORS
D0
MODE0
WC
R3
1
B 4
C 7
10 MHz
MODE1
R2
D1
#
D2
D3
CD4017
CLK
CLK_ENA
MODE1
RESET
PD*
VCC
MODE[1:0]=00'B
WCLKOUT
WCLKIN
PD
Figure 4
You can apply the LM2501 to reduce the number of signal lines a keypad-to-microprocessor interface requires.
converts the selected active line to a serial signal, and transmits the signal to the
deserializer.
For example, suppose that the user
presses the 5 key. The first clock pulse
that the CD4017 receives drives column
line D0 to a logic one, but, because the
user does not press keys 1, 4, 7 and *, row
lines A, B, C, and D remain at logic zero.
The second clock pulse drives column
line D1 to a logic one, and pressing key 5
connects row line B to logic one, whereas lines A, C, and D remain at logic zero.
The pseudocode fragment in Listing 1,
available in the online version of this De-
VDD
2.7 TO 3.6V
1
0.1 F
IN
0.1 F
0.1 F
MAX6025
OUT 2
AIN1
5
REF
1
VDD
SCLK
2.5V
MAX1087 DOUT
GND
3
AIN2
3
CNVST
MICROCONTROLLER
6
GND
4
TRANSDUCER
Figure 1
design
ideas
VDD
2.7 TO 3.6V
1
0.1 F
IN
tolerance resistors may introduce an objectionable error. You can solve the problem by eliminating the divider, connecting the ADCs reference input to its
power supply, and connecting one of the
ADCs inputs to a precision voltage referencein this case, a 2.5V MAX6025A
(Figure 2).
In this configuration, the ADC measures its inputs with respect to the supply voltage. Using the digitized reference
voltage as a standard, the systems software computes the ratio of the reference
voltage with respect to the power-supply
voltage and corrects the remaining inputs measurements. The ADC must accommodate an external reference voltage that equals its power-supply voltage,
and any noise on the supply rail disturbs
measurements of all channels. Thus, to
quiet the supply rail in electrically noisy
environments, you may need to add a
lowpass filter to provide extra decoupling at the ADC.
MAX6025
1%
OUT 2
2.5V
1%
GND
3
0.1 F
5
2
AIN1
REF
0.1 F
1
VDD
MAX1087 DOUT
AIN2
3
SCLK
CNVST
MICROCONTROLLER
6
GND
4
TRANSDUCER
Figure 2
To eliminate the resistive divider, you connect the ADCs reference voltage
to its power supply and measure the precision voltage references output.
IGURE
20k
380k
400k
VIN
20k
+
_
VOUT
VIN
20k
+
VOUT
20k
(a)
(b)
Figure 1
design
ideas
AD629
30 pF
8
1 REF
21.1k
2 IN
380k
3 IN+
380k
NC
380k
VS 7
V IN
V S
V S
VS
0.1 F
OUT 6
20k
V OUT
REF+ 5
0.1 F
Figure 2
Figure 3
Figure 4
Figure 5
Simple hardware or software linear-control methods compress most of the apparent intensity variation into a relative-
design
ideas
12V
12V
R8
50
R1
4.3k
R9
50
R 10
50
R 11
50
NODE A
D 1 TO D 16
RED LEDs,
V F2V
3
R2
50k
1
IC 1
AD589
Q1
1
2N3906
2
R3
1k
Q2
2N3906
2
12V
C1
0.01 F
3
R4
200
1
Q3
IRFD010
7
+ IC
2
AD8031
2 _
4
R7
100
C2
0.01 F
Figure 1
R6
10k
R5
3
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design
ideas
The best of
design ideas
it out at:
8 Check
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designideas
Abhishek Jain, Netaji Subhas Institute of Technology, Dwarka, New Delhi, India
speedometer measures a wheels
rotational speed. Unlike conventional mechanical and moving-magnet designs that use analog movingpointer displays, the electronic speedometer in this Design Idea features a digital readout and a power-saving device
that uses few components. Figure 1
shows the digital speedometers circuit
design. An Atmel AVR AT90S2313 microcontroller, IC1, drives IC3, a 16-character, two-row LCD. All components except IC4, an Allegro A3121 Hall-effect
sensor reside on a pc board within the
reach and view of the vehicles operator.
The Hall-effect sensor attaches to the vehicle near its periphery and a fixed distance from the wheels axle. When the
wheel rotates, a permanent magnet attached to the wheel passes the sensor, activating it and generating one short pulse
for each revolution of the wheel.
After you apply the pulses rising edge
to the IC1s INT0 input, the rising edge
generates a high-priority interrupt. The
AVR calculates the elapsed time between
two interrupts, computes the speed and
distance traveled, and displays the results
on the LCD. One of IC1s internal timers,
Timer0, increments after every N clock
R1
10k
VSIG
D1
D2
1N4007 1N4007
5V
Figure 1
VIN
C6
0.01 F
GND
IC3
16-CHARACTER
TWO-ROW LCD
VCC
3
VO
4
RS
5
R/W
6
E
7
D0
8
D1
9
D2
10
D3
11
D4
12
D5
13
D6
14
D7
15
BL+
BL
C7
470 F
1
2
VGND
D4
D3
1N4007 1N4007
BRIDGE
RECTIFIER
5V
IC1
AT90S2313
12
S1
PB0/AIN0
13
PB1/AIN1
14
PB2
15
PB3/OC1
16
PB4
17
PB5/MOSI
18
PB6/MISO
19
PB7/SCK
5V
20
PD1/TXD
PD2/INT0
PD3/INT1
PD4/T0
PD5/T1
PD6/ICP
XTAL1
5V
BACKLIGHT ON/OFF
16
PD0/RXD
XTAL2
VCC
RESET
HALL-EFFECT SENSOR
2
3
3
6
7
VIN
GND
2
C5
0.1 F
5V
5V
8
9
11
C1
22 pF
5
4
X1
4-MHz CRYSTAL
10 GND
IC2
7805
1
3
VIN VOUT
IC4
1
VOUT VIN
2
C2
22 pF
RESET S2
C3
0.1 F
C4
10 F
design
ideas
5V
SENSOR RINGING
ZONE
1
PA0
R1
30k
30%
PA4
TRIGGER
IC1
MC68HC908QT2
INPUT
TIME
ECHO PULSE
PA1
OUT
DISTANCE
SET ECHO
DISTANCE
OUTPUT
TIME
The firmwares features determine the characteristics of this radar and sonar echo simulator.
contact. For this application, the firmware divides the digitized potentiometer
readings by four to match the systems reception range. Every 0.5 msec, the
firmware also generates internal timeroverflow interrupts that determine the
resolution of the simulated targets return
echo. The interrupt-service routine increments the distance counter, and, when
the counters value equals the distance
design
ideas
+ C6
1
2
3
11
L4
39 H
J1
L3
39 H
2.2 F
3
5
1
7
P1C N1C
SSVP SSVS
L5
39 H
10
R9
100
L2
330 H
OUT_L
C8
1 F
C9
1 F
C5
2.2 F
C2
0.01 F
J3
MINI PHONE PLUG
D1
1N5711
5 +
IC1B
MAX474
BT1
3V (TWO AAA
IN SERIES)
3 +
IC1A
MAX474
2 _
6 _
C4
470 pF
R1
4.7M
S1
Figure 1
C10
1 F
0.5-IN.
SPACING ON
CENTERS
R3
121k
R4
121k
R2
4.7M
C14
100 F
C1
2 TO
30 pF
IN_R
IC2
TPA4411
C3
3.9 pF
L1
150 nH
C11
1 F
IN_L
R10
100
OUT_R
STEREO PHONE
JACK TO
HEADPHONES
C7
2.2 F
to-rail, dual op amp, boost the level of demodulated audio that D1 and C4 recover.
Lowpass filters R5 and C12 and R7 and C13
limit audio bandwidth to voice-range frequencies to improve intelligibility and reduce power consumption. Capacitors C10
and C11 split the amplified audio signal
into two channels to drive stereo-headphone amplifier IC2, a Texas Instruments
TPA4411. Capacitors C8 and C9 drive
IC2s inputs with stereophonic audio signals from the aircrafts entertainment system or a portable CD/DVD player. The
TPA4411 headphone amplifier provides
a fixed gain of 1.5, which allows you to
maintain a comfortable listening level by
adjusting the aircraft-entertainment devices volume control. Potentiometer R6
R6
100k
R8
100k
R5
3.3k
C12
1 F
R7
3.3k
C13
1 F
NOTE:
MOUNT PHONE PLUGS J2 AND J3 ON 0.5-IN. CENTERS TO MATCH AIRCRAFT-ENTERTAINMENT SYSTEM'S AUDIO-JACK SPACING.
SELECT R1 TO BIAS DIODE.
This modern version of the crystal radio allows you to monitor aircraft communications while listening to in-flight-entertainment programs.
www.edn.com
design
ideas
radio to 127.4 MHz. When the pilot enters the squawk into the aircrafts
transponder, the flight controllers can
identify the aircraft on-radar screens as
KLM flight 657. Each time the aircraft
enters a new segment of the taxiway on
its way to the runway and again for takeoff clearance, the pilot contacts ground
control to get taxi clearances.
Shortly after takeoff, the pilot contacts
departure control:KLM 657, radar contact, climb and maintain FL320, turn
right heading 120, proceed on course.
From then on, the pilot contacts flight
controllers upon reaching predefined altitudes or when entering a different
flight-control centers airspace. Approximately 30 minutes before reaching its
destination, the aircraft begins its descent, and the pilot contacts approach
control. Just before landing, you hear the
final clearance: KLM 657 heavy, winds
030 at 12, cleared to land runway 31.
Reference
1. Wenzel, Charles,Passive aircraft receiver, www.techlib.com/electronics/air
craft.htm.
www.edn.com
design
ideas
two power supplies, a pc board, and a display. For simple products, you can assume that all of the power entering the
cabinet from the ac power line ultimately converts into heat that dissipates within the cabinet. After you calculate the systems ac and dc power requirements, you
can estimate the amount of power that
the cooling method must dissipate. As a
rule of thumb, the thermal capacity of air
is 0.569W-minute/C/ft3 (Reference 2).
That is, one cubic foot per minute of
moving air can transfer 0.569W of dissipated heat for a 1C temperature change.
You can also express this rule as its reciprocal: To dissipate the heat 1W of power
produces and maintain a 1C temperature change, you need to provide an air
design
ideas
Interrupt-driven keyboard
for MCS-51 uses few components
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design ideas
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design
ideas
problem and allows use of an interruptdriven keypad even in hardware-resetbased systems (Reference 1).
Reference
1. Chrzaszcz, Jerzy, Use 8051s power-down mode to the fullest, EDN, July
6, 2000, pg 138, www.edn.com/article/
CA47001.html.
VBATT
Figure 2
D1
WHITE
LED
+ SINGLE CELL
R3
100k
1.5V NOMINAL
L1
220 H
VA
Y
B
IL
Q1
2N3906
B
A
IC1
NC7SV57
Y
C1
3.3 F
R1
1M
Figure 1
VC1
R2
100k
C2
100 pF
R4
100
GND
Q2
2N3904
VCC
NC7SV57
GND
D1 and Q1s base-emitter junction are reverse-biased. Provided that the inductor
does not saturate, current IL ramps up
linearly and reaches a peak value, IL(PEAK)
at the end of the on-time.
When IC1s output goes low and Q2
turns off, L1 generates back EMF to forward-bias D1 and raises its anode voltage,
VA, to a value greater than VBATT. Current
circulates through L1 and D1 and ramps
down to zero as L1s stored energy decays.
Values of 100 pF for C2 and 220 k for
R2 set the astable oscillators frequency at
approximately 20 to 30 kHz. On each cycle, a current pulse with a peak value,
IL(PEAK),flows through the LED. Due to the
high repetition frequency and persistence
of vision, the LED appears to be continually on.
Without Q1 and R3, the astable circuit
design
ideas
mains even when battery voltage decreases to 0.8V. The circuit continues to
operate when VBATT decreases to 0.65V, although the LED dims considerably at
that level.
The NC7SV57s guaranteed operating
voltage ranges from 0.9 to 3.6V, which allows operation from one or two alkaline
or rechargeable nickel-cadmium cells or
from a single 3V lithium cell. Texas Instruments SN74LVC1G57 offers the
same logic functions but operates over a
slightly higher supply voltage range of
1.65 to 5.5V. To eliminate flashing operation, simply omit C1, R1, R3, and Q1. To
turn the LED on or off, you can apply a
gating signal to IC1s Input A.
Reference
1. Smith, Anthony, Single cell flashes
white LED, EDN, Dec 11, 2003, pg 84,
www.edn.com/article/CA339716.html.
duced in LS, and C1 provides lowpass filtering. The resultant dc voltage, VX, powers low-dropout regulator IC1, which
supplies a constant 3V to VFC IC2 and the
load resistors, RLF and RLV. Trimmer potentiometer RLV sets the output current at
2.5 to 13.5 mA.
The combined total current drain of
the low-dropout regulator and the VFC
measures a few tens of microamperes and
is negligible compared with the output
current. Hence, IIN approximately equals
IL,. Equation 1 expresses the dc output
power that the inductive power supply
produces:
(1)
design
ideas
IC1
D2
BAT54A
IIN
VX
IN
3V LOW-DROPOUT
REGULATOR
VDD
3V
IL
OUT
C2
1 F
C1
1 F
RLF
220
GND
R3
10M
Figure 1
RC
390k
D1
RSF
BAT54A 10
RLV
1k
VC
RD
1.2k
RSV
1k
R2
10M
R1
8.2M
+
Q1
FDV301N
LS
49 H
C3
12 pF
CS
33 nF
IC2
LMC7211
Q2
FDV301N
C5
0.1 F
R4
10M
C4
0.1 F
VOUT
A low-power VFC and load modulator measure power generated by a wireless-telemetry power source.
output ability by measuring the transmitted dc voltage that the VFC digitizes.
To minimize power consumption, component count, and pc-board area, a simple passive integrating network comprising RC, RD, and C5 replaces the classical
op-amp integrator that constitutes a typical VFCs input stage.
The VFC generates a constant-amplitude sawtooth voltage whose rising slope
is proportional to VX across integrating
capacitor C5. When the capacitors voltage reaches a high reference voltage,
switch Q2 rapidly discharges the capacitor to a low reference voltage. This action
produces a free-running waveform
whose frequency is proportional to the
input voltage,VX. A noninverting Schmitt
(3)
Equation 3 shows that, to reset the integrated voltage almost to 0V, the value
of R1 must be slightly lower than that of
R2. Using standard values of E12-series
resistors and taking into account powerconsumption constraints, select a value
of 8.2 M for R1 and 10 M for R2.Re-
Figure 3
160
140
120
100
OUTPUT
FREQUENCY 80
(Hz)
60
40
20
0
0
Figure 2
Oscilloscope measurements of the VFC show voltage across capacitor C5 (upper trace) and comparator IC2s output voltage, VOUT (lower trace), for a nominal input voltage of 12V.
10
12
14
16
18
design
ideas
tX and tON:
you can linearize the charging law of capacitor C5 to a ramp having a constant
slope (Equation 7).
(7)
(5)
(6)
These formulas are useful for designing the VFC in Figure 1 but yield little insight into the circuits global-transfer
function.You can apply the following approximations to simplify the calculations: Because tXtON, the PPM output
frequency is approximately fX1/tX. In
normal operation, VX reaches relatively
high values when compared with the
Schmitt triggers threshold voltages, and
VIN2VDIOUTRO), where VIN is the input voltage, VD is a diodes forward-voltage drop, IOUT is the output current, and
RO is IC1s output resistance in free-running mode. For a 300-A load current,
the circuits output voltage is 10V. Parasitic inductances inherent in the capacitors and pc-board traces produce a voltage overshoot that charges the output
capacitors, delivering more than 11V at
no load (Figure 2).
C3
2.2 F
4
C2
2.2 F
5
2
CAP+
1
VIN+
4
CAP
OUT
IN
C1
7
10 F
6
6
D1
CMPSH-3S
5
VOUT
C4
10 F
FB
D2
CMPSH-3S
C5
10 F
7
OUTPUT
VOLTAGE
8
(V)
9
IC1
MAX889T
10
SHDN
11
GND
3
Figure 1
This switched-capacitor inverter derives 10V from 5V.
12
0.001
AGND
8
0.01
0.1
10
100
1000
Figure 2
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
Q1
SOURCE-VOLTAGE INPUT
C1
OUTPUT TO REST
OF CIRCUIT
Q2
R3
designideas
T1
1
T2
1
R1
1.22k
1
Q1
13
START 1
STOP 1
S1
S2
2
2
PA1
9 PA2
8
D3
Q2
START
SWITCH
CLOSURE
R4
1.22k
t1
Q1
D4
12
PA0
R3
1.22k
D2
D1
1
R2
1.22k
1
Q3
Q4
PA4
PA5
5V
VCC
Q2
t2
OUTPUTS
VDD
IC1
MC908QY
PA3
VSS
1
1
16
Q3
C1
2 0.1 F
Q4
PB7
PB6
PB5
PB4
10
11
14
15
S3
S4
S5
S6
S7
S8
S9
S10
1
B3
PB3
PB2
PB1
PB0
B2
B1
B0
B3
B2
B1
B0
T1 SETUP
T2 SETUP
Figure 1 This dual timer comprises only a few switches and a microprocessor
whose internal clock sets the time intervals.
and S2 start and stop the timers operating cycles. The start function initiates
the main timer and operates only when
the timer stops. After activation, out-
put Q1 goes to logic one during interval t1 (Figure 2). Output Q2 complements Q1 and remains at logic one until
the next cycle starts. On Q1s trailing
edge, output Q3 goes to logic one for
time interval t2. After t2 elapses, output
Q4 goes to logic one and remains there
until the next cycle starts. You can use
the stop switch, S2, at any time to terminate a cycle and reset all four outputs
to logic one.EDN
For output voltages below 8V, switching regulator IC1 remains in shutdown
mode, and the output stage draws current through L1 and D1. Q1s collector
voltage, VC, measures approximately
11.4Vthat is, 12V minus D1s forward-voltage drop. Transistor Q1 monitors the voltage drop across R7, which
measures a fraction of Q2s collectorbase voltage, VCB. As long as VCB
exceeds 1V, Q1s collector current
remains high enough to drive IC1s feedback input higher than 1.25V, which in
turn keeps IC1 shut down.
As the output voltage increases, the
voltage differential across R7 decreases,
and, when it drops below 0.9V, Q1s col-
designideas
Apart from selecting the VCE ratings of
Q1 and Q3 to withstand the highest
desired output voltage, values of other
VIN
C2
0.22 F
D2
1N4148
VSW
LT1072HV
VC
R1
1.5k
VC
D5
36V
IC1
C1
100 F
25V
D1
1N4936
L1
220 H
12V
SUPPLY
components are not critical. If you substitute appropriate components for D5,
Q1, and Q3, the circuit can deliver out-
R6
3.3k
R7
4.7k
C4
100 nF
D3
1N4148
R2
1k
FB
GND
C3
22 F
63V
Q1
2N5087
R4
10k
R3
10k
R9
15k
0 TO 2V
CONTROL INPUT
FROM DAC
_
IC2
LM358
D4
1N4148
R11
10k
OUTPUT
0 TO 32V
Q3
BC237
R10
1k
Q2
MPS-U45
R8
4.7k
R12
4.7k
R13
100
Figure 1 Able to deliver a wide range of output voltages, this regulator circuit automatically selects a linear or a switched mode
as required.
designideas
D1
1N4148
R6
3.3k
D2
1N4148
SECOND INTEGRATOR
V+
IC1A
SUMMING
AMPLIFIER
C3
5 pF
R1
68
FIRST INTEGRATOR
R7
68k
LIMITER
IC1B
5V
IC1C
V
C1
RV2
0 TO 100k
BANDPASS
FILTER
R2
3.3k
RV1
0 TO 100k
C2 LOWPASS
FILTER
R5 HIGHPASS
15k FILTER
R4
15k SUM
R3
3.3k
R8
15k
SCHMIDT TRIGGER
R9
150k
VIRTUAL-GROUND SOURCE
SQUARE-WAVE OUTPUT
IC1D
S1
SINE-WAVE OUTPUT
IC1E
IC1F
R10
15k
C4
330 F
+
R12
15k
R13
15k
C5
330 F
R11
150k
SINE-WAVE OUTPUT
GND
NOTE: IC1=74HCU04 HEX INVERTER.
Figure 1 Build a sine-wave source around a single high-speed CMOS hex inverter and a handful of components.
designideas
and the circuit oscillates with adequate
gain and phase margins. Due to its
symmetric internal configuration, a
CMOS-inverter circuit attempts to
maintain a logic threshold of one-half
of its supply voltage. However, an Nchannel MOS transistor conducts
more than its P-channel counterpart,
and the logic threshold shifts slightly
toward the negative supply rail. Because an imbalance would lead to
asymmetry if you use it as is for limiting the oscillations amplitude, a pair of
back-to-back 1N4148 diodes, D1 and
D2, serves as a symmetrical limiter, preventing the gates from clipping the
bandpass filters output.
Soft clipping eases the filters performance requirements by producing
a third-harmonic level of 17 dB at the
clippers output. The filters response
peaks at 17 dB at the oscillation frequency, and the lowpass node provides
20 dB of third-harmonic attenuation
for a theoretical third-harmonic total
rejection of 54 dB. In practice, the
CMOS devices gain and threshold
characteristics depart from ideal performance, and, as a result, the circuit
produces sine waves that approach 1%
distortion at the lowpass node, an acceptable level for the intended application. Replacing the CMOS inverters
with operational amplifiers would further enhance performance.
The filters highpass node provides
the first integrators input signal, and
the two cascaded integrators approach
a 180 phase shift for all frequency
components and also attenuate harmonic frequencies by a factor of 1/N2,
where N represents the harmonic
number. Subtracting some of the highpass signal, which contains harmonics
produced by the diode limiter, from the
lowpass signal further reduces the outputs harmonic components. Resistors
R8 and R9 form a 10-to-1 cancellation
circuit that provides an additional 6-dB
harmonic reduction for a 0.5% distortion figure at the signal output. Figure
2 shows harmonic levels for a 500-Hz
fundamental output frequency.
Oscillation occurs at unity gain at
which the integrators capacitive reactance equals the integrators resistance,
0
10
20
30
40
VOUT
(dB)
50
60
70
80
90
100
110
50.0082
500.082
5.00082k
FREQUENCY (Hz)
designideas
READERS SOLVE DESIGN PROBLEMS
Comprising a microprocessor, an
LCD, a 32.768-kHz crystal, and
little else, the basic countdown-timer
circuit in Figure 1 operates from a
commonly available CR2032 lithiumcoin-cell battery. Based on the circuits
calculated current drain, the battery
may never need replacement over a
projected 10-year operational life.
Careful selection of the battery and diligent exploitation of the microprocessors low-power modes help minimize
power consumption and thus maximize
battery life. The coin-cell batterys size
and flat form factor encourage miniaturization for portable-system applications. In addition, the lithium cell presents a flat voltage-versus-time discharge
curve that allows direct drive of the
LCDs segments to produce high contrast without additional compensation
circuitry.
A typical CR2032 cell delivers ap-
proximately 200 mAhr of rated energy capacity. To achieve the design goal
of 10 years of continuous operation,
the systems average current consumption must not exceed 2.28 A, which
you calculate by dividing the batterys
energy capacity by the systems operational life: 200 mAhr/10 years/365
days/24 hours2.28 A. A microprocessor from Texas Instruments
MSP430 family presents a low-standby-current demand of only 0.8 A,
which includes current drawn by its
crystal oscillator, integrated LCD
driver, and interrupt-driven wake-up
timer. The 31/2-digit LCD, a Varitronix
model VI-302-DP, consumes an additional 1 A. The total standby-current
consumption for all active countdowntimer components is thus 1.80 A.
In normal (standby) operation, the
microprocessors 32-kHz external-crystal clock drives an internal counter that
DISPLAY
BUS
CONNECTIONS
R1
68k
3V
BATTERY
DVCC/AVCC
S0-S23
RST/NMI
COM0-3
RESET
DVSS/AVSS
S1
IC1
MSP430F412IPM
32,768 Hz
XIN
XOUT
Y1
Figure 1 A half-dozen components are all it takes to build a battery-thrifty countdown timer.
D Is Inside
80 Wide-range regulator delivers
12V, 3A output from 16 to 100V
source
82 Stable, 18-MHz oscillator
features automatic level control,
clean-sine-wave output
84 Ultra-low-noise low-dropout
regulator achieves 6-nV/Hz
noise floor
generates an interrupt once per second.
The interrupt awakens the processor,
which executes an active main-software
loop that decrements a countdown register via direct BCD (binary-coded-decimal) subtraction. Adding a value of 99
(decimal) to the countdown register
and discarding the leftmost digit perform a one-digit subtraction. For example, 2199120; dropping the one in
the 100s place yields a value of 20. As
a bonus, this method directly displays
the countdown registers contents on
the LCD without requiring currenthungry binary-to-BCD conversions.
(You can download the timer softwares
assembly-language listing from the
online version of this Design Idea at
www.edn.com/050623di1.)
As a final step, the main loop compares the countdown registers contents
with zero to determine whether the preprogrammed time interval has expired.
If so, the display flashes the time-out
message. The main loop activates the
CPU and its on-chip high-speed oscillator, which consume a total of 250 A.
Writing the software to execute 100 or
fewer clock cyclesequivalent to 100
sec at the default 1-MHz CPU clock
frequencyreduces current demand.
With such a short active period, the
main loops total current consumption
is virtually negligible: Main loop250
mA(100/1 million)0.025 A.
designideas
Thus, total current consumption for
the digital countdown timer is the sum
of the standby- and main-loop currents:
1.80.0251.8 A.
At approximately 1.8-A average
current consumption, the countdown
timer easily meets the 2.28-A design
goal and ensures more than 10 years of
continuous operation. Given the devices low current drain, a designer
could reduce the timers cost and complexity by packaging the circuitry along
with a nonreplaceable battery. Many of
the microprocessors functions and I/O
pins remain unused and available for
additional features, and the compact
firmware for implementing the counter occupies less than 250 bytes of 8
kbytes of available flash memory.
Applications for the circuit range
designideas
100
inant loss component. For
currents as high as 3A. This rou95
applications with less critical
tine-sounding specification also
90
space requirements, you can
requires operation in a physi85
improve circuit efficiency by
cally and electrically harsh
80
increasing L1s inductance and EFFICIENCY 75
environment in which the
(%)
size, thus reducing ripple curpackaged circuit resides on an
70
rent and enabling use of a largengine block that reaches a
65
60
er core and increased windingtemperature of 125C, and
55
wire gauge. Reducing the outambient-air temperature reach50
put voltage improves efficienes 100C. In addition, the
0.5
1
1.5
2
2.5
3
OUTPUT CURRENT (A)
cy, but, as output voltage drops
power source comprises two
below the circuits 8V boot- Figure 2 Circuit efficiency varies as functions of powerseries-connected 12V batteries
strap voltage, IC1 dissipates supply input voltage and load current.
that provide a nominal voltage
additional power and requires
of 24V, which in practice varies
caution to avoid exceeding its ratings.
One practical application for the cir- from 18 to 40V and includes inductively
Figure 2 shows the circuits measured cuit met a customers requirement for a induced load-dump voltage spikes that
efficiency versus output current for dc/dc converter that would operate from reach 100V.EDN
three input voltages.
a 24V source and deliver 12V output at
Spice-circuit simulation predicts a second-harmonic amplitude of 35 dB below the fundamental. The second harmonic exceeds the amplitudes of all
higher order harmonics, and an oscilloscope measurement displays a cleanlooking sine wave across the 50 load.
To provide a good termination for
the amplifier and still obtain 7.3 dBm
(1.47 V p-p)for example, to drive a
diode-ring mixeryou can insert a
50, 5-dB pad between output transformer T1 and the load. Potentiometer
R2 adjusts the RF output level, and, for
increased stability, you can replace R2
with a fixed resistive divider built with
low-temperature-coefficient, metalfilm, fixed resistors. Part of the signal
at Q4s collector drives the gate of JFET
source follower Q5 through C7 and R9.
Diode D1 rectifies the signal, which, after filtering, feeds operational amplifier IC1s inverting input. Resistor R1 and
low-temperature-coefficient potentiometer R2 divide the 12V supply to
produce a dc reference voltage for IC1s
noninverting input and set the output
signals level. After filtering, IC1s dc
output drives Q1s Gate 2 to set the devices gain and thus control RF output.
Connected to the center tap of coil
L1, trimmer capacitor C18 allows fine
adjustment of the oscillators frequency. If decreased frequency stability is
acceptable, you can replace C18 with a
low-cost ceramic trimmer. Piston-type
trimmers are rather expensive and less
available than ceramic trimmers, but a
typical ceramic trimmer exhibits a
temperature coefficient thats at least
an order of magnitude worse than a piston trimmers. To operate the oscillator at a frequency other than 18 MHz,
multiply the inductance of L1 and the
capacitances of C12, C13, C16, C17, and
C18 by 18/fOSC2, where fOSC2 is the new
frequency in megahertz. Adjust the tap
for Q1s source connection so that it remains at about 20% of the windings
total number of turns as counted from
the inductors grounded end.
You can replace the series combinations of C12 and C13 with a 13-pF capacitor, and you can replace C14 and
C15 with a 2.5-pF capacitor. If you redesign the circuit for a different frequency, adjust the values of C14 and
C15 or their single-capacitor replacement for just enough capacitance to
ensure reliable start-up under all anticipated operating conditions. Also, note
that using two capacitors for C16 and
C17 helps reduce start-up drift, as does
designideas
12V
NOTES:
L1: EIGHT TURNS #22 AWG WIRE ON A 5/8-IN.-DIAMETER
COIL FORM AT 24 TURNS PER IN.
SOURCE TAP IS 1.5 TURNS FROM THE GROUNDED END.
TAP FOR C18 IS FOUR TURNS FROM THE GROUNDED END.
T1 PRIMARY: 25 TURNS #24 AWG WIRE ON A CWS
BYTEMARK F-50-61 CORE.
SECONDARY: FIVE TURNS #24 AWG WIRE INTERLEAVED
BETWEEN THE PRIMARY TURNS ON THE SIDE
OPPOSITE FROM THE PRIMARY LEADS.
C18: 1- TO 10-pF GLASS OR CERAMIC PISTON TRIMMER.
C2
0.01 F
R1
10k
1%
R3
3.3k
2 _
IC1
IL082
R2
5k
C3
0.01 F
1
3 +
C4
0.01 F
C1
0.01 F
R4
10k
R5
33k
C5
1000 pF
D1
SD101C
12V
Q5
C6
2N5486 R
0.01 F S
8
10k
1%
R7
R6
3.3k
1.5k
R9
3.32k
1%
C7
0.01 F
12V
8V
C14 C15
5 pF 5 pF
C12
22 pF
FOUR
TURNS
C13
33 pF
FOUR
TURNS
L1
1.09
H
C16
22 pF
C17
33 pF
C10
C9
0.01 F 0.01 F
Q1
BF998 D
G2
Q2
G1
2N5486 D
S
R13
1M
R14
10k
SECONDARY
T1 WINDING
ARRANGEMENT
T1
12V
25
TURNS
C11
0.01 F
C8
1000 pF
PRIMARY
R10
47
VOUT
VOUT
2.61VP-P
12.3 dBm
R11
10k
C19
0.01 F
FIVE R12
TURNS 50
Q3
2N3904
Q4
2N3904
R18
47
1.5 C
18
TURNS
R15
2.2k
R16
2.7k
R17
1k
R19
82
C20
0.01 F
12V
Figure 1 This low-distortion, 18-MHz oscillator offers high stability and automatic output-level control.
using temperature-stable (NP0-characteristic) ceramic-dielectric capacitors for C12 through C17. The buffer amplifier, Q2 through Q4, requires modifications for operation at frequencies
above approximately 25 MHz.
A well-regulated external dc source
(not shown) provides 12, 12, and 8V
to the circuit. To maintain high stabil-
REFERENCES
1 Martnez, H, J Domingo, J Gmiz,
and A Grau, JFETs offer LC oscillators
with few components, EDN, Jan 20,
2005, pg 82.
2 Reed, DG, editor, A JFET Hartley
VFO, ARRL Handbook for Radio
Communications, 82nd Edition, American Radio Relay League, 2005.
designideas
VDD
OUTF
IN
VDD
VDD
R1
10k
Q1*
FDN302P
OUTS 6
IC1
MAX6126
C2
1 F
C3
1 F
IC2
MAX4475
C1
100 F
VN_REF
MAX8887
1000
NOISE DENSITY
100
(nV/Hz)
VN_OPAMP
R1
IOUT=100 mA
VDD=3.4V, VOUT=3.3V
FIGURE 1
IC1
C1
10,000
IN_OPAMP
Q1
IC2
+
10
VN_FETs
NOISE FLOOR
1
10
100
1000
FREQUENCY (Hz)
Figure 3 A noise-density-versus-frequency plot for the lowdropout circuit in Figure 1 is 38 dB lower than that of a conventional low-noise, low-dropout-voltage regulatorin this
case, a Maxim MAX8887.
designideas
READERS SOLVE DESIGN PROBLEMS
Contact-debouncing algorithm
emulates Schmitt trigger
D Is Inside
88 Inexpensive peak detector
requires few components
Among other interface problems, contact bounce complicates the connection of mechanical
contacts or any noisy digital input signal to a microcontroller. Although
designers have proposed a variety of
hardware and software approaches
that address the problems that contact
bounce poses, no one has yet claimed
a definitive and predictably stable
approach. (For a sampling of approaches, see references 1 through 10.)
The usual hardware approach to eliminating contact bounce comprises an
RC filter followed by a Schmitt trigger
(Figure 1). You can extend the filters
effectiveness simply by increasing the
RC time constant at the expense of
increased response time.
Software-debouncing methods usually include 1-bit processing, which
involves twice reading the contacts
input state with a fixed delay between
the two readings. You can also implement a state machine or launch an
input signal through a shift register and
wait for three or four register-output
states that havent changed. The low
efficacy of 1-bit processing approaches
5V
R1
10k
R2
220k
C1
220 nF
IC1
OUT
S1 ELECTROMECHANICAL
SWITCH CONTACTS
designideas
quately processes most switches contact bounce.
You can easily modify the main filter
coefficient to provide different filteringtime constants. For particularly troublesome contact bounce, you can use
the following recursion formula, which
requires 16 time constants to trigger the
software Schmitt routine. YNEW(1/16)
XNEW(15/16)YOLD. You can implement this algorithm with only eight
assembly-language instructions, whereas the Schmitt-trigger routine requires
12 instructions. When you combine
both of these routines, the software
Schmitt trigger updates bit 0 of a register, which the main program loop
should continuously check to ascertain
the contacts status. As an alternative,
you can activate a software interrupt to
signal a contacts status change. To do
so in the AVR architecture, you write
to that port bit that functions as an
external interrupt input.
Always avoid connection of mechanical contacts to interrupt inputs
unless the contacts undergo hardware
debouncing. Otherwise, the contacts
may bounce dozens of times, unnecessarily consuming processor-machine
cycles. The software routine reads the
inputs only every 4 msec and thus
imposes additional filtering on the
inputs. Simulation and practical testing
have confirmed that the debouncing
algorithm behaves as expected, producing clean output transitions when
enduring noisy contacts. When you
program the assembly-language source
code accompanying this Design Idea
into an Atmel Atmega8, the code turns
on an output LED connected to Port_B
bit 0 when Port_D bit 0 of the microcontroller goes to ground.
A simulated input waveform
(pind0) and its corresponding output
log file (portb0.log, both available at
the Web version of this Design Idea at
www.edn.com/050707di1,) illustrate
the filters excellent debouncing capabilities. Beginning with a key closure at
10 msec, the stimulus loads into the
AVR Studio integrated development
environment. After multiple input
transitions, the output-log file shows a
single output transition occurring at
paul.hills/Circuits/MercurySwitch
Filter/MercurySwitchFilter.html,
August 2001.
2 Baker, Bonnie, The debounce
debacle, EDN, Oct 28, 2004, pg 26,
www.edn.com/article/CA472833.
3 Ganssle, Jack, My favorite hard-
5.5
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
0
0
10
20
30
40
50
60
70
80
90
100
TIME (mSEC)
Figure 2 Switch contacts first close at 10 msec and then bounce erratically for
more than 50 msec before reaching a stable closed condition.
VOLTAGE
(V)
0
0
10
20
30
40
50
60
70
80
90
100
TIME (mSEC)
Figure 3 The debouncing-software routine signals that the contacts have closed
only after bouncing ceases.
designideas
ware debouncers, Embedded Systems
Programming, June 16, 2004, www.
embedded.com/showArticle.jhtml?
articleID=22100235.
4 Ganssle, Jack, The secret life of
switches, Embedded Systems Programming, March 18, 2004, http://embed
ded.com/showArticle.jhtml?article
ID=18400810.
5 Smewing, Alan, Icc-avr keypaddebounce code, http://dragonsgate.
net/pipermail/icc-avr/2004-March/
003376.html, March 4, 2004.
6 Switch debouncing, www.mite
du.freeserve.co.uk/Design/debounce.
htm.
7 Matic, Nebojsa, The PIC Microcontroller, www.mikroelektronika.co.yu/
english/product/books/PICbook/
7_03chapter.htm.
8 Ganssle, Jack, Smoothing digital
inputs, Embedded Systems Program-
(continued on pg 92)
VS 5V NOMINAL
R2
1M
C1
1 F
2
IC1
TLC372
3
VIN
R1
100k
+
2 _
3
8
IC2A
LM358
+
1 VOUT
5 +
R3
100k
IC2B
VOUT
6 _
C2
100 nF
VS 5V NOMINAL
designideas
A relatively large value of capacitance
minimizes the negative-going ripple on
VOUT, which can be useful when dealing with low frequencies, low-dutycycle pulse trains, or both. However,
making C1 too large renders the detector sluggish when responding to a sudden decrease in input-signal amplitude.
Note that C1 also affects the attack
time; for example, doubling the capacitance doubles the time the circuit
takes to acquire the peak level of VIN.
Because the comparators feedback
path includes op amp IC2A, offsets and
errors that IC2A presents have no effect
on the circuits accuracy. At low to
moderate frequencies, only the comparators input offset errors contribute
to the detectors overall accuracy. At
high frequencies, the comparators
response time becomes a significant factor, leading to a reduction in VOUT that
worsens as the frequency increases.
Despite these limitations, the circuit
performs well over several decades of
frequency from approximately 50 Hz to
500 kHz. Figure 2 and Table 1 show
the test circuits sine-wave-frequency
response by plotting the error in VOUT
for three peak levels of VIN.
The oscilloscope photo shows the circuits response to a 500-mV peak sine
wave at 400 kHz, in which the output
voltage, at 488 mV, lies just below the
positive peaks (Figure 3). In addition
to exhibiting good sine-wave response,
the test circuit produces good results
with rectangular signals of duty cycles
as low as 5%. Note that the virtual
ground at IC2As inverting input
restricts VOUT to positive voltages only.
Therefore, the circuit can respond only
to true positive peaksthat is, peaks
that go above 0V. If the input signal
goes entirely below 0V, VOUT simply
levels off at 0V.
Although not essential to the circuits operation, the lowpass filter and
buffer formed by R3, C2, and IC2B can
minimize any switching noise that
appears on VOUT. However, offset errors
inherent to op amp IC2B affect the filters output voltage.
Figure 4 shows a single-supply version of the circuit, in which RA and RB
set a reference voltage, VREF, at IC2As
Error VIN=2.5V
peak (%)
0.4
0.4
0
0
0
2.4
12
Error VIN=250
mV peak (%)
0.8
1.2
0.4
2.4
4
4.8
6
Error VIN=25
mV peak (%)
10
10
6.4
7.6
22
28.4
34
15
10
5
0
5
10
ERROR 15
(%)
20
25
VIN=2.5V PEAK
VIN=250 mV PEAK
VIN=25 mV PEAK
30
35
40
100
1000
10,000
FREQUENCY (Hz)
100,000
1,000,000
Figure 2 Plotting the difference between peak signal levels and output voltage
for three peak levels illustrates the detectors frequency response.
100 mV/DIV
100 mV/DIV
1 SEC/DIV
designideas
VS
R2
1M
RA
2
3
IC1
TLC372
+
R1
100k
2 _
4
VREF
VIN
CA
100 nF
VOUT
Figure 4 For operation from a single power supply, this version of the peak
detector sets a reference voltage via resistors RA and RB.
8
IC2A
LM358
3
+
4
RB
C1
1 F
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
IC1
8
R1
100k
R2
1k
6
NC
CAT
BASE
AN
EMT
NC
6
R3
15k
VCC
5V
R5
1k
R4
10k
NC
COL
MOC211-M
R6
47k
Q1
BSS-138
REPRESENTATIVE
LATCH-UP-PRONE
DEVICES
IT
MICROCONTROLLER/
DSP
EEPROM
ETC
Figure 1 Upon sensing an overcurrent spike, this circuit interrupts power and
enables the circuits recovery from ESD-induced latch-up.
designideas
High-impedance FET probe extends
RF-spectrum analyzers usable range
Steve Hageman, Windsor, CA
5V
J1
R2
100
C1
0.047 F
INPUT
R1
1M
C2
6.8 pF
D1
BAV99L
C4
0.22 F
R5
51.1
1M 15 pF
0.8V P-P
MAXIMUM
2 _
J2
OUTPUT
C3
0.22 F
4
IC1
OPA656NB
50
5V
R3
249
R4
249
5V
5V
5VIN
5VIN
NOTES:
ENCLOSE IN BRASS TUBE FOR SHIELDING.
ALL RESISTORS ARE 1%.
+ C
C6
5
2.2 F + 2.2 F
Figure 1 Just a handful of parts can help extend a spectrum analyzers performance. This unity-gain probe emulates a standard oscilloscope probes 1-M and 15-pF input characteristics and easily drives 50 loads.
designideas
the limited large-signal response does
not affect most applications.
High-performance FET input operational amplifier IC1, a Texas Instruments OPA656, provides a voltage gain
of two. This configuration yields a
bandwidth of approximately 200 MHz
(Figure 2). The OPA656 can drive
50 back-matched loads for a total
load of 100, which results in a 6-dB
gain loss for which IC1s gain of two
compensates for a net gain of unity. The
OPA656 also introduces lower noise
and distortion than that of most commercially available, active FET-based
probes.
The probe in Figure 3 fits into a
small section of brass hobby tubing.
The input connector comprises a small
SMA edge-launch connector that you
can easily adapt to other connectors,
including the BNC and its many accessories. The probe requires 5 and 5V
at approximately 18 mA each, which
you can obtain from an instruments
probe-power connector if available
or from a linear supply designed around
an ac wall transformer. For best
results, use 78L05 and 79L05 voltage
regulators to stabilize the supply
voltages.
Standard miniature 50 coaxial
cable connects the probe to the meas-
dB
AMPLITUDE
RESPONSE
(dB)
1
0
1
2
3
CH1
5
6
7
ABS
1
START 0.300 MHz
FREQUENCY (MHz)
Figure 3 You can assemble the probe on a piece of breadboard that fits into a
section of brass tubing from model and hobby shops. An SMA input connector
matches a multitude of adapters and probe tips, a few of which are shown.
Use a rubber grommet to close the probes output end.
uring instrument. For the flattest frequency response and uniform gain, terminate the probes output with 50;
designideas
The protection circuit consumes no
power except when the battery undergoes charging and therefore doesnt burden the battery. Supervisor IC1 provides
a RESET output that can serve as a
charger-ready interrupt input to the
baseband-controller CPU. The RESET
outputs open-drain structure allows its
connection to other circuits that operate from different supply voltages. Supplying power to the watchdog and
PWM circuits only during charging also
prevents reverse current from flowing
into the IC1s RESET output and discharging the battery via a sneak path.
The timing diagram illustrates the
circuits operation when an active
D1
SI5853DC
Q2
CHARGER
INPUT
R3
BASEBAND
PWM INPUT
R1
MAIN
BATTERY
ONE LI-ION
OR
THREE NIMH
Q1
R2
GROUND
Q2
CHARGER
INPUT
R3
51k
R4
5.1k
VCC
IC1
MAX6321HPUK30-CY
WDI
CHARGEREADY SIGNAL
TO BASEBAND
PROCESSOR
VCC
RESET
NC
MAIN
BATTERY
ONE LI-ION
OR
THREE NIMH
D1
SI5853DC
IC2
MAX4514CUK
..
..
..
.
RESET
GND
BASEBAND
PWM INPUT
GND
D2
5.1V
R1
240k
C1
0.1 F
CERAMIC
R2
56k
Q1
BC847
GROUND
Figure 2 Adding watchdog protection to the circuit of Figure 1 guards against battery damage when the baseband processor stalls or ceases software execution.
VCC
1V
VRST
VRST
1V
VCC
tRD
RESET
tRD
WDI
tRST
GND
RESET
RESET
tRP
tRP
GND
NOTES:
tRP=RESET-ACTIVE-TIME-OUT PERIOD (200 mSEC).
tRD=RESET-DELAY TIME FROM VCC (40 SEC).
tRP
tWD
tRP
NOTES:
tWD=WATCHDOG-TIME-OUT PERIOD (1.6 SEC).
tRP=RESET-ACTIVE-TIME-OUT PERIOD (200 mSEC).
designideas
charger connects to the phones charger-input socket (Figure 3). In this
example, the MAX6321-HPUK30-CY
that IC1 uses is factory-trimmed for a 3V
reset threshold, and the -CY suffix indicates complementary reset outputs and
a 1.6-sec delay interval. The reset interval begins when VCC reaches 3V45
mV. After 200 msec, RESET goes low,
input and pausing the charger algorithm using a CPU interrupt that the
charger-ready signal conveys (Figure
4). All active and passive components
for the circuit are available in surfacemount packages. Pass transistor Q2, a
Siliconix-Vishay SiS5853, includes an
integrated Schottky diode, D1.EDN
(1)
(2)
In a practical design, you select values for IKNEE and ISC and equal values for
R3A and R3B and then use equations 1
and 2 to calculate resistors RSC and R4.
For the circuit in Figure 1, the outputs
maximum and short-circuit currents are
fixed at 0.7 and 0.05A, respectively.
With R3A and R3B set to 100, solving
the equations yields values of 0.73 for
RSC and 4.3 k for R4.You can demonstrate the circuits performance by
applying a variable-load resistor thats
adjustable from 0 to 200. As Figure
2 shows, the outputs simulated and
measured voltage-versus-current characteristics, VOUT and IOUT, respectively,
are in close agreement.EDN
REFERENCES
Hulseman, Herb, MOSFET
enhances voltage regulators overcurrent protection, EDN, March 3, 2005,
pg 74.
2 Galinski, Martin, Circuit folds back
current during fault conditions, EDN,
Nov 28, 2002, pg 102.
1
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
94 Precision active load
operates as low as 2V.
designideas
R18
330
R5
2.2k
+
+
C10
1000 F
C2
100 F
R8
15k
R4
27k
C1
3.3 F
+
VIN
R6
270k
C3
2200 F
R2
1M
Q1
BC546C
220
9V
Q3
BC159
C4
0.22 F
Q4
BC337
Q2
BC337
R7
390k
C9
1000 F
R9
560
R11
27k
C8
10 F
+
R12
100
R10
15k
R3
2.2k
R14
1k
VOUT
+
C5
220 F
C7
3.3 F
R13
390
R19
3.3k
D1
KA262
R15
1.5k
Q5
BC337
+
Q6
BC337
C6
100 F
D2
KA262
R17
1.8M
R16
56k
Figure 3 You can assemble this AGC circuit entirely from discrete components.
circuits attenuator from the input-signal source and output load. Figure 2
illustrates a typical small-signal bipolar
transistors short-circuited VI characteristic, showing that you can control
differential resistance over at least five
decades of rangethat is, more than
100 dB.
In a practical circuit, the finite values of R1 and R2 limit the control range.
For proper operation and to keep the
signals THD (total-harmonic-distortion) factor, k, below 5%, the outputvoltage amplitude, VOUT, should be just
a few millivolts. Even with these limitations, this attenuator circuit appears
to offer one of the best and simplest
AGC circuits.
Figure 3 shows the completed circuit
design. The input signal, VIN, drives
buffer stage Q1, whose unbypassed
emitter resistor, R3, serves four purpos88 EDN | AUGUST 4, 2005
determinant (h11Eh22Eh12Eh21E),
which this Design Idea includes for theoretical accuracy. However, you can
neglect the numerical value of DhE for
modern silicon transistors without significantly affecting the calculations
accuracy.) Third, as Equation 2 shows,
leaving R3 unbypassed helps linearize
the response of Q1s collector currentto-voltage drive. Fourth, Q1s differential base input resistance rises to:
RdBASEh11Eh21ER3, which is larger
and less dependent on Q1s instantaneous operating point than h11E alone.
In Figure 3, resistor R4 forms the
variable attenuators fixed resistance,
analogous to the upper resistor, R1, in
Figure 1, and Q6 forms the attenuators
variable-resistance element. Transistor
Q5 supplies Q6s collector-drive current,
and Q5s common-emitter configura(continued on pg 92)
designideas
tion draws little base current. This
approach enables use of a high value for
AGC-release time-determining resistor
R17, thus permitting a long AGCrelease time. Resistor R19 limits the
maximum dc control current through
Q5 and Q6.
The large value of C3, when you compare it with Q6s minimum differential
resistancethat is, its maximum signal
amplitudeat full control, presents
negligible reactance to the lowest frequency-signal-spectrum component.
A voltage-doubler rectifier comprising
D1 and D2 extracts a portion of the signal from output stage Q4 and produces
the control voltage for Q5. This
arrangement accommodates both
polarities of large peak amplitudes of
nonsymmetrical signal waveforms.
Resistor R15 determines the AGCs
attack time. Too small values of R15
in combination with C6 can lead to
instability by creating a pole in the
feedback-transfer function. Resistor R17
determines the AGC-release time.
To secure good response to high-frequency-signal components, use either
Schottky or fast PN silicon diodes for
D1 and D2. The dc-coupled complementary cascade comprising Q2 and Q3
supplies most of the circuits voltage
gain. A 1-k resistor, R14, isolates Q4,
the output-emitter follower, from the
signal-output terminal. If necessary, you
can use a lower resistance at R14, but a
large-capacitance connecting cable
can provoke Q4 into parasitic oscillation if R14 is too low.
Figure 4 shows the circuits inputversus-output characteristics as measured with a sine-wave signal. The effective AGC range extends from 100-Vto 100-mV-rms input voltage, a 60-dB
dynamic range. Output voltage varies
less than 2 dB over this input range,
reaching a nominal level of 775 mV
rms at a 20-dB- (100-V-rms) input
level. The inputs 0-dB point is set arbitrarily at 1-mV-rms input, which corresponds to an 803-mV-rms output.
The AGC attack time for a sinusoidalinput-signal step from 0 to 100 mV rms
is approximately 0.3 sec, and the AGC
10
60
40
20
0
20
40
60
1.8 dB
10
60 dB
OUTPUT
VOLTAGE
(dB) 20
VIN = 1 mVRMS
VOUT = 850 mVRMS
30
5
4
3 THD k
2 FACTOR
1
(%)
0
NOISE LEVEL
40
40
20
20
40
designideas
Precision active load operates as low as 2V
By Joel Setton, Crolles, France
R7
1k
R8
10k
Q4
2N5087
Q3
2N5087
VS
1.2V
R1
100k
1%
IC1A
LM10
+
R2
20k
1%
R9
CONTROL
12k INPUT (1A PER
VOLT WITH P1
FULLY CW)
R11
7k
1%
R4
68k
Q1
2N5087
R6
5.6k
R10
10M
C1
100 nF
REFERENCE
1 Toffoli, Tommaso, Self-powered
dummy load checks out multiple
power supplies, Electronic Design,
April 17, 2000, pg 118.
R12
115k
1%
Q6
2N6053
R14
900k
1%
A
P1
5k
10 TURNS
S1
CURRENT
CONTROL
C3
10 F
10V
R25
10
R22
22k
IC1B
2 _LM10
E
R17
1k
R16
22k
Q8
2N6053
Q7
BC237
Q5
BC237
R13
95k
1%
1
R3
15k
R15
95k
1%
C2
10 F
100V
Q2
BC237
R5
220k
8 _
R23
10
R19
270
R20
100
R21
2.2k
R24
0.12
5W
Figure 1 This versatile precision load circuit draws constant current or emulates an adjustable power resistor.
LOAD
TERMINALS
R26
0.12
5W
designideas
Squeeze extra outputs
from a pin-limited microcontroller
Abel Raynus, Armatron International Inc, Malden, MA
Many of todays designs use lowcost microcontrollers from Freescale and Microchip, but during the last
decade, device packages have resorted
to ever-smaller footprints featuring as
few as eight or even six pins. Although
these packages minimize pc-board
area, they also reduce the number of
available I/O pins and pose problems
for designers who need to add one more
function without migrating to a device
that occupies a larger package.
To overcome a shortage of inputs, a
designer can increase a small microcontrollers inputs by writing a program
MC68HC908QT1
5V
74HC595
5V
16
PA0
IC1
PA1
PA4
7 SD
14
6 CLK
11
3 EN
12
IC2
10
LED0
LED1
Q2 2
LATCH
5V
Q0 15
Q1 1
SERIALDATA INPUT
SHIFT
CLOCK
RESET
13 OUTPUT
ENABLE
LED2
Q3 3
Q4 4
LED3
Q5 5
Q6 6
LED5
LED4
LED6
Q7
LED7
Figure 1 Do you need more outputs? You can emulate an SPI in software to
add a shift register to a pin-limited microcontroller.
MSB
1
LSB
0
DATA
TIME
CLK
TIME
SHIFTREGISTER
OUTPUTS
Q7
Q6
Q5
Q4
Q3
Q2
Q1
Q0
Figure 2 The sample timing diagram illustrates the loading of $F0 byte into
an external shift register.
designideas
READERS SOLVE DESIGN PROBLEMS
Build a precise dc
floating-current source
D Is Inside
84 Frequency dithering
enhances high-performance
ADCs
IIN
Z1
VREF
IC1
IIN
R1
IC1
Z4
_
+
Z5
R3
Z3
IC2
R2
Z2
88 Voltage reference is
software-programmable
VIN
86 Memory-termination IC
balances charges on series
capacitors
R4
IO
R5
IO
IC2
VREF
designideas
large values for R1, R2, and R3 helps
minimize current drawn from the reference voltage. For example, the circuit
can supply 2 to 10 mA to R4 and draw
only a few tenths of a microampere from
the reference source. Using tight-tolerance and low-drift components for VREF
and R5 ensures the stability of IO. Applications include providing constant-current drive for Wheatstone-bridge and
2
Ramrez, Diego, S Casans, and
C Reig, Current loop generated from
a generalized impedance converter: a
new sensor signal conditioning circuit,
Review of Scientific Instruments, Volume 76, No. 1, January 2005.
3
Anderson, KF, Looking under the
(Wheatstone) bridge, Sensors, June
2001, pg 105.
C1
0.01 F
C2
10 F
18V
R5
3.3k
R1
33k
R2
1k
C2
10 F
+
5V
C5
0.22 F
5V
5V
C3
0.22 F
R3
100k
8
IC1A
LT14133 + CN8
4
R7
10k
R4
100k
1
V+
2 _
C4
1 F
+
D1
12V
C1
0.01 F
R1
33k
R2
1k
6 _
IC
1B
LT14135 CN8
+
OUT
IC2
LTC1799
2
FREQUENCYDITHERED OUTPUT
5V P-P
GND
7
R6
1M
SET
DIV
Figure 1 A zener diode, two stages of amplification, and an FM voltage-controlled oscillator form a constant-amplitude dither
generator.
designideas
ital shift registers and semiconcan select amplification-stage
10 MHz
ductor junctions biased into the
gains such that clipping of
breakdown range. In this
noise peaks isnt evident at the
design, a 12V zener diode, D1,
circuits output. If your appligenerates the noise, which a
cation requires it, you can alter
two-stage amplifier amplifies
the amplifiers frequency reand frequency-shapes. If necessponses to alter the noise specsary, you can further shape the
trum. Finally, adjust the LTCnoise distribution by using 10 dB/DIV
1799s frequency-setting resismore complex active-filter sectors, R6 and R7, so that the
100 kHz/DIV
noise-spectrum display resemtions, IC1A and IC1B. After filtering, the noise modulates the Figure 2 The broad bell-shaped curve shows a ranbles that in Figure 2. Any clipLTC1799. Make sure that the dom-frequency-dithered spectrum superimposed onto
ping along the amplifier path
LTC1799s power-supply volt- the LTC1799s unmodulated, 10-MHz output.
tends to add peaks to the edges
age is pure dc and free of ripple,
of the spectrum, which indibecause power-supply noise
cates amplitude clipping and
produces nonrandom AM sidebands.
their noise outputs can vary greatly. reduction of the noises random charFigure 2 shows an amplitude-versus- Even among diodes from the same acteristics.
frequency plot of the frequency-limit- manufacturing batch, you can observe
You can add a filter between the
ed spectrum that the design in Figure popcorn noise, unevenly distributed noise output and the A/D converters
1 produces. Depending on the circuits noise histograms, amplitude shifts, and summing input to limit inband noise
configuration, you can apply the dither frequency-weighted noise. In a high- or remove any periodic modulation
to the A/D converter using a small cou- volume application, well-specified that power-supply ripple introduces.
pling capacitor or a more complex noise diodes, such as those from Micro- In a modern, high-performance A/D
active summing circuit. Although netics (www.micronetics.com), may converter, even a small amount of
zener-diode noise generators offer the- prove more cost-effective than zener periodic noise can manifest itself as
oretical simplicity, they behave poorly diodes.
a 80-dBc (decibels-below-carrier)
in production environments because
Once you select a noise diode, you spurious response.EDN
As one of todays most interesting component families, highvalue capacitors offer ratings ranging
from tenths to tens of farads but suffer
from relatively low working voltages.
For example, Maxwells (www.maxwell.
com) PC10 ultracapacitor occupies an
area about the size of a large postage
stamp and the thickness of four
stacked US 25-cent coins. The PC10
provides 10F capacitance, a 2.5A maximum discharge-current rating, and an
18 ESR (equivalent-series resistance). However, its rated working voltage is only 2.5V.
To accommodate a supply voltage
greater than 2.5V, you can connect two
capacitors in series, halving the available capacitance and doubling the
overall voltage rating. However, due to
SUPPLY RAIL
IC1
LP2996
+ C
1
VDDQ
AVIN
10F
VSENSE
VTT
PVIN
SD
GND
+ C
2
10F
designideas
identical, and the loop equatwo. The LP2996 includes
tion, including the supply
thermal-shutdown protecvoltage, becomes: VSUPPLY=
tion, but an instantaneous
VC1(0)VC2(0)(C1C2)/
short circuit across either
(C1C2)I(t)dt. During
capacitor may occur too
charging to a 5V-supply
quickly to activate the prolevel, differences in tolertection circuitry.
ances between C1 and C2 or
Thermal considerations
residual voltages on either
determine the capacitors
capacitor cause the voltage
maximum current-handling
across one capacitors tercapability, and the PC10s
minals to exceed 2.5V and
data sheet derates the current
cause the other to fall below
downward from 2.5A. You
2.5V.
can connect 1 current-limTo overcome this undesiriting resistors in series with
able mismatch, the LP2996
both capacitors if the power
Figure 2 The oscilloscope waveforms within the active-balDDR termination regulator,
supply provides charging
ance circuit show the power-supply rail voltage (top trace),
IC1, sinks or sources current
current in excess of 2A.
the midpoint voltage at the junction between the two capacifrom both capacitors and
Upon interruption of the
tors (middle trace), and the charge/discharge current (lower
actively maintains their voltpower supplied to the cirtrace, scaled to 1A per division). The traces reflect a 1A
ages at one-half of the supply
cuit, the LP2996 imposes a
charge interval to 5V, followed by a 1A discharge to 0V. The
voltage (Figure 1). The LPself-discharge current of
waveform steps at the start of the charge and discharge
2996 provides an active terless than 1 mA, which repintervals are due to the capacitors internal ESRs.
mination for DDR-SDRAM
resents a capacitor-batdevices and can sink or
tery discharge rate of 5000
source large amounts of cursec per volt into an open
rent; its data sheets nomenclature and waveforms for 1A current steps.
circuit. You can reduce the LP2996s
This active balancing circuit does self-discharge current by applying an
labels reflect its intended memory-support role. The LP2996s Class B output, impose some limitations. Using a external control signal to its shutdown
VTT, drives the capacitors common power supply rated at 5V and 1A, the input. Upon power interruption, the
connection, actively maintaining the two capacitors achieve charge balance two-capacitor string can supply a conjunction at VDDQ/2 and becoming in a maximum of 25 sec: Charge stant-current load of 1A for 15 sec over
active only when the capacitors get out time5F5V/1A. The initial charging a voltage change from 5 to 2V. You can
of balance. At balance, the LP2996 interval overcomes any initial prebias connect additional pairs of capacitors
wastes no charging current and thus charge on either C1 or C2. The steady- in parallel to provide additional curoperates efficiently. The devices data state current flow into and out of the rent, but, depending on capacitance
sheet specifies that the LP2996s out-of- LP2996 amounts to a fraction of the mismatches, initial bias voltages, and
balance error amounts to a VTT offset of high current flowing through the current demand, you may need addi20 mV around the VDDQ/2 setpoint. capacitors and is just sufficient to over- tional LP2996s to maintain charge
Figure 2 shows charge and discharge come any tolerance mismatch in the balance.EDN
For a variety of reasons, designers often discover that their creations need yet more power-supply
voltages. For example, a system powered
by 2.5V power supplies suddenly
needs a precision 1.4V reference for
a signal-level-shifting circuit and needs
a 2.1V reference to drive an ADC. Your
options include adding a couple of oper-
ational amplifiers and resistors to levelshift and buffer the systems voltage reference or adding a couple of DACs. Opamp circuits lack programmability to
accommodate design changes, and,
although the DACs offer programmability, their settings are volatile, and the
outputs are typically unipolar and lacking in drive capability.
designideas
input. Both inputs connect
voltages after a power
to ground, and the first
interruption, and a parity
2.5V
2.5V
1
8
+
term is thus close to 0V, or
bit can indicate a mal+
VCC
VEE
10 V maximum due to
function if an internal
7
2
input-amplifier errors, and
device failure accidentally
FILTER
FILTER
VOUT
IC1
the circuits output voltage,
causes the programmed
AD8555
6
3
DATA
VCLAMP
VOUT, is equal to VDAC.
voltage to change.
+
10k
Until you permanently
The programmable volt4
5
DATA
IN
+IN
program the internal regisage reference comprises
ters, they allow you to alter
IC1, an Analog Devices
AD8555 high-precision
the output voltage and
auto-zero instrumentation
explore the circuits beamplifier, which contains
havior as a fixed-voltage
an 8-bit DAC as part of its Figure 1 Occupying a tiny, eight-lead LFCSP footprint, a proreference and reprogramoffset-adjustment circuit. grammable instrumentation amplifier doubles as a last-minute
mable 8-bit DAC. To proIn a change from its adjustable-voltage bipolar-reference source.
gram the output voltage,
intended role, the monoyou apply the appropriate
tonic DAC generates the
pattern according to the
output voltage, which can swing from DACs approximate internal reference first equation and instructions from the
VSS (input code 0) to VDD1 LSB voltage, VDAC:
devices data sheet. After verification,
(input code 255). The DACs 8-bit resyou can permanently set the output
olution provides voltage steps of 0.39%
voltage by blowing certain of the
of the difference between VDD and
devices internal polysilicon-fuse resisVSSfor example, steps of 19.5 mV and the following equation yields the tors. As Figure 2 shows, for a given outwith a 5V supply. The output-voltage, circuits output voltage, VOUT: VOUT put-voltage level, the devices absolute
VDAC, temperature coefficient is less GAIN(VPOSVNEG)VDAC, in which error is less than 0.4% across a 40 to
than 15 ppm/ C.
GAIN represents the circuits default 140 C temperature range.EDN
The following equation describes the internal gain of 70 for the differential
0.50
0.40
0.30
0.20
0.10
0.00
ERROR
(%)
0.10
0.20
0.30
0.40
VOUT(ACTUAL)VOUT(CALCULATED)
5V FULL-SCALE
40 C
25 C
25
5
23
2
20
0
16
8
13
6
10
4
72
40
14
2
14
0
13
8
13
6
13
4
13
2
13
0
12
8
0.50
125 C
Figure 2 Output-voltage error for the reference circuit reaches a maximum of 0.4% at a temperature of 40 C and a 5V
power supply.
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
82 1-Hz to 100-MHz VFC features
160-dB dynamic range
Rectifier circuits based on semiconductor diodes typically handle voltage levels that greatly exceed
the diodes forward-voltage drops,
which generally dont affect the accuracy of the rectification process. However, the rectified signals accuracy suffers when the diodes voltage drop ex-
R3
2k
R4
2k
R2
1k
VIN
2 _
6 _
V
IC1A OUT
3 +
R5
1k
VCC
VCC
R1
1k
IC1B OUT
1
LMC6482AIN
4 V
VOUT
LMC6482AIN
4 V
VHALF
Figure 2 From bottom to top, the waveforms show VIN (CH1), VHALF (CH2), and
VOUT (CH3).
ceeds the applied voltage. Precision rectifier circuits combine diodes and operational amplifiers to eliminate the
effects of diode voltage drops and
enable high-accuracy, small-signal rectification. By taking advantage of modern operational amplifiers that can handle rail-to-rail inputs and outputs, the
circuit in Figure 1 dispenses with
diodes altogether, provides full-wave
rectification, and operates from a single power supply.
The circuit operates as follows: If
VIN0V, then IC1As output, VHALF,
equals VIN/2, and IC1B operates as a subtracter, delivering an output voltage,
VOUT, equals VIN. In effect, the circuit
operates as a unity-gain follower. If
VIN0V, then VHALF0V, and the circuit behaves as a unity-gain inverter
and delivers an output of VOUTVIN.
Figure 2 shows the circuits input signal at VIN; its intermediate voltage,
VHALF; and its output voltage, VOUT.
The circuit uses a single National
Semiconductor LMC6482 chip and
operates in the linear regions of both
operational amplifiers. Suggested applications include low-cost rectification
for automatic gain control, signal
demodulation, and process instrumentation. The circuit relies on only one
device-dependent property: The amplifiers must not introduce phase inversion when the input voltage exceeds
the negative power supply; the LMC6482 meets this requirement.EDN
designideas
1-Hz to 100-MHz VFC features
160-dB dynamic range
Jim Williams, Linear Technology Corp
gain/temperature coefficient, a 1Hz/C zero-point shift, and a 0.1% frequency shift for a 10% power-supplyvoltage variation. A single 5V supply
powers the circuit.
Chopper-stabilized amplifier IC1, an
LTC-1150, controls a crude but widerange oscillator core comprising bipolar transistors Q1 and Q2 and inverters
IC2A and IC2B. In addition to delivering a logic-level output, the oscillator
core clocks divide-by-four counter IC3,
5V
R3
120
R4
120
R2
12k
R1
7.5k
Q1
2N3906
D1
FOUT
1 Hz TO 100 MHz
OSCILLATOR
CORE
Q2
C2
2N3904
0.1 F NC
5V
D1
IC2A
C1
20 pF
IC2B
74AHC14
CLK1
D2
74AHC14
VBIAS
3V DC
GENERATOR
R16
D3
D2
510k
SERVO
AMPLIFIER
C10 +
10 F
C9
10 F
P1 CLR1
IC3
74AHC74 CLK2
Q2
P2 CLR2
Q1
5V
R14
2k
R13
510k
5V
R15
33
CLK
IC1
LTC1150_
R10
10k
R12
20
R9
2k
LINEARITY
(60 MHz)
VIN
0 TO 5V
Q4
12
R8
6.19k
IC4
74HC4060
CLR
FEEDBACK
DIVIDER
CHARGE
PUMP
SUMMING
NODE
R11
10k
C8
1 F
IC5
LTC6943
C4
100 pF
11
4
R5
100
C7
C5
0.22 F 100 pF
100 MHz
R7
1k
14
15
13
C6
1 F
IC6
LT1460
2.5V
5V
R6
1.5k
NOTES:
1. D1: JPAD-500, D2, D3: BAT-85, R5, R6, R8: TRW-IRC TYPE MAR-6, 1% METAL-FILM, C4, C5: WIMA TYPE FKP-2 CAPACITORS,
AND C7, C8: WIMA TYPE MKS-2 CAPACITORS.
2. CONNECT ALL COMPONENTS AT Q1'S COLLECTOR WITH A MINIMUM-AREA AIR-INSULATED "FLOATING" JUNCTION
OVER A RELIEVED AREA OF GROUND TO MINIMIZE STRAY CAPACITANCE.
3. ENCLOSE R11 AND ITS CONNECTIONS TO R9, R10, IC1'S INVERTING INPUT, C7, AND PINS 5 AND 12 OF IC5 WITHIN SOLDER- AND
COMPONENT-SIDE GUARD TRACES TO INTERCEPT ANY BOARD-SURFACE LEAKAGE CURRENTS.
(NOTE THAT THE DASHED LINE DEFINES THE GUARD TRACE.)
4. CONNECT IC2'S UNUSED INPUTS TO GROUND. THE SCHEMATIC OMITS POWER-SUPPLY CONNECTIONS TO MOST ICS FOR CLARITY
Figure 1 Featuring a 160-dB dynamic range corresponding to a 1-Hz- to 100-MHz-frequency span, this voltage-to-frequency converter operates from a single 5V power supply.
designideas
The circuits extraordinary dynamic
range and high speed derive from the
oscillator cores characteristics, the
divider/charge-pump-based feedback
loop, and ICls low dc input errors. Both
IC1 and IC5 help stabilize the circuits
operating point by contributing to
overall linearity and stability. In addition, ICls low offset drift ensures the
circuits 50-nV/Hz gain-versus-frequency characteristic slope and permits
operation as low as 1 Hz at 25C.
Applying a positive input voltage
causes IC1s output to go negative and
alter Q1s bias. In turn, Q1s collector
current produces a voltage ramp on C1
(upper trace in Figure 2). The ramps
amplitude increases until Schmitt trigger inverter IC2As output (lower trace
in Figure 2) goes low, discharging
C1 through Q2 (connected as a lowleakage diode). Discharging C1 resets
IC1As output to its high state, and the
ramp-and-reset action continues.
The leakage current of diode D1, a
Linear Systems JPAD-500, dominates
all other parasitic currents in the oscillator core, but its 500-pA maximum
leakage ensures operation as low as 1
Hz. The two sections of charge pump
IC5 operate out of phase and transfer
charge at each clock transition. Components critical to the charge pumps
stability include a 2.5V LT-1460 voltage reference, IC6; two Wima FKP-2
polypropylene film/foils; 100-pF capacitors, C4 and C5; and the low chargeinjection characteristics of IC5s internal switches.
The 0.22-F capacitor, C7, averages
the difference signal between the inputderived current and the charge pumps
output and applies the smoothed dc signal to amplifier IC1, which in turn controls the bias applied to Q1 and thus the
circuits operating point. As noted, the
circuits closed-loop-servo action reduces the oscillators drift and enhances
its high linearity. A 1-F Wima MKS2 metallized-film-construction capacitor, C8, compensates the servo loops
frequency response and ensures stability. Figure 3 illustrates the loops wellbehaved response (lower trace) to an
input-voltage step (upper trace).
1V/DIV
(AC COUPLED)
2V/DIV
5 nSEC/DIV
2V/DIV
(ON 0.05 VDC)
1V/DIV
10 mSEC/DIV
designideas
cuits input to the charge pumps output allows for correction of small nonlinearities due to residual charge injection. This input-derived correction is
effective because the charge injections
effects vary directly with the oscillation
frequency, which the input voltage
determines.
Although you can use the component values given in Figure 1 to assem-
the input and adjust the 100-MHz trimmer, R7 for a 100-MHz output. Next,
connect the input to ground and adjust
trimmer R13 for a 1-Hz output. Allow
for an extended settling interval
because, at this frequency, the chargepump update occurs once every 32 sec.
Note that R13s adjustment range
accommodates either a positive or a
negative offset voltage because IC1s
clock output generates a negative bias
voltage for R13. Next, apply 3V to the
input and adjust R9 for a 60-MHz output. A certain amount of interaction
occurs among the adjustments, so
repeat the process until you arrive at
optimum values for the three calibration frequencies.EDN
L1
IC1
TPS61040
D1
SW
VOUT
28V
Q1
VIN
6V
VCC
+
C
1
PEAK-CURRENTMODE CONTROL
FB
R1
CFF
RF1
RF2
Figure 1 Based on the barefoot TPS61040, this dc/dc boost converter delivers output voltages only within IC1s ratings.
designideas
common-gate, configuration.
Q2 comprises a low-on-resistance,
low-gate-voltage-threshold MOSFET
with the addition of diode D2 between
Q2s gate and source. To ensure the circuits proper operation, VCC5V in
this examplemust exceed Q2s gatethreshold turn-on voltage. In operation, IC1s internal control circuit turns
on Q1, which pulls Q2s source close to
ground level and turns on Q2 with
almost 5V of gate-to-source potential.
Current flows through inductor L1,
external transistor Q2, internal transistor Q1, and sense resistor R1, and
IC1s control circuit sees no difference
with the installation of Q2. Once the
inductor current reaches its preset
limit, Q1 turns off, leaving Q2 with no
path for current to flow from its source.
The voltage on Q2s drain rises rapidly
to the desired output voltage plus the
voltage drop across D1. As the drain
voltage rises, Q2s drain-to-source
capacitance attempts to pull the
MOSFETs floating source above 5V,
which forward-biases D2, connects
D1
ES1G
L1
V+
9V
C1
10 F
CERAMIC
47 H
CURRENT RATING >0.5A
HIGH-POTENTIAL RATING >200V
IC1
TPS61040
SI4464
SW
C4
+ 1 F
200V
CERAMIC
OR
ALUMINUM
Q2
D2
BAS21
VOUT
180V
4 mA
Q1
VCC
5V
VCC
C2
1 F
CERAMIC
PEAK-CURRENTMODE CONTROL
FB
R1
C3
22 pF
200V
R1
2.21M
200V
R2
15k
Figure 2 Adding an external cascode-connected MOSFET transistor, Q2, with higher breakdown-voltage ratings, enables
the circuit to produce higher output voltages.
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
90 Temperature controller has
take-back-half convergence
algorithm
94 MOSFET enhances
low-current measurements
using moving-coil meter
96 Shunt regulator serves
as inexpensive op amp
in power supplies
the approximately 1V-dc offset that Reference 1 requires. Transistors Q1 and Q2,
resistors R1 and R2, and LED D3 form an
emitter-follower amplifier for the ramp
voltage available at IC1, Pin 7 across
timing capacitor C1. This arrangement
provides reliable current-mode operation over the full range from no-load to
full-load output current by delivering a
R2
R1
4.7k
IC1
UCC3895
1
2
3
VDC(RAMP)
R1
C1
4
5
6
7
8
9
10
EAN
EAOUT
SS/DISB
RAMP
OUTA
REF
OUTB
GND
SYNC
2N3906
4
EAP 20
PGND
VCC
CT
OUTC
RT
OUTD
DELAB
CS
DELCD
ADS
Q2
19
D3
YELLOW
LED
18
17
Q1
15
C1
200 TO
820 pF
14
13
11
C3
2N3904
16
12
R2
1k
R3
C2
1000 pF
REF
RAMP
IC1
R3
511 UCC3895
12 CS
7
CT
R4
100
D1
1N4148
D1
CT1
SHOWN FOR 8
TO 10A
PRIMARY
CURRENT
T1
C2
R4
R5
R5
16
D2
1N4148
100-TO-1
designideas
sawtooth drive with a dc offset to IC1s
ramp input. Diode D3, a yellow LED,
performs a 1.7V level translation without introducing any substantial signal
loss. The component values not shown
depend on the application.EDN
REFERENCES
Mappus, S, UCC3895
OUTC/OUTD Asymmetric Duty Cycle
Operation, Texas Instruments Application Report, SLUA275, September
2002.
H = H + F(TST).
NEW HEATER
EQUILIBRIUM
+H
H
H PERTURBATION
THAT IS, SUDDEN
AMBIENT COOLING
OLD HEATER
EQUILIBRIUM
T = TS.
SETPOINT
CROSSINGS
T = TEMPERATURE.
designideas
the current (H) and previous (HO)
crossings. This action takes back half of
the adjustment applied to the heater
setting between crossings. Figure 2
shows how a simulated TBH algorithm
forces rapid half-cycle convergence.
Successful applications of the TBH
algorithm range from precision temperature control of miniaturized scientific instrumentation to managing
HVAC (heating/ventilation/air-conditioning) settings for crew rest areas in
Boeings 777 airliner. Experience with
TBH applications shows that, with a
reasonable choice for loop gain, F, the
algorithm exhibits robust stability.
In general, a TBH systems natural
cycle time is proportional to the square
root of the ratio of the thermal time
constant to F. Based on both simulations and experiments, a cycle time
thats at least eight times longer than
H
+H
HOH =
H + HO
.
2
H
HO
TS
Figure 2 In this simulation, applying the take-back-half algorithm forces convergence to the setpoint value in a single half-cycle.
J2-1
J2-2
THERM1
F1
J2-3
ACIN
R12
301k
J2-5
49.9k
7
2
PS2501-2
3 IC2B
NTC
THERMISTOR
HEATER
12V
SOLID STATE AC
RELAY 10A
AC
FEEDBACK
4
1N4148
12V
8
IC2A
RT1
LED
ACOUT LED
J2-4
120V
AC
IC3
CC1028-ND
C7
1k 0.001 F
LMC6484A
8 _
7
IC5B
5 +
40.2k
1k
X0
X0
5
X
1
R5
C3
X1 A
A X1
12V
2.67k
1 F
9
10
IC1C
IC1B 1%
IC1A
CD4053B
R4 CD4053B
CD4053
12
43.2k
X0
1%
X 14
13
R9
R6
X1 A
22.1k
43.2k
12V
11
1%
1%
4
C5
0.047 F
12V
12V
C8
0.1F
RSET
1%
12V
15 VCC
IC1D
8
GND CD40538
C9
0.1 F
7 VEE
THERM1
EN
6
C1
1 F
C2
1 F
C10
1 F
R1
1M
1%
R26
100k
1%
2 _
IC5A
3 +
R29
100k
1%
Q8
MMBT3904LT1
R12
10k
1%
C11
1 F
LMC6484A
R7
665k
C15
10 F
16V
LMC6484A
Q6
MMBT3904LT1
LMC6484A
13 _
IC5D
12 +
Q7
MMBT3904LT1
14
1
R2
100k
1%
R3
475k
1%
TBH INTEGRATOR
Figure 3 For safety, this version of a TBH heater controller features full isolation of the ac-line and control circuits.
IC
10 + 5C
R10
1M
1%
LMC6484A
4
_
IC5E
+
11
9 _
C4
0.1F
designideas
the heater-sensor time delay ensures
convergence. Therefore, setting loop
gain F low always achieves convergence, and the steady-state error,
TST, remains equal to zero.
Figure 3 shows a practical example
of a TBH controller thats suitable for
managing large thermal loads. Thermistor RT1 senses heater temperature.
The output of error-signal integrator
IC5A ramps negative when TTS and
ramps positive when TS T, producing
a control signal thats applied to comparator IC5C, which in turn drives a
solid-state relay, IC3, which is rated for
10A loads.
Comparator IC5D and the reverseparallel diodes formed by the collector-base junctions of Q6 and Q7, and
the CMOS switches of IC1 perform
the TBH zero-crossing convergence
function.
In most temperature-control circuits,
its advantageous to apply a reasonably
linear feedforward term that represents
the actual ac voltage applied to the
heater; the need for complete galvanic isolation between the control and
the power-handling circuits complicates this requirement. In this example,
a linear isolation circuit comprising
a PS2501-2 dual-LED/phototransistor
optoisolator (IC2A and IC2B) and opamp IC5B delivers feedback current to
C15 and IC5C thats proportional to the
averaged ac heater current. As a bonus,
the feedback circuit provides partial
instantaneous compensation for ac-line
voltage fluctuations.EDN
REFERENCES
Williams, Jim, Linear Applications
Handbook, Linear Technology, 1990.
2 Hybrid Digital-Analog Proportional-Integral Temperature Controller,
www.discovercircuits.com/C/
control3.htm.
1
tion to emitter current is generally negligible. However, is sometimes smaller. For example, the general-purpose
BC182, an NPN silicon transistor, has
a low-current of only 40 at room temperature. If you were to use a 15-mAfull-scale meter in the transistors collector, full-scale base current IB at minimum would amount to 0.375 mA.
OPERATINGSUPPLY
RANGE
0 TO 32V
RSENSE1
1
1
RS+
MEASURED
CURRENT
0 TO 100 mA
2
RS
V+
5V INSTRUMENT SUPPLY
5V
+
M1
METER
FULL-SCALE
15 mA
IC1
MAX4172
OUT
FULL-SCALE
=1V
R1
1k
3 +
IC2
2 MAX495
_
Q1
BSN254
6
G
4
GND
RSENSE2
66
designideas
BC182 with an N-channel MOSFET,
such as the BSN254 (Figure 1).
Because a MOSFET draws no gate current, its drain current, ID, equals its
source current, IS. When you select a
MOSFET for the circuit, note that the
devices gate-source threshold voltage
should be as low as possible. For example, the BSN254 has a room-temperature gate-source threshold-voltage
RSENSE1. In this application, 100 mA produces 0.1V across RSENSE1, and the voltage across R1 thus corresponds to 1V for
full-scale deflection of the meter.EDN
REFERENCE
Bilke, Kevin, Moving-coil meter
measures low-level currents, EDN,
March 3, 2005, pg 72, www.edn.
com/article/CA505070.
1
Developed as a three-terminal
shunt regulator, the popular and
multiple-sourced TL431 IC offers designers many intriguing possibilities
beyond its intended application. Internally, the TL431 comprises a precision
voltage reference, an operational amplifier, and a shunt transistor (Figure
1a). In a typical voltage-regulator application, adding two external resistors,
RA and RB, sets the shunt-regulated
output voltage at the lower end of load
resistor RS (Figure 1b).
In todays power-supply market, cost
reduction drives most designs, as evidenced by Asian manufacturers that
have resorted to shaving pennies off
their power-supply products by using
single-sided pc boards. This Design Idea
shows how a three-terminal shunt reg-
VIN
VIN
VOUT
RS
CATHODE VSHUNT
RA
IC1
TL431
VREF
RS
D1
VOUT
VOUT
RI
RA
+
_
RB
+
RB
ISOLATED
FROM
AC LINE
ANODE
(b)
CZ
PWM
REFERENCE
INPUT
CATHODE
RZ
CP
R2
IC1
TL431
VREF
VERR
OUTPUT
IC2
OPTO
(a)
R1
R3
ANODE
AC-LINE SIDE
(NONISOLATED
COMPONENTS)
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
96 Added components improve
switching-regulator stability
R8
1k
R5
390
+ C
3
47 F
R10
100k
IC1
7 LMC7211AI
2 _
6
3 +
4
R9
1k
IC2
7 LMC7211AI
2 _
+C
6
R28
4
+
1k
47 F 3
4
R12
3.3M
R13
2.2k
R14
3.3M
R29
2.2k
R19
10k
0.5%
R20
10k
0.5%
R21
10k
0.5%
R32
10k
0.5%
13
14
15
25
26
27
16
17
18
28
29
30
19
20
21
31
32
33
KEYPAD
12
SECTION 1
22
23
SECTION 2
D1
1N4148
24
34
35
R4
47k
C1
100 nF
R7
4.99k
0.5%
8 4
VCC R
+ C5
3
Q
TR
7
DIS
5
6
CV
THR
GND
1
IC4
LMC555
R16
10k
0.5%
2
D2
1N4148
R6
100k
4.7 F TO MICROCONTROLLER
EXTERNAL
INTERRUPT
PIN
R24
10k
0.5%
11
R3
47k
C9
10 nF
R31
10k
0.5%
10
C6
1nF
R1 R2
47k 47k
D3
1N4148
R17
10k
R15
10k
C8
1 F
R18
10k
0.5%
C10
1 F
C2
1nF
C7
1nF
R30
3.3M
R11
2.2k
IC3
7 LMC7211AI
2 _
+C
6
12
47 F 3 +
4
36
R25
30k
0.5%
C11
10 nF
1%
R26
30k
0.5%
R27
30k
0.5%
SECTION 3
Figure 1 A keyboard encoder uses multiple variable-width pulses to communicate keys addresses to a microcontroller using a single-wire interface.
designideas
resides in section 1, 2, or 3, respectively. The microcontroller identifies the
pressed key by measuring the width of
the first pulse and identifies the keypad
section by counting the number of
pulses. Implementing the multiplepulse-encoding scheme requires no
additional active components. Pressing
a key in Section 1 generates a single
pulse. Pressing a key in Section 2 causes comparator IC2s output to go low
and triggers IC4 to generate the first
pulse. At the same time, R15 and C8
apply IC2s output transition to comparator IC1s input. As IC2s output, Pin
6, goes low, C3 starts to charge, and,
after a delay of about 2 msec, IC1 triggers IC4 to generate the required second
pulse. Because the time-constant prod-
VIN
C1
R1
VIN
RON
L1
VOUT1
SW
C3
VCC
C2
D1
IC1
BST
LM5007/8
C4
VOUT2
FB
RCL
R4
GND
R2
R5
R3
C5
Figure 1 This basic switched-mode voltage regulator reduces its input voltage to a lower value.
designideas
and increase the circuits immunity to
added load capacitance. The regulators
feedback voltage derives from VOUT1,
and C4 reduces output-ripple losses in
the feedback divider, R4 and R3. Unfortunately, this frequently used design
introduces new problems: As output
current increases, VOUT2 falls below
VOUT1 and degrades load-voltage regulation. Second, R5 carries full load current and dissipates power, reducing
overall efficiency. Using a large, highwattage fractional-ohm resistor at R5
increases product cost and regulatorpackage dimensions.
Figure 2 shows a rearranged buckmode-switching regulator with two
additional components. Assume that
C5s ESR is negligible and that R6 is
open. Now, R5 remains inside the feedback loop, and C4 couples voltage ripple from the inductor side of R5 to feedback. This action stabilizes the regulators operation and requires almost no
output-ripple voltage, and R5 introduces
only a small reduction in efficiency.
Taking dc feedback at the load preserves
the circuits excellent load regulation.
In another scenario, suppose that you
replace R5 with a short circuit and
select values for R6 and C4 that provide
the desired amount of ripple voltage at
the feedback pin. This configuration
produces almost no output-voltage ripple and eliminates R5s power losses.
Load regulation suffers because, as load
current increases, inductor L1s ESR
introduces voltage droop at VOUT1 and
forces the voltage at switching node
SW slightly higher. However, designers
can select L1 for a low ESR that minimizes its effects on load regulation and
can make R6s resistance larger than
that of R4.
The following examples compare
output ripple, circuit losses, and component count for the design scenarios.
Assume that input voltage is 50V, out-
VIN
VIN
C1
R1
VIN
RON
L1
C3
VCC
IC1
BST
LM5007/8
RCL
FB
C2
R5
VOUT
SW
D1
R6
C4
R4
GND
R3
R2
C5
Figure 2 Adding two components, R6 and C4, helps reduce output-ripple voltage and improve output-voltage regulation.
Figure
1
1
1
1
2
2
R5
()
0.25
0.125
0.25
0.125
0.125
0
R6
()
0
0
0
0
0
30k
C4
(nF)
0
6.6
0
6.6
6.6
6.6
VOUT,
R6
(mV)
100
50
6
6
6
6
Voltage
droop
(mV)
0
0
100
50
0
7
Power
dissipation
(mW)
0
0
40
20
20
0
Issues
Load capacitance and stability
Load capacitance and stability
Voltage droop and power dissipation
Power dissipation
Power dissipation
Voltage droop
designideas
where R4||R3 represents the value of
the parallel combination of R4 and R3.
In the second scenario, VOUT2 droops
to 100 mV at full load but exhibits only
6 mV of ripple without C4 in the circuit. Losses in R5 amount to 40 mW.
Adding C4 delivers 50 mV of ripple to
the feedback pin and VOUT1; setting R5
to 0.125 reduces R5s power loss to 20
mW. In the third scenario, R6 is an
open circuit, and the design in Figure
2 requires an R5 value of 0.125 to provide 50-mV ripple at FB. VOUT1 exhibits
no voltage droop at full load current
and has only 6 mV of ripple voltage.
R5s power loss is 20 mW.
In the fourth case, a short circuit
replaces R5, and the design in Figure 2
requires a value for R6 that increases the
voltage across C4 to provide 50 mV of
ripple voltage at FB. Use the following
equations to calculate the value:
RS
9950
VIN
0 TO 10V DC
RCOIL
+
+
_
M1
0 TO 1 mA,
0 TO 50 mV
FULL-SCALE
designideas
ly exceeds that of RCOIL and therefore
significantly reduces the electromagnetic damping action on the meter
movement. Although you can improve
damping by shunting the meter with a
capacitor, this approach also increases
the meters settling time.
Figure 2 illustrates a better approach,
in which a moving-coil meter connects
to the output of an operational amplifier, IC1, embedded in a deep negativevoltage-feedback loop. Because the op
amp presents an extremely low equivalent output resistance, the meters terminals are virtually shorted, providing effective electromechanical damping that results in more stable readings
and increased shock and vibration
resistance. In Figure 2, the resistive
voltage divider comprising R1 and R2
connected to the op amps noninverting input determines the meters fullscale reading. You can add RF and CF to
form an optional highpass filter to further improve the meters settling time.
Transistors Q1 and Q2 are also optional and added as overvoltage protection.
Note that, for normal operation, the
transistors forward base-emitter voltage, VBE, should be several times larger than the meters full-scale voltage,
VFS, which is typically 50 to 100 mV.
A rail-to-rail-capable, single-supply
micropower op amp makes a good
choice for this application. If the input
voltage, VIN, exceeds the op amps minimum power-supply-voltage requirement, you can connect the op amps
VCC pin directly to the input terminal,
as the dashed line in Figure 2 shows.
In effect, the circuit combines the
advantages of meter buffering and
improved shock and vibration resistance with a traditional moving-coil
meters advantage of requiring no
external power supply. You can choose
from among many commercially
available off-the-shelf, rail-to-rail output-micropower op amps that draw
supply currents well below the fullscale current drain, IFS, of typical
moving-coil meters. For example,
Maxims MAX4289 requires as little as
1V and 9 A of power, and the
MAX4470 requires a minimum of
VCC
R1
VIN
DC
+
IC1
CF
RF
RCOIL
M1
ANALOG
METER
Q2
Q1
R2
Figure 2 An operational amplifiers low output resistance provides electromechanical damping for a moving-coil meter for stable readings and
enhanced resistance to mechanical shock and vibration. Connect VCC to
either an external power supply or the circuits input terminal if VIN exceeds
IC1s minimum power-supply-voltage rating.
VCC+
R4
100k
+
IC2
R1
+
VIN
AC OR
DC _
R3
200k
R5
300k
RCOIL
IC1
+
R2
Q2
Q1
M1
ANALOG
METER
Figure 3 Based on rail-to-rail operational amplifier IC1, this circuits input stage
forms a diodeless, precision full-wave rectifier and enables the circuit of Figure
2 to display ac- or dc-voltage measurements on a dc meter.
designideas
READERS SOLVE DESIGN PROBLEMS
example, the LM5020s internal oscillator delivers a regulated 2V at its programming pin (RT), and a programming resistor connected to RT sets the
current that RT delivers. The oscillator also delivers a proportional current
into an internal timing capacitor
(Reference 1). The period of the timing capacitors ramping voltage determines the oscillators frequency.
The external dithering circuit in Figure 1 comprises a simple stand-alone
comparator-based oscillator configured to operate at approximately 800
Hz. The output state of comparator IC2
goes high upon power-up. R1, R2, and
R3 set the comparators positive input,
which initially rests at 2.9V. The voltage at capacitor C3 ramps up toward the
positive threshold.
When the voltage at the comparators negative input reaches the positive-threshold voltage, the comparators output switches low, which also
R1
100k
5V REF
R2
280k
3
R3
100k
C1
0.1 F
IC2
LMC7215
4 _
R4
17.8k
C2
1 F
IC1
LM5020
R5
64.9k
RT
C3
0.1 F
RT
16.5k
V
D Is Inside
100 Single-port pin drives
dual LED
102 Network linearizes dc/dc
converters current-limit
characteristics
104 Add a Schmitt-trigger function to CPLDs, FPGAs, and
applications
What are your design problems
and solutions? Publish them here
and receive $150! Send your
Design Ideas to edndesignideas@
reedbusiness.com.
lowers the threshold at the comparators positive input to 2.1V. The voltage at capacitor C3 then ramps down
toward the new threshold, and, when
it reaches the lower threshold voltage,
the cycle repeats. The voltage across C3
approximates a triangular wave with a
minimum voltage of 2.1V and a maximum of 2.9V.
To dither the LM5020 controllers
PWM-oscillator base frequency, the triangular wave generated by IC2 modulates the current from the controllers
RT pin. Resistor R5 sets the percentage
of modulation dither. The right side of
R5 is fixed at the RT pins regulated
potential of 2V, and the low-frequency
triangle wave coupled from IC2
through capacitor C2 drives R5s left
side. For R5 with a value of 64.9 k, the
peak-to-peak current through resistor
R5 is approximately 12 A. With the
dither circuit disconnected, the steadystate current that RT sources is approximately 121 A, and the 12-A p-p
dither current thus represents 10% total
modulation.
An LM5020-controlled PWM flyback dc/dc converter, IC1, evaluates the
dither circuits effectiveness. The circuits fundamental operating frequency
is 250 kHz, which the controllers RT
designideas
0
CONDUCTED
EMI
(dB)
40
80
130
180
230
280
FREQUENCY (kHz)
330
380
REFERENCE
1 LM5020 data sheet, National
Semiconductor, www.national.com/
pf/LM/LM5020.html#Datasheet.
IC1
FROM
MICROCONTROLLER
PORT
R5
D1
designideas
VCC
5V
VCC
3V
R1
47k
R2=
R3
D3
FROM
MICROCONTROLLER
PORT
D5
D4
>VCC/2
3V
FROM
MICROCONTROLLER
PORT
Q1
BC547
R4
regardless of whether the microcontrollers port pin goes high or low. VCC
may vary during operation but must
remain higher than 3V.
You can individually adjust the LEDs
currents to equalize brightness or compensate for a difference between the
microcontrollers power-supply voltage
PORT
R2
LEDs
L
RED ON
H
GREEN ON
Z (INPUT) BOTH OFF
D1
>VCC/2
3V
D2
BAS15
Q2
BSS101
VCC
R1
100k
THERMISTOR
100k, 25C
John Guy and Lance Yang, Maxim Integrated Products Inc, Sunnyvale, CA
Recently announced versions
of integrated step-down dc/dc
converters have eliminated the requirement for a high-side current-sense
resistor by sampling the voltage drop
across an external, low-side, MOSFET
synchronous rectifier. This topology
eliminates the sense resistors cost and
pc-board-space requirement and also
provides a modest increase in circuit
efficiency. However, the MOSFETs
highly temperature-dependent onresistance dominates the currentlimit value. Fortunately, certain newer
dc/dc converters, such as Maxims
MAX1714, allow external adjustment
of the current-limit threshold. The circuit in Figure 1 shows how a thermistor applies temperature compensation
to the circuits output-current limit.
The MAX1714s linear currentlimit (ILIM) input range at Pin 6 of IC1
spans 0.5 to 2V, which corresponds to
current-limit thresholds of 50 to 200
mV, respectively. For the default current-limit setting, 100 mV, the circuit
imposes a 7.5A current limit at 25C.
However, Figure 2 shows that the current limit varies from 9A at 40C
to 6A at 85C. To design the temperature-compensation network, begin by
breadboarding the circuit and using an
R2
69.8k
6 ILIM
R3
110k
IC1
MAX1714
designideas
12
WITHOUT THERMISTOR
rating the original current10
limit-voltage-versus-temperature data and added
8
columns for each of the net6
works resistors, plus the
OUTPUTWITH THERMISTOR
CURRENT
thermistor specification
LIMIT (A)
4
sheets resistance-versustemperature data. While
2
observing the circuits tem0
perature-versus-voltage
40 15
10
35
60
85
transfer function, we varied
TEMPERATURE (C)
the spreadsheets values for
R2 and R3 until the transfer
Figure 2 Before (black trace) and after (red
function best approxitrace) current-limit-versus-temperature characmated the measured curteristics show the performance enhancement
rent-limit-voltage-versusthat the circuit in Figure 1 provides.
temperature data. Finally,
we constructed the circuit
and tested it over the temperature design goal. You can achieve more prerange and noted that it yielded a rea- cise compensation by selecting a difsonably flat response.
ferent thermistor or by incorporating
The curvature of the corrected out- multiple thermistors.EDN
put characteristic of Figure 2 (red
trace) is intrinsic to the thermistor. R E F E R E N C E
Though not perfectly flat, the correct- 1 Horowitz, Paul and Winfield Hill,
ed curve represents a great improve- The Art of Electronics, ISBN 0 521
ment over the original (black trace) 37095 7, Cambridge University Press,
and is sufficient to meet the original New York, 1980.
IN
OUT
(a)
R2
CPLD
R1
IN
OUT
(b)
VCC
R1
R2
CPLD
R Q
OUT
IN
R2
R1
(c)
designideas
CPLD
Entity Oscillator is
Port (
A : in std_logic;
B : in std_logic;
OUT : out std_logic
);
end Oscillator;
R1
R
R2
OUT
B
C
VCC
A
CPLD
R1
R
R2
OUT
C
TRIGGER
VCC
A
CPLD
R1
R
R2
OUT
B
C
C
Entity Monostable is
Port (
A : in std_logic;
B : in std_logic;
Trigger : in std_logic;
C : out std_logic;
OUT : out std_logic
);
end Monostable;
architecture RTL of Monostable is
begin
A <= B;
OUT <= not A;
C <= 0 when Trigger= 1 else Z;
end RTL;
Port (
A : in std_logic;
B : in std_logic;
Trigger : in std_logic;
C : out std_logic;
OUT : out std_logic
);
end Monostable;
architecture RTL of Monostable is
begin
A <= B;
OUT <= not A;
C <= 0 when Trigger= 1 and A=0 else Z;
end RTL;
TRIGGER
Figure 4 A NAND gate locks out trigger pulses, forming a nonretriggerable, monostable
circuit.
VCC
R4
R1
CPLD
R3
R2
SPST
SWITCH
IN
C
SCHMITT-TRIGGER
BUFFER
OUT
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
AMPLIFIER
IOUTf(VIN)
INPUT
OUTPUT
In this equation, AO is the overall voltage amplification and RD is the LC circuits dynamic resistance at its resonant
frequency. In practical circuits, the
value of RD depends on the LC circuits
properties and thus can fall anywhere
within a wide range. Also, Equation 1
assumes an ideal amplifierthat is, one
having characteristics that are independent of frequency.
Figure 1 and Equation 1 yield a simple insight into the basic design problem: If the operation over a wide freA1
quency range demands the use of several LC circuits with widely varying
values of RD, the amplifiers properties
must be adjustable over a wide range.
You can adjust the amplification to fulfill the gain-limitation condition for
the worst-case LC circuit and then rely
on device nonlinearities to reduce
amplification under overdrive conditions. However, a heavily overdriven
amplifiers input- and output-differential resistances can drop to a fraction
of their optimum, high-resistance values. Second, large amounts of nonlinear distortion can impair frequency stability. Moreover, these effects depend
A2
VA
VIN
VA
I1
I2
IOUT
V11
C
RS
V22
FEEDBACK
designideas
A1
A2
VA
VA
I1
V11
I2
RS
V22
FEEDBACK
VCONT
CS
RECTIFIER
PO
y21S
VCONT
0
VGS
VTH
avoid these problems include transformer coupling or providing impedance-matching taps on the LC circuit,
both of which complicate the design
and only partially solve the problems.
As Figure 2 shows, another oscillator topology features two cascaded noninverting amplifiers, A1 and A2, as voltage-to-current converters (voltagecontrolled current sources). In the circuit, coupling resistor RS converts
amplifier A1s output current, IIN, to
voltage VIN, .and drives the second
stage, A2. The tuned circuits dynamic
resistance converts A2s output current
to output voltage, V22., which feeds
back to A1s input to complete the positive-feedback loop. The overall loop
amplification, ATOTAL, appears in
Equation 2:
(2)
must apply for all values of the LC circuits dynamic resistance, RD. In theory, this condition presents no problem;
however, in practice, a situation arises
in which the circuit must operate as an
LC oscillator with a broad range of tuning inductances and capacitances; a
wide range of tuned-circuit quality-factor Q, which the inductor primarily
determines; a constant-amplitude output at any combination of conditions
A and B; and the best possible frequency stability versus supply voltage
and load.
Most LC oscillator circuits cannot
simultaneously fulfill all of these requirements. Some oscillator circuits can
sequentially fulfill some requirements,
but none can fulfill all of them without
complicating the circuit beyond reasonable limits. Figure 3 shows a circuit
deriving an external dc control signal
from V22 to control the voltage-to-current-conversion coefficientsthat is,
amplification factorsof A1 and A2.
Applying amplification control to
both stages considerably increases the
controls effectiveness. In addition to
the original positive feedback for starting and sustaining oscillation, you can
add an indirect negative-feedback
path to the oscillator circuit to limit
V22s amplitude. To meet the original
design goals, amplifier blocks A1 and A2
should exhibit voltage-controlled
input-versus-output characteristics,
should possess linear-control amplification characteristics (Figure 4),
should not invert the signals phase, and
should draw nearly no input current.
Also, to emulate a current source, A2
should present the highest possible differential internal output resistance.
The best active devices for both
amplifier stages are the selected Nchannel, medium-grade BF245Bs
JFETs with a drain current of 5 mA at
a gate-to-source voltage of 0V and a
drain-to-source voltage of 15V. Figure
5 shows the final circuit, in which Q2
operates as a common-drain amplifier,
A2, and Q1 operates as a common-gate
amplifier, A1.
The gate-source junction of Q1 rectifies the ac voltage, V22, across the
tuned circuit. Coupling capacitor C4
designideas
10VSUPPLY
R1
330
R2
1M
R3
1M
Q2
BF245
Q1
BF245
(a)
C4
82 pF
C2
0.001 F
C1
L1
R4
150
C3
0.001 F
VOUT
(b)
(c)
Figure 6 A clean sine wave (V22 in
Figure 3) appears across the tuned
circuit at 280 kHz for values of 147
H and 2200 pF for L1 and C1,
respectively (a). The sine wave with
respective values of 56 H and 60
pF differ (b). The output waveform
at 280 kHz, for values of 147 H
for L1 and 2200 pF for C1, exhibits
a flat top (c).
expense of added complexity and a larger component count, you can include
a buffer stage and extract a true sine
wave from the LC circuit, but, in the
circuits original application as a radarmarker generator, the constant output
amplitude ranked as of greater importance than the waveshape.EDN
(continued on pg 100)
designideas
Use a systems real-time clock
to hide a code sequence
Mihaela Costin, Delmhorst Instruments, Towaco, NJ
tine at the location in which the hidden code executes. Under normal conditions, the program skips the hidden
code and executes the routine only if
the systems date matches the one that
the routine specifies.
For example, the following pseudocode illustrates the use of Aug 12, 1980,
as a system password:
Check_date:
if (Read_RTC(year)1980 and
Read_RTC(month)8 and
Read_RTC(day)12)
run_hidden_sequence();
Continue_the_Code();
After completing the procedure, you
must remember to reset the systems
clock to the current date and time.
Otherwise, the system executes the special code for the remainder of the day
until the clock rolls over to the next
day.EDN
VIN
VIN
RS
RS
CATHODE VSHUNT
RA
IC1
TL431
VREF
VOUT
VOUT
RA
+
_
RB
+
RB
ANODE
(a)
(b)
designideas
operates as you would expect and delivers output power to the load, and the
auxiliary winding and its components
power the PWM controller.
However, removing the output load
reduces the energy supplied to the auxiliary bias winding, depleting the
charge on CHOLD and causing IC1 to
turn off, which in turn upsets outputvoltage regulation and causes the power
supply to operate erratically. A lowpower bias-supply circuit supplies
light-load start-up power and then
switches off to conserve power whenever the auxiliary winding can supply
enough energy to PWM controller IC1
(Figure 3). In this circuit, a series-pass
regulator turns on under light-load
conditions and turns off when the bias
winding can supply the energy to the
PWM controller, thus conserving
energy under load and improving converter efficiency.
Resistors RA through RD, shunt regulator IC1, diode D1, and transistor Q1
form the low-load series-pass-regulated
bias supply. You select these components to produce a voltage at Q1s emitter that falls between IC1s turn-off voltage and the nominal voltage produced
by rectifying the auxiliary bias windings
output, VAUX_NOM. In effect, the voltage
at IC1s VCC pin follows in wired-OR
fashion whichever is higher: VAUX_NOM
or the voltage at transistor Q1s emitter.
When the auxiliary bias winding and its
components deliver sufficient power,
Q1s emitter sees a reverse bias, and Q1
shuts off to conserve energy. Conversely, Q1 supplies power when VAUX
decreases below VAUX_NOM due to a light
output load. Note that the circuit still
must include trickle-charge resistor RT
because most PWM controllers incorporate undervoltage lockout, the ability to start at a higher than nominal
supply voltage.
To design the series-pass regulator,
select resistor RC to supply sufficient
operating current to IC2, and select
resistor RD to maintain Q1s collector
voltage and current within its safe operating area. Select resistors RA and RB to
set the series regulators output voltage
above IC1s start-up voltage and below
the nominal voltage supplied by the
T1
85 to 265V AC
VOUT
RC
RT
VAUX
T1
CHOLD
IC1
UCC38C42
PWM CONTROLLER
VCC
T1
VLINE
85 to 265V AC
RC
CA
RA
RB
T1
D2
D1
VOUT
RD
Q1
VAUX
RT
VCC
IC1
UCC38C42
PWM CONTROLLER
which the auxiliary bias winding supplies. VREF represents shunt regulator
IC2s internal nominal reference voltage
of 2.495V, and VD1 and VBE(Q1) represent
D1s voltage drop and Q1s forward baseemitter voltage, respectively.EDN
REFERENCE
OLoughlin, Michael, Shunt regulator serves as inexpensive op amp in
power supplies, EDN, Sept 15,
2005, pg 96, www.edn.com/
article/CA6255051.
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
82 Two wires control
SPI high-speed ADC
D1
IN4148
RS
2N3819
S 5k
D Q
D2
IN4148
IS
D4
IN4148
3 +
IC1
2 _LF411
4
R4
OFFSET 10k
ADJUSTMENT
12V
R2
3.07k
12V
R3
10k
D3
IN4148
C1
0.47 F
R1
14.97k
SENSITIVITY
ADJUSTMENT
12V
3 +
7
IC2
LF411
2 _
4
OUTPUT
VOUT
12V
A
THERMISTOR
RP
9466.4
R1
B
Figure 1 This simple circuit linearizes a thermistors response and produces an output period thats proportional to temperature.
designideas
varying R2. For a given temperature
range, L to H, and conversion sensitivity, SC, you can design the circuit as
follows: Let C represent the center
temperature of the range. Measure the
thermistors resistance at temperatures
L, C, and H. Using the three resistance values RL, RC, and RH, determine
RP, for which RAB at C represents the
geometric mean of RAB at L and H. For
this value of RP, you get RAB exactly
equal to AB at the three temperatures, L, C, and H.
At other temperatures in the range,
RAB deviates from AB, causing a nonlinearity error that is appreciably less
than 0.1K for most thermistors when
the temperature range is 30K or less.
You can easily compute RP using:
RPRC[RC(RLRH)2RLRH]/(RLRH
RC2). Because temperature-to-periodconversion sensitivity, SC, is 2R1
C1lnb, you can choose R1 and C1 such
that R1C1SC[HC]/ln(RAB at L/
RAB at H) to obtain the required value
of SC. To get a specific output period,
TL, for the low temperature, L, R2
should equal (RAB at L)eY, in which Y
represents (TL/2R1C1). In practice, use
a lower value for R2 because the nonzero response delay of IC2 causes an increase in the output period.
Next, set potentiometers R1 and R2
close to their calculated values. After
you adjust R1 for the correct SC, adjust
R2 until T equals TL for temperature L.
The two voltage-divider resistances, R3
and R4, should be equal in value and of
12
COMPARATOROUTPUT
VOLTAGE
(V)
T/2
2T
T/2
2T
12
IR2
IRAB
COMPARATORINPUT
0
VOLTAGE
(V)
IRAB
IR2
Figure 2 Waveforms show input to comparator IC2 (lower trace) and its output
(upper trace). In the lower trace, IR2 represents the voltage across R2.
designideas
dedicated chip-selection line.
Given the perpetual demand for
higher sample rates and resolution, I2Cs
limited speed may restrict its use in
some applications and instead force
designers to select SPI. However, SPI
requires an additional I/O pin on the
host controller. In situations in which
extra pins are unavailable but the
application requires a fast SPI-bus converter, you can apply the technique in
Figure 1.
For example, Texas Instruments
ADS7816 comprises a 200k-sample/
sec, 12-bit-sampling ADC that requires a bit rate of 3M samples/sec to
sample continuously at a 200k-sample/sec rate (Reference 1). Selecting
the ADS7816s active-low CS (chipselect) pin initiates a conversion cycle.
After toggling and holding CS low during the data transfer, CS returns high
after transferring the data completes
the process.
When the clock line initially goes
low, it also asserts CS to a low state.
The time constant of the peak detector comprising D1, R1, and C1 ensures
that CS does not go high until the
clock line remains high for more than
one clock cycle (Figure 2). Although
the clock line toggles and retrieves data
from IC2, CS remains asserted low, and,
upon completion of retrieval, the clock
line goes high, and CS follows, readying the circuit for another conversion
cycle.
Because C1 must discharge at the end
MICROCONTROLLER
CLOCK
SCLOCK
DATA
DATA
D1
B0520LW
A
ANALOG
IC1A
IC1B
NOTE: IC1=SN74LVC2GU04.
Figure 1 Two inverters and a few components can substitute for an SPI ADCs
chip-select line.
CLOCK
A
CS
DATA
ZERO B11
B10
B9
B1
B0
B0
B1
NOTE: THE ADS7816 RETRANSMITS THE DATA IN REVERSE-BIT FORMAT AFTER ALL DATA HAS BEEN SENT.
Figure 2 An SPI-clock waveform (top trace) evokes data (bottom trace), and
peak detection of the clock (the waveform at Point A in Figure 1) yields a signal
(next-to-bottom trace) that mimics the chip-selection lines behavior.
CS
R1
C1
ANALOG+
IC2
ADS7816
designideas
nately, the input-to-output delay
inherent in comparators and nonlinear amplifiers determines the minimum output-pulse width. If the hold
capacitor charges quickly to track large
input bursts, the minimum charge step
must greatly exceed the level of small
signals and thus limits the dynamic
range.
Inductor L1 solves the capacitorresponse problem by providing an
adaptively variable source of charging
current. Adding a 10-mH inductor
limits the maximum current rate when
the comparator generates narrow
pulses, thus reducing the minimum
charging amplitude step to a smaller
level of 1 mV or less. For wider charging pulses, the current automatically
ramps up to higher levels to provide
the desired high slewing rate. The
minimum charge step is essentially
proportional to the signal-step size,
ensuring a constant relative accuracy
of better than 1 dB over a 60-dB signal range. A signal level of 59 dB
corresponds to a 13-mV input, and a
C1
22 pF
R10
100
15V
R2
30.1k
6 _
C2
15 pF
IC1B
7
1/2 LT1469
5 +
R7
7.5k
IN
2V P-P
FULL-SCALE
8
2 _
8
3 _
IC1A
1
1/2 LT1469
3 +
4
15V
R9
1.5k
C3
0.033 F
15V
R1
4.99k
C5 +
100 F
D1
CMPD6263S
R3
4.99k
R4
4.99k
R5
15k
IC2
LT1011
+
2
1
R6
30.1k
R11
1.5k
Q1
MMBT3906
R12
22
15V
R8
30.1k
C4
330 pF
NOTE: SCHEMATIC DOES NOT SHOW THE 0.033-F BYPASS CAPACITORS AT EACH IC POWER LEAD.
D2
MBR0520
L1
VISHAY-DALE
IHSM-7832
10 mH
C6
4.7 F
TO METER
12V FULL-SCALE
13 mV AT 59 dB
designideas
Pacer clock
saves subroutine
calls
Enver Torlakovic, Willmot, New
South Wales, Australia
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
IC1
MAX4411
AUDIO
INPUT
J1
HEADPHONE 1
IC2
MAX4762
AUDIO
INPUT
J2
HEADPHONE 2
HEADPHONE
DRIVER
CONTROL
PIN
Figure 1 For low values of power-supply voltage, 2.8V maximum, use an analog switch at IC2 that handles signal amplitudes to VDD5.5V to direct IC1s
bipolar outputs to the headphone loads.
VDD
2.8 TO 5.5V
INPUT
RIGHT
VDD
J1
HEADPHONE 1
INL
INR
SHDN
COM1
OUTL
INL
C1
1 F
IN1
IC1
MAX9722B
IC2
MAX4679
INR
C2
1 F
SVDD
CIN
C1P
J2
HEADPHONE 2
COM
OUTR
PVSS
SVSS
PVDD
C3
1 F
INPUT
LEFT
IN2
C5
1 F
V GND VL V
C4
1 F
C6
1 F
CONTROL
PIN
Figure 2 Higher values of VDD, 2.8 to 5.5V, require a different amplifier and a
dual-supply-voltage switch at IC2.
designideas
tive voltage generated within the low-noise, positive-supply voltage of impedance would heavily load the
MAX9722B to eliminate the need for approximately 2V. The resistor provides microphone and halve its dc bias, movan additional charge-pump-power- dc bias to the JFET and allows the ing it out of its optimum operating
supply circuit.
microphone capsules audio-output sig- range and reducing its output and
To enhance a mobile-telephone nal to appear on the output terminal. In SNR. Adding analog switch IC2
design, you can use a stereo-headphone most applications, the microphones between the microphone and the
jack to accommodate a hands-free com- output connects directly to a high- headphone amplifiers output maintains
bination earphone and microphone. impedance, low-noise amplifier, IC3, by the microphones bias and resistive
load.EDN
You use the stereo jacks tip connection ac coupling of capacitor C1.
The amplifiers 2-k-to-ground offas the headphone contact, the ring contact for the microphone, and the shell
MICROPHONE
IC3
BIAS
contact as the common
MICROPHONE
connection to ground
AMPLIFIER
R1
MICROPHONEC1
(Figure 3). When you
AMPLIFIER
OUTPUT
connect the hands-free
2.8V
MICROPHONE
combination, you must
also turn off one channel
J1
IC2
of headphone amplifi
MAX4762
AUDIO
SPEAKER
_
er IC1. Although the
INPUT
MAX4411 amplifier of+
fers an individual-chanIC1
MAX4411
nel-shutdown feature,
AUDIO
_
the devices outputs
INPUT
present an impedance of
+
2 k to ground when
HEADPHONE
you switch it off.
DRIVER
An electret microCONTROL
PIN
phone capsule typically
includes an open-drain
Figure 3 When using a hands-free microphone/earphone kit as an alternative to stereo headJFET-output
circuit
phones, add the circuitry shown to avoid loading the microphones output with the headphonethat typically requires
driver amplifiers output.
a 2-k resistor, R1,
which connects to a
Recent developments in electric-double-layer-capacitor technology have made it possible to replace rechargeable batteries in certain
secondary-power-storage applications
(Reference 1). Capacitors offer significant advantages over rechargeable batteries, including a practically unlimited number of charge/discharge cycles,
survival of short circuits, and simple
charging circuits that require only overvoltage protection. In addition, storage
capacitors recharge quickly and pose no
designideas
inexpensive, hand-powered flashlight
and use its generator as a capacitor
charger (Figure 4). Also, a variety of
manually powered products now
appearing on the market offer possibilities for experimentation. For higher
outputs, you can use a stationary-bicycle-powered generator. Depending on
the individual providing pedaling
power, these generators can deliver
average powers ranging from 20 to
100W. The hand-cranked flashlight in
Figure 4 originally lit a 2.5V, 0.15A, filament-type bulb, which consumes
approximately 0.4W at full brightness.
However, measurements show that the
generator could deliver more power and
could charge a 1F capacitor to 5V in
approximately 10 sec. Thus, the following equation calculates the energy,
E, stored in the capacitor of value C:
E1/2CVMAX212.5J, and the following equation calculates the average
maximum muscle-generated electrical
power over time, T: TMAXE/T12.5/
101.25W.
You can use the following equation
to calculate the effective energy,
EEFF, that the capacitor can deliver during its discharge cycle while its
terminal voltage changes from maximum to minimum voltage: EEFF
1
/2C(VMAX2VMIN2), where VMAX2 and
VMIN2 represent the maximum and minimum operating voltages, respectively,
MUSCLEPOWERED
GENERATOR
DIODE BRIDGE
+
DZ
DC OUT
Figure 1 This charger circuit for storage capacitor C requires few additional
components: a diode-bridge rectifier and an overvoltage-limiting zener diode.
rent ratings of the diode-bridge rectifier and the zener diode, DZ. Experimental measurements on the handcranked generator yield the following
approximate values for its open-circuit
voltage: maximum voltage of 10V rms,
peak voltage of 14V, and maximum
short-circuit current of 200 mA rms.
For this application, an inexpensive
bridge rectifier with 20V minimum
peak-inverse voltage and 0.5A minimum forward current provide adequate
margins. DZs breakdown-voltage rating
should be slightly lower than the storage capacitors maximum working
voltage, and the diodes power rating
2W in this applicationshould exceed
the product of the generators maximum output current and the zeners
conduction voltage.EDN
REFERENCE
Figure 4 A hand-cranked flashlights electrical generator serves as a musclepowered charger for a high-capacity storage capacitor (lower left).
1
Bell, Alexander, Single capacitor
powers audio mixer, EDN, March 14,
1997, pg 80, www.edn.com/archives/
1997/031497/06DI_04.htm.
designideas
FET biasing targets
battery-powered
PWM applications
12V
CL
RL
VIN
VOUT
RL
CL
(a)
(b)
12V
CL
RL
VOUT
D
VIN
G
S
(a)
(b)
Figure 2 An N-channel FET driver (a) has output that exhibits an exponential rising edge on shutoff.
12V
12
VIN
0 TO 5V
R1
2.1k
S
CB
1 F
R2
7.9k
(a)
VB
9.5V DC
G
D
fC =
VOLTAGE
(V)
1
.
2RC
9.5
(b)
Figure 3 Adding resistive bias and capacitive coupling to an N-channel MOSFET (a) improves transition times but introduces waveform droop during on or
off intervals (b).
designideas
R2 applies a dc bias to the output FETs
gate thats equal to the difference
between the output power-supply voltage and the midrail logic voltage. For
example, in a 12V Class D PWM audio
amplifier driven from a 5V microcontroller, bias the P-channel FETs gate at
9.5V (12V5V/2). Use the specified
FETs for logic-level gate drive as output
devices because other FETs dont
exhibit nominal IDS characteristics at
gate drives of 5V or lower.
Battery-powered amplifiers with
resistive-divider output-stage bias introduce an additional complication. As
battery voltage decreases, so does bias.
Instead, you can use a voltage-reference
IC or a zener diode, D1, to provide a
VREF
GND
D1
2.5V
CB
1 F
VIN
0 TO 5V
R1
100
VB
9.5V DC G
R2
100k
48V
2.5VREF
Q1
12V
1
2
ZETEX ZRC250
48V
C3
1 F
R3
20k
R4
100
5V
VCC
C1
1 F
AUDIO IN
C2
1 F
R5
100k
PVCC
OUT+
VREF
IN
Q3
OUT
GND
C5
1 F
48V
2.5VREF
IN+
R2
150k
IRL3502
IC1
TPA2010D1
R1
150k
Q2
MTP50P03HDL
FET PAIR
L1
33 H
SP1
1
2
SPEAKER
5V
NOFF
GND
ZETEX ZRC250
GND
48V
C4
1 F
R6
20k
R8
100k
R7
100
Q4
MTP50P03HDL
FET PAIR
L2
33 H
IRL3502
Figure 5 This Class D audio amplifier boosts its drivers output to 200W rms for a 48V power supply.
C6
1 F
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
124 DMA eases CPUs workload for waveform generation
TWO-ROW-BY-16-CHARACTER LCD
E
6
DATA
7-14
RS
4
R/W
5
VCC
XTAL1
15 pF
PORTA.1
AT90S8515
MICROCONTROLLER
FROM RECEIVER
PORTA.4
15 pF
XTAL2
BIT1
BIT2
BIT3
BIT4
BIT5
BIT6
BIT7
BIT8
designideas
TIMER INTERRUPT
TIMERITPS=0?
NO
YES
MAIN LOOP
SEND 1E6 BITS?
NO
PORTA.1=
PORTA.4?
YES
NO
YES
SET DISPLAY
DISPLAY SET?
YES
NO
INCREASE ERRORS
INCREASE TIMERITPS
RETURN
checks for table boundaries to determine when to reset the table pointer.
Writing the periodic values to the
DAC to maintain the output waveform
requires CPU overhead, which varies
depending on the data tables length,
the output waveforms frequency, and
the CPUs operating frequency. For
example, using 32 data points per period to generate a 1-kHz sine wave
requires the CPU to service 32,000
interrupts/sec. If the application requires a second analog output wave-
REFERENCES
http://intec.ugent.be/design/.
AVRStudio 4, www.atmel.com.
3
SP12, www.xs4all.nl/~sbolt/
e-spider_prog.html.
4
www.newwaveinstruments.com/
resources/articles/m_sequence_
linear_feedback_shift_register_lfsr.
htm.
1
2
designideas
OPTIONAL RECONSTRUCTION
FILTERS
VCC
DAC0_OUT
DAC
DATA
TABLE
MSP430F15/16X
DMA
DAC
DAC1_OUT
VSS
Figure 3 A phase shift occurs between the sine and the cosine output waveforms; removing the lowpass filters in Figure 2 reveals switching artifacts.
designideas
ate a periodic waveform. Although
DMA transfers do not involve the CPU,
each transfer does consume two CPU
clock cycles, which delays CPU code
execution and thus introduces overhead. For the single-waveform example,
using DMA transfers consumes two
clock cycles for each DAC update
instead of the 18 cycles necessary when
using only the CPU. Thus, for a CPU
clock rate of 1 MHz, using DMA
reduces the effective CPU loading from
57.6% to 6.4% and increases the possible maximum output frequency from
approximately 1.73 kHz to approximately 15.6 kHz. For an 8-MHz clock
rate, using DMA reduces single-waveform CPU loading from 7.2% to 0.8%.
Generating two waveforms requires
two DMA transfers or four clock cycles.
For the two-waveform example, DMA
VIN
V+
V+
PDN
VIN
1
8
V+
V+
7
V+
PDN
+
I1
+
I1
+
4
+
4
monic distortion. Listing 2, also available at www.edn.com/051205di2, contains software that generates sine and
cosine waves and illustrates the DMA
channels independent operation apart
from the CPU. Note that, after initialization of DMA channels and other
device-specific peripherals, no further
CPU activity occurs.
Figure 2 shows a partial schematic of
the DACs outputs. Depending on the
application, you may need to add
optional resistance-capacitance lowpass
filters at the DACs outputs. Select values for the resistor and capacitor in
each filter to produce a pole in the filter response at the desired output frequencies. Note that the oscilloscope
photo in Figure 3 was taken with filters removed to show the DAC outputs
unfiltered waveforms.EDN
RSENSE
1k
IO
IO
IC1
AD8130
I2
RSENSE
1k
I2
_
V
IC1
AD8130
V
+
IC2
AD8065
_
Figure 2 Adding an Analog Devices AD8065 buffer amplifier, IC2, isolates the current-sampling resistor RSENSE and
reduces errors that IC1s input-bias current contributes.
designideas
though the circuit in Figure 1 provides
V+
V+
a good starting point, the AD8130s rel7
3
atively high input bias current can
V+
PDN
affect output-current accuracy at low
1
VIN
+
current levels.
I1
8
_
RSENSE
To overcome the problem, you can
CO
1k
6
+
add a unity-gain buffer, IC2, to isolate
IO
4
the current-sense resistor (Figure 2). In
+
I2
addition, you can use the buffer ampli5
_
IC1
fier to measure the load voltage and
AD8130
V
bootstrap the output cables capaci2
tance. The circuit presents an output
V
impedance of about 500 k at 1 MHz
R1
+
and a current-compliance range of 0 to
1M
IC2A
+
3V using 5V power supplies.
AD8066
IC2B
_
AD8066
C1
Current sources that have capaci_
1 F
tance-coupled loads benefit from a dc
servo loop to stabilize the circuits operC2
R2
ating point (Figure 3). The value of
1 F
1M
output-coupling capacitor CO depends
on the desired low-frequency roll-off
characteristic. Further improvements
Figure 3 For an ac-coupled current output, add a dc-stabilization loop, IC2A and
of the basic circuit enable compensaIC2B.
tion of output capacitance and increase the circuits output impedance.
A small, adjustable feedback
V+
0V
capacitor, CCOMP, thats approxC13
C10
C9
C12
C11
C8
10 F
100 nF
10 F
100 nF
100 nF
100 nF
imately one-half of the outputs
V
0V
stray capacitances provides
V+
V+
feedforward compensation and
7
3
C1
further reduces the effects of
R1
V+
PDN
10 F 1.8k
1
stray capacitance at the output
VIN
+
(Figure 4). To prevent oscillaI1
8
C7
_
R9
tion, the cables shield-driver
10 F
100
6
R
+
2
circuits gain should be slightly
200
4
less than unity. Note that
+
I2
reducing the output-currentC6
CCOMP
5
_
10 F
3 TO 20 pF
IC2
sense resistor, R9, to 100 comAD8130
V
C3
pensates for the input attenua1 F
2
tor formed by R1 and R2 and
VOSTP
V
C5
maintains a 1-mA/V character10 F
R3
istic. This voltage-to-current
+
OUTPUT
1M
sources frequency range spans
+
IC1B
_
IC1A
1/2
20 Hz to 10 MHz. For best
_
1/2
AD8066
results, use high-frequency cirC4
AD8066
10 F
cuit-layout and power-supplyR7
100
bypassing methods.EDN
SHIELD
C2
V+
1 F
MORE AT EDN.COM
R4
1M
R5
20k
1k VOS
R8
10k
R6
10
V
Figure 4 The complete circuit includes trimmer capacitor CCOMP, which compensates
for stray capacitances in the circuits packaged layout. Also, note wideband treatment of power-supply bypass capacitors.
designideas
READERS SOLVE DESIGN PROBLEMS
D Is Inside
66 Programs calculate
1% and ratio-resistor pairs
D2
TO OUTPUT
FILTER
RT
VSHUNT
Q1
VCC
GATE
IC1
UC3853A
D1
CH
L2
NOTE: DASHED LINE SHOWS MAGNETIC COUPLING BETWEEN WINDINGS L1 AND L2.
VIN
FROM RAW
DC SUPPLY
L1
RD
D4
VOUT
TO FILTER
RE
D3
Q1
RA
VREF
RB
CT
D2
D1
TL431
L2
CH
VAUX
Q2
VCC GATE
IC1
UC3853A
RC
NOTE: DASHED LINE SHOWS MAGNETIC COUPLING BETWEEN WINDINGS L1 AND L2.
designideas
Capacitor CT and resistor RC conserve
energy by setting the bootstrap circuits
turn-off time and voltage. Resistor RD
supplies bias current to D1, the TL431
shunt-regulator IC, and resistor RE keeps
transistor Q1 within its safe operating
area by limiting its collector current.
To design the circuit, begin by selecting resistors RA and RB to establish the
peak charging voltage, as the following
equation shows:
Contemporary research laboratories include a variety of instruments that connect using any of
several interface methods to a PC for
automating procedures and collecting
data. Although different communication interfaces exist, the GPIB (general-purpose-interface bus) still enjoys
wide popularity. The host PC must
include a suitable GPIB controlleran
internal interface card or an external
device. Newer PC designs are phasing
out traditional internal buses, such as
PCI, ISA, and EISA, in favor of other
standards, so using an external controller offers a more appropriate approach because external I/O ports, such
as RS-232 and USB, tend to maintain
backward compatibility.
This Design Idea covers the development of a GPIB controller, which
turned out to be easier and cheaper
than commercially available alternatives. The design uses easy-to-obtain
components with a total component
cost of approximately $50. For comparison, a commercial controller costs
at least 10 times more: $500 to $1000.
The USB 2.0-compliant controller, an
external device, draws its operating
power from the bus and provides plugand-play operation and high-speed data
transfer. In addition, a USB-controller
design extends its applications to notebooks and other computers that lack
available I/O slots. The controller re-
As in Figure 1, diode D2 and auxiliary winding L2 provide normal operating power to IC1.EDN
SWITCHED SUPPLY
SUPPLY
DATA
DATA
PB
PA
75160
TE
USB
MICROCONTROLLER
USB
GPIB
CONTROL
PD
PC
75161
DC
CONTROL
designideas
controller with any programming language that supports serial-port communications. The LabView driver is
compatible with LabViews built-in
GPIB driver, thus simplifying adapta-
Programs calculate
1% and ratio-resistor pairs
Carl Rutschow, Upland, CA
tion, you can choose whether the program displays all possible values or only
the values closest to the target value.
Using standard 1%-resistor values,
a second program, RPar2a.exe, also
available at www.edn.com/051216di1,
checks and displays all appropriate
combinations that generate a desired
parallel resistors value. The program
VIN
R2
VIN
R2
R1
VOUT
R1
VOUT
RATIO1
(a)
VIN
R2
.
R1
(b)
R1
.
R1R2
_
VOUT
R1
ATTENUATION
R2
R
GAIN1 2 .
R1
(c)
Figure 1 You can use the program Rratio2.exe to calculate ratio (a), attenuation (b), or gain (c).
designideas
Simplify worst-case PSpice
simulations with customized
measurement expressions
13V enable threshold, the output voltage goes high and enables other circuit
blocks. When the input voltage falls
below a 10V disable threshold, the output voltage goes low and disables other
circuits. The difference between the
Wayne Huang and Jeff Van Auken, Picor Corp, North Smithfield, RI
enable and the disable thresholds
During IC design, worst-case pression to find a y2 value when Trace that is, 3Vdefines the hysteresis voltsimulations help designers ac- 1 crosses a y1_value for the nth nega- age. A worst-case simulation of the circount for variations in characteristics tive slope or when Trace 1 crosses a cuit must account for variations in
of PNP and NPN transistors and base given percentage of its full y-axis range. characteristics of NPN and PNP tranand polysilicon resistors. These four
Figure 1 shows a simulation example sistors, base resistors, and polysilicon
classes of devices alone produce more in which the input and the output volt- resistors in the circuit. Each devices
than 16 combinations of simulation ages represent a comparators input and characteristics can fall at either the low
conditions. To accommodate temper- output, respectively. When the input or the high end of the process specifiature variations, each combination voltage is greater than the positive cations and thus produce 16 combinaundergoes simulation at 40, 27 threshold voltage, then the output volt- tions.
(room temperature), and 125C, pro- age is high; when the input voltage is
The toolbar lists a few of the 16 posducing at least 48 series of data to ana- less than the negative threshold volt- sible combinations. For example,
lyze when simulations are complete. To age, the output voltage is low. Using LLLL refers to the case in which charhelp an IC designer evaluate simulat- customized measurement expressions, a acteristics of NPN and PNP transistors
ed waveforms characteristics, PSpice designer can easily find the rising and and base and polysilicon resistors all fall
provides a library of ready-to-use, pre- falling thresholds and the comparators at their low values. In addition, one
defined measurements, including hysteresis voltage for all conditions pass of the simulation uses nominal valbandwidth, gain/phase margins, and immediately after the probe data ues; that is, the components specificamore. PSpice also allows a designer to becomes available. If any condition tions fall in the centers of their nomiuse predefined YatX and XatNthY exists in which the threshold doesnt nal characteristics. For each combinameasurements to measure a waveforms meet the design specification, the tion, PSpice simulates the circuits
y value at a given x valueusually, designer can then go directly to that behavior at low, room, and high temtimeand to find an x value that cor- condition and spend time on further peratures, respectively, producing 51
responds to the nth instance of a given analysis.
data traces for the blocks input and
y value (Reference 1).
The simulation example describes an output voltages for a total of 102 disHowever, when a designer must input-voltage monitor comprising a played traces. After PSpice assembles
measure the value of Waveform 1 comparator that acts as a power-good the data, the circuits designer must
when Waveform 2 crosses a certain y block in a power-management IC. extract the actual threshold voltages for
value, predefined measurements do When the input voltage rises above a each condition for comparison with the
not apply because, unlike
circuits specifications.
many programming lanGiven the large numguages, PSpice allows no
ber of displayed traces,
embedment. This Design
using the displays curIdea describes how to create
sor to measure each
a customized PSpice measthreshold consumes
urement expression that
much of a designers
solves the problem. As
time. Using a cusListing 1 shows, the meastomized PSpice measurement expression itself is
urement extracts the
straightforward. Line 1
threshold voltages in a
finds the X_value (x1)
fraction of the time
when Trace 1 crosses the
and presents the data
y1_value for the nth posiin tabular form. The
tive slope. Line 2, denoted
table
immediately
by braces { } at the bottom
below the waveform
of the listing, searches for
plot contains simulathe value of Trace 2 (y2) at
tion results for all 51
x1. Similarly, Listing 2
traces. Columns 1, 2,
Figure 1 On-screen waveforms represent inputs and outputs for
shows how a designer can
and 3 list results for
multiple simulation passes.
create a measurement exnominal characteris-
designideas
LISTING 1 MEASUREMENT EXPRESSION FOR x1
Y2atY1SIG_Neg(1,2,y1_value,n_occur)=y2
{
1| search forward for n_occur:level (y1_value, negative) !1;
2| search forward Xvalue (x1) !2;
}
Y2atY1SIG_Percent(1,2,y1_pct,n_occur)= y2
{
1| search forward for n_occur:level (y1_pct% ) !1;
2| search forward xval (x1) !2;
}