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ProgrammablePeripheralInterface(8255).
ProgrammableCommunicationInterface(8251).
ProgrammableTimer(8253).
DMAController(8257).
ProgrammableInterruptController(8259).
KeyboardDisplayInterface(8279).

DirectMemoryAccess

CONCEPTOFDMA
Theideaisoneoftransferringdatainoneofthe

followingcases
i)frommemorytoaperipheral
ii)fromaperipheraltomemory
ii)f
i h l
iii)frommemorytomemory(aspecialcase)

FlybyDMA

Figure11.17|Timingassociatedwithflyby
DMAoperation(DMAwrite)

ThefastestDMAtransfertypeisreferredtoasasingle

cycle,singleaddress,orflybytransfer.
InaflybyDMAtransfer,asinglebusoperationisused

toaccomplishthetransfer,withdatabeingreadfrom
toaccomplishthetransfer withdatabeingreadfrom
thesourceandwrittentothedestination
simultaneously.

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Figure11.18|Timingforfetchand
depositDMA

FetchandDepositDMA
ThistypeoftransferinvolvestwomemoryorI/O

cycles.
ThedatabeingtransferredisfirstreadfromtheI/O

deviceormemoryintoatemporarydataregister
internaltotheDMAcontroller.

TheDMAcontrollercanissuecommandstothe
memorythatbehaveexactlylikethecommands
issuedbytheCPU.

TheDMAcontrollerinasenseisasecond
processorinthesystembutisdedicatedtoan
I/Ofunction.

TheDMAcontrollerasshownbelowconnects
oneormoreI/Oportsdirectlytomemory,where
theI/OdatastreampassesthroughtheDMA
controllerfasterandmoreefficientlythan
throughtheprocessorastheDMAchannelis
specialised tothedatatransfertask.

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ThebulkdatatransferfromfastI/Odevicestothe
memoryorfromthememorytoI/Odevicesthrough
theaccumulatorisatimeconsumingprocess.

Themicroprocessorhastorelinquishthecontrolofthe
addressanddatabusesforDMAoperationontherequest
oftheI/Odevice.

ForDMAdatatransfertheI/Odevicemusthaveitsown
registerstostorebytecountandmemoryaddress.

Itmustalsobeabletogeneratecontrolsignalsrequiredfor
DMAdatatransfer.

Forsuchasituationthedirectmemoryaccess(DMA)
techniqueispreferred.

InDMAdatatransferscheme,dataaredirectly
transferredfromI/OdevicestoRAMorfromRAMto
I/Odevices.

GenerallysuchfacilitiesarenotavailablewithI/Odevices.
SinglechipprogrammableDMAControllershavebeen
developedbyseveralmanufacturersfortheinterfacingof
I/OdevicetothemicroprocessorforDMAdatatransfer.

ForDMAdatatransfer,thedataandaddressbuses
comeunderthecontroloftheperipheraldevicewhich
wantsDMAdatatransfer.

SuchcontrollersmeetalltherequirementsforDMAdata
transfer.

1.TheprocessortransmitsthefollowinginformationtoaDMA
controller:
(a)beginningaddressinmemory
(b)blocklength(numberofwordstotransfer)
(c)direction(memorytodeviceordevicetomemory)
(d)portID
(e)endofblockaction(interruptrequestornointerruptrequest).
2.TheprocessorreturnstootheractivitieswhiletheDMAcontroller
p
startsthedatatransfer.
3.EachtimetheDMAcontrolleraccessesmemory,itsynchronises this
memoryrequestwithanidleperiodoftheprocessor todothisthe
possibilitiesare:
(a)forceanimmediatedisablingoftheprocessor,or
(b)requestahaltoftheprocessor,andawaitanacknowledgement,or
(c)timetheDMAaccesstoaclockintervalorstatussignalofthe
processorthatsignalsanidlecycle.

Thisshowsthatthecontrolleristreatedasa
standardportbeforeandafterblocktransferand
duringtransfertheDMAmustbeableto
synchronise withtheprocessor.
Thecontrollerimprovesperformanceespecially
withabuiltinprogramformovingastreamof
databetweenmemoryandanI/Oportthereby
notrequiringtoaccesstheinstructionfrom
memoryandexecutingthemonebyone.

4.WhentheDMAcontrolleraccessesanI/Oportor
memory,itusesthesamefunctionalcontrolsignalsasused
bytheprocessor.I/Oportactivitycanbeperformedon
dedicatedlinesthatdonothavetobesynchronised with
theprocessor.
5.Atthecompletionoftheblocktransfer,theDMA
controllerraisesaninterruptrequestiftheinterruptsare
"armed"andotherwiseindicatescompletioninitsstatus
register.
6.Theprocessorrecognises I/Ocompletion(eitherby
interruptorbyreadingthestatusregister);thereafterthe
activitybetweentheprocessorandtheDMAcontroller
followsthenormalpostcompletionactivityofanyI/O
port.

Someelementaryactionscanbeperformedinparallel
insteadofsequentiallywhenimplementedwithsoftware
intheprocessor.Forexample,thecontrollerdecrementsa
countereachtimeitmovesadata.
Thecontrollercanoverlapthesubtractionwithmemory
accessandavoidthetimepenaltyforthearithmetic
p
y
instruction.
Becauseoftheabilitytoachievehigherperformancefor
blocktransfers,theDMAcontrollerisusedmost
frequentlyforhighspeedI/O,especiallydisk.Fastdisks
moveblocksofdataatspeedsmuchgreaterthanany
programcancontrolandthereforemustbeinterfacedto
computersthroughDMAcontrollers.

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Thei8527controllerhasfourindependentchannels
eachofwhichcontainsanaddressregisteranda
counter.
Thecounterdecrementsaseachbytetransferoccurs,
Thecounterdecrementsaseachbytetransferoccurs
andforcesterminationoftheDMAoperationafter
thelasttransfer.
Thecontrollerincrementstheaddressregisterafter
eachoperation,sothatsuccessivedatatransfersare
madeatcontiguousascendingaddresses.

Thearbiterresolvesconflictsamongthechannelsfor
accesstomemory.
Twomethodshavebeenusedinthischiptomakethechip
usefulinavarietyofdifferentapplications.
Inonemodethechannelshaveafixedpriorityand
conflictsareresolvedaccordingtothepriority,for
fli t
l d
di t th i it f
example,Channel0hashighestpriorityandChannel3
lowest.
Thesecondmodeisarotatingpriorityschemeinwhich
priorityrankingsarethefourcycleshiftsof0123,whena
channelisgrantedaccesstothebusthepriorityranking
shiftscyclicallytoplacethechannelinthelowestpriority
positionforthenextarbitrationcycle.

Itisa40pinICpackageandrequiresasingle+5Vsupply

foritsoperation.
FourI/Odevicescanbeinterfacedtothemicroprocessor

throughthisdevice.Itiscapableofperformingthree
operations,namelyread,writeandverify.
Duringthereadoperationdataaredirectlytransferred

fromthememorytotheI/Odevice.
Duringthewriteoperationdataaretransferredfromthe

I/Odevicetothememory.

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OnreceivingarequestfromanI/Odevice,the8257

Initially,theDMAaddressregisterisloadedwiththe

generatesasequentialmemoryaddresswhichallows

addressofthefirstmemorylocationtobeaccessed.

theI/Odevicetoreadorwritedirectlytoorfromthe
memory.
Eachchannelincorporatestwo16bitregisters,

DuringDMAoperationitstoresthenextmemory

locationtobeaccessedduringnextDMAcycle
locationtobeaccessedduringnextDMAcycle.

namely(i)DMAaddress
registerand(ii)bytecountregister.
Theseregistersareinitialised beforeachannelis

enabled.

DRQ0DRQ3.TheseareDMArequestlines.AnI/Odevice
sendsitsDMArequestononeoftheselines.AHIGHstatusof
thelinegeneratesaDMArequest.
DACKo DACK3 .TheseareDMAacknowledgeline.The
Intel8257sendsanacknowledgesignalthroughtheline
informinganI/OdevicethatithasbeenselectedforDMAdata
transfer.ALOWonthelineacknowledgestheI/Odevice.
AoA7:Theseareaddresslines.
AoA3arebidirectional
lines.Inthemastermodetheselinescarry4LSBsof16bit
memoryaddressgeneratedbythe8257.
Intheslavemodetheselinesareinputlines.Theinputsselect
oneoftheregisterstobereadorprogrammed.
A4 A7linesgivetristatedoutputswhichcarry4through7ofthe
16bitmemoryaddressgeneratedbythe8257.

MEMR:Memoryread.
MEMW:Memorywrite.
TC:Bytecount(Terminalcount).
MARK:Modulo128Mark.
CLK.Clock.
HRQ.Holdrequest.
HLDA.Holdacknowledge.

14LSBsofthebytecountregisterstorethenumberof

bytestobetransferred.214 (16384)bytesofdatacan
directlybetransferredtothememoryfromtheI/Odevice
orfromthememorytotheI/Odevice.

DoD7:Thesearedatalines.
AEN:Addressenable.
ADSTB:AHIGHonthislatchesthe8MSBsoftheaddress,whichare
sentonDbus,intoIntel8257connectedforthispurpose.
CS:Itischipselect.
I/OR I/Oread.Itisabidirectionalline.Inoutputmodeitisusedto
accessdatafromtheI/OdeviceduringtheDMAwritecycle.
I/OW:I/Owrite.Itisabidirectionalline.Inoutputmodeitallowsthe
transferofdatafromthememorytotheI/OdeviceduringtheDMAread
cycle.

AnI/OdevicesendsitsrequestforDMAtransfer
throughoneofthefourDRQlines.
OnreceivingtheDMArequestforDMAdatatransfer
fromanI/Odevice,theIntel8257sendsthehold
requesttotheCPUthroughtheHRQline.
The8257receivestheholdacknowledgedsignalfrom
theCPUthroughHLDAline.
AfterreceivingtheholdacknowledgefromCPUit
sendsDMAacknowledgetotheI/Odevicethrough
DACKline.

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Forreadoperation,ie.,forthetransferofdatafromthe
memorytotheI/OdeviceMEMRandI/OWlinesgolow.

Thememoryaddressissentoutonaddressand

datalines.
The8257sends8MSBsofthememoryaddress

overDbus.
These8MSBsofthememoryaddressare

latchedinto8212(Latch)usingADSTBsignal.
ADSTBissimilartoALEofIntel8085/8086.

Forwriteoperationi.e. forthetransferofdatafromthe
I/OdevicetothememoryMEMWandI/ORlinesgolow.
.Thebytecountisdecrementedbyoneafterthetransferof
onebyteofdata.
onebyteofdata
Whenbytecountbecomeszero,TCgoeshighindicating
thatthedatatransferusingDMAiscomplete.
ThefourDMAchannelsareprogrammedeitherinafixed
prioritymodeofrotatingmodeofoperation.READYlineis
usedbyslowmemoryorI/Odevices.

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