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ARM microcontroller
Krzysztof MAICHER*
In this paper basic information about Xilinx Spartan-3 Generation FPGA architecture is described
and its configuration options are compared. Then the advantages of microcontroller controlled FPGA
configuration are discussed. Finally the microcontroller-based configuration system and its
functionality are presented, focusing on the interface between microcontroller and FPGA.
1.
INTRODUCTION
1.1.
SPARTAN-3 ARCHITECTURE
Politechnika Wrocawska, Wybrzee Wyspiaskiego 27, 50-370 Wrocaw, Koo Naukowe CHIP,
opiekun Koa Naukowego: dr Tomasz Surmacz, opiekun projektu: dr Jacek Majewski
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Figure 1. Spartan-3 architecture [2].
1.2.
FPGA devices have internal RAM, where the configuration bitstream is loaded.
After every system power-up the configuration file has to be send to FPGA to define
its functionality. There is also possible to reconfigure internal RAM upon system
demand during FPGAs work. Spartan-3 generation devices offer elastic ways of
internal RAM configuration. They can initiate communication and download
configuration beatstream from an external flash memory (master configuration mode)
or wait to be configured by other device, such as microcontroller or CPU (slave
mode). After every reset, FPGA samples mode bits (M[2..0]), which determinates the
configuration option. All available possibilities are summarized in Tabele 1.
Configuration beatstream is loaded to Spartan-3 generation devices from an
external memory using serial or parallel communication interfaces. Parallel interface
is faster than serial, but more I/O pins have to be used during configuration process.
In master configuration mode, FPGA always initiates the transmission and controls
the clock signal. That mode is useful in stand-alone applications, which means, that no
external download host is needed for start-up FPGAs application. In slave mode,
when an intelligent host, like microcontroller, DSP, or CPU controls the FPGA, there
is a possibility to configure it in any moment during working application. It can be
also reconfigured with another configuration beatstream, depended of system needs.
The configuration data can be located anywhere in system, including already existed
in system ROM, on SD card, or even in microcontrollers internal flash. That saves
costs and place on PCB due to fact that no special memory has to be used to store the
configuration files. There is also possible to extend microcontroller-based configurator
by USB interface and configure the FPGA loading data from PC using USB interface.
2.
HARDWARE
2.1.
TEST BOARD
The idea of the project is to show how to control the FPGAs configuration process
by the microcontroller. Block schematics of the test board is shown on figure 2. FPGA
and microcontroller are placed on their own minimodules, which are connected
together by the interface on the main board.
Xilinx Spartan-3 XC3S200 is used as the FPGA platform. Its minimodule was
design by dr Jacek Majewski, documentation can be found on website of Students
Organisation KN CHIP (http://chip.ict.pwr.wroc.pl). To configure this FPGAs internal
configuration memory, microcontroller has to transfer 1.047.616 configuration bits
(~130kB). As a configuration host NXP LPC2148 ARM microcontroller is used. Its
internal flash memory is big enough to fit the XCS200 configuration file. The
microcontroller is also placed on a minimodule - ZL10ARM, distributed by Kamami
(www.kamami.pl).
Main board (designed by Krzysztof Maicher) includes connectors for described
minimodules and peripherals used to communicate with the computer (JTAG for
ARM, JTAG for Spartan-3, RS232) and with user (LCD, keypad).
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Figure 2. Block schematics of the test board.
2.2.
COMMUNICATION INTERFACE
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Figure 3. Communication interface between microcontroller (LPC2148) and Spartan-3 (XC3S200).
SOFTWARE
2.3.
MICROCONTROLERS SOFTWARE
2.4.
CRC. As the configuration data is send, FPGA calculates the CRC (Cyclic
Redundancy Check) and compares it with CRC transferred during data
transmission. When they dont match, that means errors has occurred during
data transmission. FPGA puts INIT_B line low and microcontroller shows
CRC error communicate to user.
Start-up sequence check. When CRC phase was successfully completed,
microcontroller has to give 7 more clock cycles. FPGA needs 5 cycles to
finish start-up sequence, then drives DONE bit low, which means, that whole
configuration process has ended and FPGA is ready to work. In next 2 clock
cycles it activates I/O ports.
FPGAS SOFTWARE
FPGAs configuration file was prepared in Xilinx ISE 9.2i Project Navigator. Its a
simple program, written in VHDL, which purpose is to show that FPGA was
configured successfully, by blinking the LED connected to FPGAs IO port (figure 4).
LITERATURA
[1] MAJEWSKI J, ZBYSISKI P, Ukady FPGA w przykadach, Warszawa, Wydawnictwo BTC, 2007
547, 193212
[2] Spartan-3 Generation Configuration User Guide, http://www.xilinx.com, 8 marca 2008
[3] Spartan-3 Generation User Guide, http://www.xilinx.com, 8 marca 2008
JTAG
All
<1:0:1>
Serial
Slave
Serial
All
<1:1:1>
Serial
External
clock
on TCK
pin
External
clock
signal
applied
on
CCLK
pin
Slave
Parallel
All
<1:1:0>
Bytewide
Internal
Master
SPI
Spartan-3 AN
<0:1:1>
Serial
Master
Parallel
Spartan-3
<0:1:1>
Bytewide
12
BPI
Spartan-
-3A,
-3AN,
-3A DSP,
-3E
<0:1:0>
Bytewide
SPI
Spartan-
-3A,
-3AN,
-3A DSP,
-3E
<0:0:1>
Serial
13
Master
Serial
All
<0:0:0>
Serial
Spartan-3
Generation
Families
M[2:0]
mode pin
settings
Data
width
Configuration memory
source
Internal
oscillato
r
Clock
source
21
46
I/O pins
borrowed
during
config.