Totem Pole Voltage Sources

Define a series of bias voltages between the positive and the negative supply
voltages.

V+
IREF

Q3

VOUT3

M2

VOUT2

Q1

VOUT1

In practice, output currents are small (or zero), so that the DC bias voltages are
set by IREF

EE 105 Spring 1997

Lecture 20

MOSFET Current Sources

Bias n-channel MOSFET with a DC voltage source

VDD
IREF

iOUT
+

M1

+
VREF

M2

vOUT

Intuitively, VREF is set by IREF and determines the output current of M2

I REF
V REF = V Tn + ------------------------------- = V GS1 = V GS2
W
----- C
2L 1 n ox

EE 105 Spring 1997

Lecture 20

MOSFET Current Sources (cont.)

Substituting into the drain current of M2 (and neglecting (1 + nVDS2) term)

2
W
I OUT = I D2 = ------ n C ox ( V GS2 V Tn )
2L 2

2
I REF

W
I OUT = I D2 = ------ n C ox V Tn + ------------------------------- V Tn
2L 2
W

----- n C ox

2L 1

Output current is scaled from IREF by a geometrical ratio:

( W L ) 2
I OUT = -------------------- I REF
( W L ) 1

EE 105 Spring 1997

Lecture 20

MOSFET Current Source Equivalent Circuit

Small-signal model: source resistance is ro2 by inspection

+
gm1vgs1

ro1

gm2vgs2

vgs2 = 0 V

ro2

Combine output resistance with DC output current for approximate equivalent

circuit ... actual iOUT vs. vOUT characteristics are those of M2 with VGS2 = VREF

iOUT

iOUT
+

(W/L)2
IREF
(W/L)1

ro2

vOUT

(a)

(W/L)2
IREF
(W/L)1

1/ro2
VDS

vOUT

SAT2

(b)

EE 105 Spring 1997

Lecture 20

The Cascode Current Source

In order to boost the source resistance, we can study our single-stage building
blocks and recognize that a common-gate is attractive, due to it high output
resistance

VDD
iOUT
IREF

M3

M4

M1

M2

Adapting the output resistance for a common gate amplifier, the cascode current
source has a source resistance of
R S = ( 1 + g m4 r o2 )r o4 g m4 r o4 r o2

Penalty for cascode:

needs larger VOUT to function

EE 105 Spring 1997

Lecture 20

MOSFET Current Sources and Sinks

n-channel current source sinks current to ground ... how do we source current
from the positive supply? Answer: p-channel current sources...?
VDD

M1

MR

M2
iOUT2

iOUT1

M3
iOUT3

IREF

By mixing n-channel and p-channel diode-connected devices, we can produce

current sinks and sources from a reference current connected to VDD or ground.
VDD

M1

MR
iOUT1

M2
iOUT2
iOUT4

IREF

M3

M4

EE 105 Spring 1997

Lecture 20

Two-Stage BiCMOS Transconductance Amplifier

Concept: cascade two common-emitter stages to get more transconductance -not an ideal solution but illustrates DC biasing and interstage coupling

iout

RS
+
vs

+v

in1
Rin1

Rout1 Rin2
Gm1vin1

CE (npn)

vin2
_

Rout2 RL
Gm2vin2
CE (pnp)

DC Issues:
First stage: npn common-emitter amplifier (DC level shifts up)
Second stage: pnp common-emitter amplifier (DC level shifts down)

EE 105 Spring 1997

Lecture 20

Amplifier Topology

Basic structure -- connect output of CE (npn) to input of CE (pnp),

attach small-signal voltage input (with RS) and load (RL)

V+ = + 2.5 V
iSUP1
Q2
RS
+
vs
_

iout

Q1
RL

V
_ BIAS

iSUP2
V - = - 2.5 V

Current source design:

assume that the reference current is generated by a resistor (to ground)

EE 105 Spring 1997

Lecture 20

DC Currents from Reference

p-channel diode-connected M3 is used to generate source-gate voltages for M4

(which generates iSUP1) and for M5. The second current supply is generated by
first using -ID5 to generate a DC gate-source voltage via diode-connected M7.

V+ = + 2.5 V
M4

M3

M5

iSUP1
IREF

- ID5

RREF
iSUP2
ID7
M6

M7
V - = - 2.5 V

EE 105 Spring 1997

Lecture 20

Two-Stage BiCMOS Transconductance Amplifier

Combine current source circuit with basic amplifier topology

V+ = + 2.5 V
M4

M3

M5

Q2
iout

RREF

RS
+
vs
_

Q1
RL

V
_ BIAS

M6

M7
V -= - 2.5 V

EE 105 Spring 1997

Lecture 20

DC Bias of Transconductance Amplifier

Given: VOUT = 0 V (DC); V+ = 2.5 V, V - = -2.5 V; RS = RL = 50 k

Standard simplifications: assume IB = 0 for bipolar transistors, neglect Early
effect (BJT) and channel-length modulation (MOSFETs) for hand calculations

V+ = + 2.5 V
M4

M3

M5

Q2
iout

RREF

RS
+
_

vs

Q1
RL

V
_ BIAS

M6

M7
V -= - 2.5 V

Device Properties: (for simplicity, make all n-channel and all p-channel
MOSFETs the same dimensions)
MOSFETs: n Cox = 50 AV-2, (W/L)n = (50/2), VTn = 1 V, n = 0.05 V-1
p Cox = 25 AV-2, (W/L)p = (80/2), VTp = - 1 V, p = 0.05 V-1
BJTs: on = 100, VAn = 50 V, op = 50, VAp = 25 V

EE 105 Spring 1997

Lecture 20

Reference Resistor

Find RREF such that IREF = 50 A and then find all node voltages and DC bias
currents ...
+2.5 V
+ V_SG3
M3

V SG3 = V DD I REF R REF V SS

- ID3

I D3
V SG3 = V Tp + --------------------------------------------( W ( 2L ) ) p p C ox

0
IREF

RREF

- 2.5 V

Substituting IREF = - ID3 = 50 A, the source-gate voltage drop is

50 A
V SG3 = ( 1 V ) + ---------------------------------------------------- = 1.22 V
2
80
--------------- ( 50 A/V )
( 2 ( 2 ) )

Solve for the reference resistor:

( V DD V SS ) V SG3
2.5 V ( 2. 5 V ) 1.22 V
R REF = ---------------------------------------------------- = ----------------------------------------------------------------- = 75.6 k
I REF
50 A

EE 105 Spring 1997

Lecture 20

DC Operating Point

Since width-to-length ratios are identical for n-channel and p-channel devices
(separately), the DC supply currents are equal to the reference current
V+ = + 2.5 V
ISUP1 =
50 A
Q2
RS
+
_

vs

iout

Q1
RL

V
_ BIAS

ISUP2 =
50 A
V - = - 2.5 V

Neglecting base currents, IC1 = 50 and IC2 = 50

Q1: gm1 = 2 mS, r1 = 50 k, ro1 = 1
Q2: gm2 = 2 mS, r2 = 25 k, ro2 = 500 k
Source resistances of the current supplies for first and second stages:
roc1 = ro4 = (4(-ID4))-1 = (0.05(0.05))-1 = 400 k
roc2 = ro6 = (6(ID6))-1 = (0.05(0.05))-1 = 400 k

EE 105 Spring 1997

Lecture 20

Overall Two-Port Model

Rin = Rin1 = 50 k and Rout = Rout2 = ro2 || roc2 = 500 k || 400 k = 220 k

Overall short-circuit transconductance Gm -- must apply procedure

iout
+

vin
_

+v

in1
Rin1

Rout1 Rin2
Gm1vin1

vin2
_

Rout2
Gm2vin2
CE (pnp)

CE (npn)
Find input voltage to the second stage:

vin2 = - Gm1( Rout1 || Rin2 ) vin = - gm1 ( ro1 || roc1 || r 2 ) vin

Output current
iout = Gm2 vin2 = gm2 [- gm1 (ro1 || roc1 || r2)] vin

Overall transconductance:
Gm = iout / vin = - gm2 gm1 (ro1 || roc1 || r2)
Gm = - (2 mS)(2 mS)(1 M || 400 k || 25 k) = - (2 mS)(2 mS)(23 k)
Gm = - 92 mS

EE 105 Spring 1997

Lecture 20

Output Voltage Swing

Find the maximum and minimum values of vOUT

V+= 2.5 V
M4

M3

M5

Q2
RREF
vOUT

Q1
+

V
_ BIAS

M6

M7
V -= - 2.5 V

Determine how high the output node can rise before a device leaves its constantcurrent region
Q2 saturates when vOUT = VOUT(max) = 2.4 V ... VEC(sat) = 0.1 V
Note that M4 is still saturated since VSD4 = VEB4 = 0.7 V > vSG4 + VTp = 0.22 V

Determine how low the output node can drop ...

M6 goes triode when vOUT = VDS7(sat) = VGS7 - VTn = 1.22 V - 1 V = 0.22 V
VOUT(min) = - 2.5 V + 0.22 V = 2.23 V

EE 105 Spring 1997

Lecture 20