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S.VENKATLAKSHMI
M.E VLSI Design
Knowledge Institute of Technology
Salem, India
gvenkatlakshme@gmail.com
Index Terms
I.
INTRODUCTION
N.VIJAYANANDAM
Assistant Professor
Knowledge Institute of Technology
Salem, India
nvece@kiot.ac.in
analyzed where delay can occur that reduced the speed of the
operation under test during test applications. The BS-LFSR is
combined with a scan-chain-ordering algorithm that orders the
cells in a way that reduces the average and peak power (scan
and capture) in the test cycle or while scanning out a response
to a signature analyzer. These techniques have a substantial
effect on average- and peak-power reductions with negligible
effect on fault coverage or test application time. Experimental
results on ISCAS89 benchmark circuits show up to 65% and
55% reductions in average and peak power, respectively[1].
Girard presented surveys about the available low
power testing techniques during testing. It also suggests some
advantages and disadvantages associated with every
technique. The System-On-Chip revolution challenges both
design and test engineers, especially in the area of power
dissipation. Generally, a circuit or system consumes more
power in test mode than in normal mode. This extra power
consumption can give rise to severe hazards in circuit
reliability[2].
Girard considers the problem of minimizing the
energy required to test a BIST combinational circuit without
modifying the stuck-at fault coverage and with no extra area
or delay overhead over the classical LFSR architectures. First,
is to analyze the impact of the polynomial and seed selection
of the LFSR used as TPG on the energy consumed by the
circuit. Second, is to propose a method to significantly
decrease the energy consumption of BIST sessions. For this
purpose, a heuristic method based on a simulated annealing
algorithm is used. Finally results are obtained with no loss of
stuck-at fault[3].
S. Gupta suggested a new built-in self-test (BIST)
test pattern generator (TPG) design, called low-transition
random TPG (LT-RTPG. An LT-RTPG is composed of a linear
feedback shift register (LFSR), a -input AND gate, and a T
flip-flop. When used to generate test patterns for test-per-scan
BIST, it decreases the number of transitions that occur during
scan shifting and, hence, decreases switching activity during
testing. Various properties of LT-RTPGs are identified and a
methodology for their design is presented. Experimental
results demonstrate that LT-RTPGs designed using the
proposed methodology decrease switching activity during
BIST by significant amounts while providing high fault
coverage[4].
TEST CONTROLLER
TPG
M
U
X
CUT
MISR
COMPARATOR
Faulty
/ Fault
free
D. Test Controller
the controller connects normal inputs to the CUT via
the multiplexer, thus making it ready for operation. Among the
modules discussed above, the most important one is hardware
test pattern generator (LFSR) as applied algorithm to test
VLSI circuits.
Block Diagram of Test Pattern Generator
Figure shows the block diagram of test pattern
generator. It consist of D Flip-Flop and seed generator.
DFF
G0
DFF
G1
DFF
Gm-1
DFF
G3
DFF
Gray counter
EX
OR
gate
EX OR
gate
EX
OR
gate
EX
OR
gate
AT
E
GA
TE
m-
m-
(a)
(d)
Fig.3.a the simulation result of test pattern generation using LFSR
b. Power analysis report of LFSR c the simulation result of test
pattern generation using Gray counter. D. Power analysis report of
Gray counter
(b)
IV CONCLUSION
Test patterns are generated by using gray counter. This
test pattern generator consists of n D flip-flops and n-1
exclusive-OR gates. Hence hardware overhead can be
controlled. The generated test patterns are applied to Circuit
Under Test and analyze the circuit with area and power
consumption. The power consumption is of the test pattern
generation were analyzed using Xilinx.
References
[1]
(c)
[2]
[3]
[4]
[5]
[6]
[7]