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Design Methodology
Application Note AN-32
Designing an off-line power supply involves many aspects of
electrical engineering: analog and digital circuits, bipolar and
MOS power device characteristics, magnetics, thermal
considerations, safety requirements, control loop stability, etc.
This represents an enormous challenge involving complex
trade-offs with a large number of design variables. As a result,
new off-line power supply development has always been tedious
and time consuming even for the experts in the field. This
application note introduces a simple, yet highly efficient
methodology for the design of TOPSwitch-GX family based
off-line power supplies. For TOPSwitch-GX Flyback designs,
Power Integrations recommends the use of PI Expert which
implements this design methodology and also includes a
knowledge base and optimization feature for making key design
choices, further reducing design time.
Introduction
The design of a switching power supply, by nature, is an
iterative process with many variables requiring adjustment to
optimize the design. The design method described in this
document consists of two major sections: A design flow chart
Clamp Zener
Blocking Diode
Output Capacitor
+VD-
Line Sense
Resistor
+VDB-
+
VAC
+
VO
+
VB
-
Bias Capacitor
CIN
L
TOPSwitch-GX
CONTROL
Feedback Circuit
July 2004
AN-32
1. System Requirements
VACMIN, VACMAX, fL, VO, PO, , Z
Step 1-2
Determine System Level Requirements
and Choose Feedback Circuit
5. Set KP
6. Determine DMAX
Step 3-11
Choose The Smallest TOPSwitch-GX
For The Required Power
From Step 23
Y
To Step 12
PI-3039-080502
C
7/04
Design Flow
Figures 2A, 2B and 2C present a design flow chart showing the
complete design procedure in 37 steps. With the basic circuit
configuration shown in Figure 1 as its foundation, the logic
behind this design approach can be summarized as follows:
1. Determine system requirements and decide on feedback
circuit accordingly.
2. Choose the smallest TOPSwitch-GX capable of the
required output power.
3. Design the smallest transformer for the TOPSwitch-GX
chosen.
4. Select all other components in Figure 1 to complete the
design.
AN-32
From Step 11
12. Determine LP
13. Choose Core & Bobbin
Determine Ae, Le, AL, BW
17. Calculate BM
18. BM 3000
Y
19. Calculate Lg, CMA
Step 12-28
Design the Smallest Transformer
to work with the TOPSwitch-GX Chosen
20. Lg 0.10 mm
Y
To Step 10
23. BP 4200
Y
24. Calculate ISP
To StepPIV
28 , PIV
28. Calculate
S
B
To Step 29
PI-3040-091802
AN-32
From Step 28
Design
Complete
PI-2584-091402
C
7/04
AN-32
Step-by-Step Design Procedure
This design procedure uses the PI Expert design software (available
from Power Integrations), which contains all the important
equations required for a TOPSwitch-GX flyback power supply
design, and automates most calculations. Designers are, therefore,
relieved from the tedious calculations involved in the complicated
and highly iterative design process. Look-up tables and empirical
design guidelines are provided in this procedure where appropriate
to facilitate the design task.
Step 1. Determine system requirements: VACMAX, VACMIN,
fL, VO, PO, , Z
Minimum AC input voltage, VACMIN: in volts.
Maximum AC input voltage, VACMAX: in volts.
Recommended AC input ranges:
Input (VAC)
Universal
85
265
195
265
VB Circuit Load*
(V) Tolerance Reg.
Pri./Basic
5.8
10%
Pri./Enhan. 27.8
5%
Opto/Zener 12
5%
Opto/TL431 12
1%
5%
Line
Reg.
1.5% 16.5%
2.5% 1.5%
1%
Total
Reg.
9%
0.5% 6.5%
Table 1.
VO
VAC
CIN
Feedback Circuit
TOPSwitch-GX
L
15
CONTROL
C
S
CIRCUIT PERFORMANCE
Circuit Tolerance 10%
Load Regulation 5%
Line Regulation 1.5%
PI-3331-112202
C
7/04
AN-32
VO
VAC
CIN
15
TOPSwitch-GX
L
CONTROL
CIRCUIT PERFORMANCE
Circuit Tolerance 5%
Load Regulation 2.5%
Line Regulation 1.5%
1N5251D
22 V
1%
C
S
Feedback Circuit
100 nF
50 V
PI-3330-091102
VO
VAC
47
CIN
470
TOPSwitch-GX
LTV817A
CIRCUIT PERFORMANCE
Circuit Tolerance 5%
Load Regulation 1%
Line Regulation 0.5%
CONTROL
C
S
Feedback Circuit
Zener, 2%
47 is suitable for V up to 7.5V. For V > 7.5V, a higher value may be required for optimum transient response.
O
O
470 is good for Zeners with I = 5 mA. Lower values are needed for Zeners with higher I . (E.g. 150 for I = 20 mA).
ZT
ZT
ZT
PI-3328-112202
C
7/04
AN-32
+
VO
VAC
470 (VO = 12 V)
100 (VO = 5 V)
CIN
CIRCUIT PERFORMANCE
Circuit Tolerance 1%
Load Regulation 0.2%
Line Regulation 0.2%
UTV817A
TOPSwitch-GX
1 k
CONTROL
3.3 k
S
R=
100 nF
VO - 2.5
2.5
X 10 k
TL431
10 k
Feedback Circuit
PI-3329-112202
P/N
4 Pin DIP
PC123Y6
PC817X1
SFH615A-2
SFH617A-2
SFH618A-2
ISP817A
LTV817A
LTV816A
LTV123A
K1010A
6 Pin DIP
LTV702FB
LTV703FB
LTV713FA
K2010
PC702V2NSZX
PC703V2NSZX
PC713V1NSZX
PC714V1NSZX
MOC8102
MOC8103
MOC8105
CNY17F-2
70 V
70 V
70 V
70 V
55 V
35 V
35 V
80 V
70 V
60 V
Sharp
Sharp
Vishay, Isocom
Vishay, Isocom
Vishay, Isocom
Vishay, Isocom
Liteon
Liteon
Liteon
Cosmo
63-125
63-125
80-160
60-160
63-125
63-125
80-160
80-160
73-117
108-173
63-133
63-125
70 V
70 V
35 V
60 V
70 V
70 V
35 V
35 V
30 V
30 V
30 V
70 V
Liteon
Liteon
Liteon
Cosmo
Sharp
Sharp
Sharp
Sharp
Vishay, Isocom
Vishay, Isocom
Vishay, Isocom
Vishay, Isocom,
Liteon
Table 3. Optocoupler
Universal
230 or 115 with doubler
2~3
90
240
Table 4
VMIN
tC
2 PO
2 fL
2
= (2 VACMIN )
CIN
C
7/04
AN-32
Step 4. Determine reflected output voltage VOR and clamp
Zener voltage VCLO (Figure 8)
VACMIN 2
V+
VMIN
tC
PO = Output Power
fL = Line Frequency
(50 or 60 Hz)
tC = Conduction Angle
Use 3 ms if unknown
= Efficiency
PI-2585-012500
BVDSS
Margin = 53 V (95 V)
Blocking Diode Forward Recovery = 20 V
700 V
647 V (605 V)
627 V (585 V)
555 V (525 V)
VCLM
VCLO
VMAX
495 V (475 V)
VOR = 120 V (100 V)
375 V
VCLO = 1.5 x VOR = 180 V (150 V)
VCLM = 1.4 x VCLO = 252 V (210 V)
0V
0V
C
7/04
AN-32
KP KRP =
IR
IP
IR
Primary
IP
K P K RP =
Primary
K P K DP =
IP
IR
IR
where IR is primary ripple current and IP
IP
V OR (1 D MAX )
(V MIN VDS ) D MAX
KP KDP = (1-D) x T
t
T = 1/fS
Primary
(1-D) x T
DxT
t
Secondary
(a) Discontinuous, KP > 1
T = 1/fS
Primary
DxT
(1-D) x T = t
Secondary
C
7/04
AN-32
KP
Input (VAC)
Continuous
Mode
Discontinuous
Mode
Universal
0.4~1.0
1.0
230
0.6~1.0
1.0
Table 5
DMAX =
(VMIN
V OR
VDS ) + V OR
Discontinuous mode
DMAX =
V OR
K P (VMIN VDS ) + V OR
IP =
I AVG
1 K P D
MAX
2 I AVG
IP =
D MAX
Input average current I AVG
PO
=
V MIN
Continuous mode
I RMS = IP DMAX
K P2
K P +1
Discontinuous mode
2
I RMS = DMAX
Z (1 ) +
10 PO
LP =
2
K
IP K P 1 P fS (min)
I
P
3
Discontinuous mode.
6
Z (1 ) +
10 PO
LP =
2
1
IP fS (min)
2
where units are H, watts, amps and Hz
10
C
7/04
AN-32
Z is loss allocation factor and is efficiency from Step 1.
Step 13. Choose core and bobbin based on fS and PO using
Table 6 and determine Ae, Le, AL and BW from core and
bobbin catalog
Core effective cross-sectional area, Ae: in cm2.
Core effective path length, Le: in cm.
Core ungapped effective inductance, AL: in nH/turn2.
Bobbin width, BW: in mm.
Choose core and bobbin based on fS, PO and construction
type.
66 kHz
Output
Power
132 kHz
Triple
Triple
Insulated Margin Insulated Margin
Wound
Wound
Wire
Wire
EF12.6
EI22
EF12.6
EI22
EE13
EE19
EE13
EE19
EF16
EI22/19/6 EF16
E122/19/6
EEL16
EE16
EEL16
0-10 W EE16
EE19
EF20
EI22
EI25
EI22/19/6 EEL19
EF20
EI28
EE19
EF20
10 WEEL22
EI22
EI25
EF25 EI22/19/6 EEL19
20 W
EF20
EF25
EI30
E128
20 WEPC30
30 W
EEL25
EI28
E30/15/7
EF25
EEL22
EI30
EER28
EF25
E30/15/7 ETD29
EI30
30 W- EER28
EI35
EPC30
50 W
EI33/29/
13-Z
EER28L
ETD29
EF32
EI28
EEL25
50 WEI35
ETD34
E30/15/7
70 W
EF32
EER28
ETD34
EI40
EI30
ETD29
E36/18/11 E36/18/11 E30/15/7
EI35
EI40
EER35
EER28
EI33/29/
70 WETD29
13-Z
100 W
EER28L
EF32
ETD39
ETD39
EI35
ETD34
100 W- EER40
EER40
EF32
EI40
150 W
E42/21/15 ETD34 E36/18/11
EER35
E42/21/15 E42/21/20 E36/18/11 ETD39
E42/21/20 E55/28/21 EI40
EER40
E55/28/21
ETD39 E42/21/15
>150W
EER40 E42/21/20
E42/21/15 E55/28/21
E42/21/20
E55/28/21
N P = NS
V OR
VO + VD
N B = NS
VB + VDB
VO + VD
OD =
L ( BW 2 M )
NP
BM =
100 IP L P
N P Ae
11
AN-32
Gap length in mm: Lg 0.1
1
NP
L g = 40 Ae
1000 L P A L
2
1.27 DIA
1000
4
CMA =
25.4
I RMS
2
Lg
CMA
NS
core
size
ODS =
I RIPPLE = ISRMS IO
1.27
1000
DIAS =
Table 7.
BP
BW (2 M )
NS
I LIMIT (max)
BM
IP
PIVS = VO + (VMAX
NS
)
NP
N
I SP = I P P
NS
PIVB = VB + (VMAX
ISRMS
K P2
= ISP (1 DMAX )
K P + 1
Step 29. Select clamp Zener and blocking diode per Table 8
for primary clamping based on VOR and the type of output
PS Output
VOR
Multiple Output
100 V
Single Output
120 V
Discontinuous mode
ISRMS
12
C
7/04
1 D MAX
= ISP
3 K P
NB
)
NP
Table 8.
Blocking
Diode
BYV26C
MUR160
UF4005
BYV26C
MUR160
UF4005
Clamp
Zener
P6KE150
P6KE180
AN-32
Step 30. Select output rectifier per Table 9
VR(V)
ID(A)
40
40
60
60
60
40
40
40
60
60
40
60
45
1
1
1
1
1.1
3
3
3
3
3
5
5
7.5
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
Axial
TO-220
MBR760
MBR1045
60
45
7.5
10
TO-220
TO-220
MBR1060
MBR10100
MBR1645
60
100
45
10
10
16
TO-220
TO-220
TO-220
MBR1660
60
MBR2045CT 45
Package Manufacturer
16
TO-220
20(2x10) TO-220
Output
Output Capacitor
UFR
UF4002
UF4003
MUR120
EGP20D
BYV27-200
100
200
200
200
200
1
1
1
2
2
UF5401
UF5402
EGP30D
BYV28-200
100
200
200
200
3
3
3
3.5
MUR420
BYW29-200
200
200
4
8
BYV32-200
200
18
Table 9.
General Semi
General Semi
General Semi
IR
IR
General Semi
General Semi
IR
General Semi
IR
General Semi
General Semi
General Semi
IR
General Semi
General Semi
IR
General Semi
General Semi
General Semi
IR
General Semi
General Semi
IR
General Semi
General Semi
IR
Axial
Axial
Axial
Axial
Axial
General Semi
General Semi
General Semi
General Semi
General Semi
Philips
Axial General Semi
Axial General Semi
Axial General Semi
Axial General Semi
Philips
TO-220 General Semi
TO-220 General Semi
Philips
TO-220 General Semi
Philips
VR (V)
Manufacturer
BAV21
UF4003
1N4148
200
200
75
Philips
General Semi
Motorola
Table 10.
13
AN-32
Series resistor: 6.8 , 1/4 W (Not needed if KP 1, i.e.
discontinuous mode).
Step 36. Select feedback circuit components according to
applicable reference feedback circuits shown in Figures 3,
4, 5 and 6
Applicable reference circuit: Identified in Step 2.
Step 37. Select input bridge rectifier
VR 1.25 x 2 x VACMAX; where VACMAX is from Step 1.
ID 2 x IAVE; where ID is the bridge rectifier rated current
and IAVE is average input current.
Note:
I AVE =
POUT
;
VMIN
14
C
7/04
AN-32
Appendix A
Multiple Output Flyback Power
Supply Design
The only difference between a multiple output flyback power
supply and a single output flyback power supply of the same
total output power is in the secondary side design. Instead of
delivering all power to one output as in the single output case,
a multiple output flyback distributes its output power among
several outputs. Therefore, the design procedure for the primary
side stays the same, while that for the secondary side demands
further considerations.
Design with lumped output power
One simple way of doing multiple output flyback design is
described in detail in AN-22, Designing Multiple Output
Flyback Power Supplies with TOPSwitch. The design method
starts with a single output equivalent by lumping output power
of all outputs to one main output. Secondary peak current ISP and
RMS current ISRMS are derived. Output average current IO
corresponding to the lumped power is also calculated.
Assumption for simplification
The current waveforms in the individual output windings are
determined by the impedance in each circuit, which is a function
of leakage inductance, rectifier characteristics, capacitor value
and most importantly, output load. Although this current
waveform may not be exactly the same from output to output,
it is reasonable to assume that, to the first order, all output
currents have the same shape as for the single output equivalent
of lumped power.
N S ( n) = NS
VO (n) + VD (n)
V + VD
NS ( n)
+ VO (n)
NP
I SRMS
IO
where ISRMS(n) and IO(n) are the secondary RMS current and
output average current of the nth output and ISRMS and IO are the
secondary RMS current and output average current for the
lumped single output equivalent design.
C
7/04
15
AN-32
Revision Notes
Date
1) Final release.
1) Minor revision.
1) Minor revision: Corrected VMAX equation.
A
B
C
9/02
12/02
7/04
The PI logo, TOPSwitch, TinySwitch, LinkSwitch and EcoSmart are registered trademarks of Power Integrations.
PI Expert and DPA-Switch are trademarks of Power Integrations. Copyright 2004, Power Integrations
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