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4.1
(a) VG > VTN corresponds to inversion region operation. (b) VG << VTN corresponds to the accumulation region. (c) VG <
VTN corresponds to a bias in the depletion region .
4.9
a 0 0.8V I D
=0
2 0.8
VGS VTN DS V DS 200 2
0.25 538 A
L
2
2
V 0.5m
I D K n'
(d ) VGS
I D K n'
V
W
A
200 2
L
V
e K n K n' W
5m
0.25
3 0.8
0.25 1.04 mA
2
0.5m
5m
mA
2.00 2
V
0.5m
4.11
Identify the source, drain, gate and bulk terminals and find the current I in the transistors in Fig. P-4.3.
W
=
L
+0.2 V
10
1
G
+5
(a)
V GS
DS
+
VGS
-0.2 V
+5
B
D
W
=
L
10
1
DS
(b)
(a)
(b)
W
L
VGS VTN
V DS
2
A 10
0.2
V DS 100 2
5 0.70
0.2 840 A
2
V 1
I = I S 100 2
V
0.2
10
5.2 0.70 0.2 880 A
2
1
Note that the source-bulk junction is forward biased by 0.2 V! This is well below the
Turn-on voltage, so we should be safe in neglecting the bulk current.
4.15
a Ron
b Ron
1
K n'
W
VGS VTN
L
1
23.0
6 100
100 x10
5 0.65
1
1
50.0
6 100
100 x10
2.5 0.50
1
4.17
Ron
ID
0.1V
10
A
0.010 10m | K n
33.9 2
10 A
VGS VTN 0.5VDS VDS 5 2 0.5 0.1 0.1
V
W K n 33.9 339,000
!
L K n' 10 4
1
4.18
395A
A
V 2 1.25
A
1
100 2
V
From the graph, VTN is somewhat less than 2 V. VTN > 0 enhancemen t - mode transisto r.
This qualitativ e observatio n agrees with our calculated value for VTN .
395 4 VTN
A
125
a For VGS 0, VGS VTN and I D 0 b For VGS 1V , VGS VTN and I D 0
c VGS VTN = 2 - 1 = 1V and VDS 3.3 | VDS VGS VTN so the device is in the
saturation region
375 A 5m
W
A 5m
mA
2
2 1 V 2 1.88 mA | K n K n'
375 2
3.75 2
2
2 V 0.5um
L
V 0.5um
V
VTN = 3 - 1 = 2V and V DS 3.3 | V DS VGS VTN so the device is in the saturation region
ID
d VGS
ID
375 A 5m
2
3 1 V 2 7.50 mA
2
2 V 0.5m
4.20
4.23
(a) VGS - VTN = 2.6 V, VDS = 3.3 V. VDS > VGS - VTN Saturation region
(b) VGS < VTN Cutoff region
(c) VGS - VTN = 1.3 V, VDS = 2 V. VDS > VGS - VTN Saturation region
(d) VGS - VTN = 0.8 V, VDS = 0.5 V. VDS < VGS - VTN triode region
(e) The source and drain of the transistor are now reversed because of the sign change in V DS. Assuming the voltages are
defined relative to the original S and D terminals as in Fig. P4.11(a), V GS = 2 - (-0.5) = 2.5 V, V GS - VTN = 2.5 0.7 =
1.8 V, and VDS = 0.5 V triode region. The "drain-substrate" diode is forward biased by 0.5 V.
(f) The source and drain of the transistor are again reversed because of the sign change in V DS. Assuming the voltages
are defined relative to the original S and D terminals as in Fig. 4.54(b), V GS = 3 - (-3) = 6 V, VGS - VTN = 6 0.7 = 5.3
V, and VDS = 3 V triode region , but the source-substrate diode is forward biased and will be conducting heavily. The
transistor would probably be destroyed.
4.27
VDS = 3.3V, VGS VTN = 1.3 V; VDS > VGS - VTN so the transistor is saturated.
a g m
A 20 m
2 0.7 6.50 mS
V 2 1m
b g m
A 20m
4.28
a g m
i D
760 140 A
A
4 1.5V 313 S
V2
390 15 A
A
b g m
i D
vGS
4.34
(a) Since VDS = VGS and VTN > 0 for both transistors, both devices are saturated.
I D1
K n' W
K n' W
2
VGS1 VTN and I D 2
VGS 2 VTN 2
2 L
2 L
Therefore
From the circuit, however, ID2 must equal ID1 since IG = 0 for the MOSFET:
I I D1 I D 2 or
K n' W
K'
VGS1 VTN 2 n W VGS 2 VTN 2
2 L
2 L
which requires VGS1 = VGS2. Using KVL:
V DD
5V
2
K n' W
VGS1 VTN 2 100 A2 10 5 0.75 2 V 2 9.03 mA
2 L
2 V 1
(b) The current simply scales by a factor of two (see last equation above), and I D = 18.1 mA.
(c) For this case,
I D1
K n' W
K'
VGS1 VTN 2 1 + VDS1 and I D 2 n W VGS 2 VTN 2 1 + VDS2
2 L
2 L
.
I D1
K n' W
K'
VGS1 VTN 2 1 + VGS1 and I D 2 n W VGS 2 VTN 2 1 + VGS2
2 L
2 L
and ID1 = ID2 = I
K n' W
K'
VGS1 VTN 2 1 + VGS1 n W VGS 2 VTN 2 1 + VGS2
2 L
2 L
which again requires VGS1 = VGS2 = VDD/2 = 5V.
K n' W
VGS1 VTN 2 1 VDS 100 A2 10 5 0.75 2 V 2 1 .04 5 10.8 mA
2 L
2 V 1
4.42
2 1.19 1.23 mA
2
0. 5
(d ) VGS VTN 3 1.19 1.81V < VDS 3.3 V Saturation region
ID
375 x10 6
2
(e) K n K n'
5
2
3 1.19 6.14 mA
0. 5
W
mA
5
375 x10 6
3.75 2
L
V
0.5
4.46
4.49
The pinchoff points and threshold voltage can be estimated directly from the graph: e. g. V GS = -3 V curve gives VTP =
2.5 - 3 = - 0.5 V or from the VGS = -5 V curve gives VTP = 4.5 - 5 = - 0.5 V.
Alternately, choosing two points in saturation, say ID = 1.25 mA for VGS = -3 V and ID = 4.05 mA for VGS = -5 V:
V VTP
I D1
GS1
or
VGS 2 VTP
I D2
1.25 3 VTP
4.05 5 VTP
2I D
VGS VTP 2
21.25mA
3 0 .5 2
A
400 2
mA W K p
V 10
0.400 2 |
'
A
L Kp
1
V
40 2
V
4.51
ID
40A 20
0.2 0.2 72.0 A
1.3 0.75
2
2
V 1
4.57
Ron
4.91
0.1V
0.2
0.5 A
Kp
ID
0.5 A
A
0.629 2
VGS VTP 0.5VDS VDS 10V 2V 0.5 0.1V 0.1V
V
800
5V
600
Q-point
(4.84)
400
4V
Q-point
(4.83)
200
3V
2V
0
VGS
V DD
3V | 6 = 10 4 I D V DS | V DS 0, I D 0.6mA | I D 0, V DS 6V
2
From the graph, Q-pt: (140 A, 4.6V) in the saturation region. --- [See Q-point 4.83 above.]
4.93
a1
100k
10V 3.13V | Assume saturation
100k 220k
100 x10 6 6
VGS 1 2
24 x10 3
2
a 2 Assume saturation
ID
210 4 6 / 1 24 x10 3
1 210
6 24 x10 3.13 1 1
3
4.104
68.8 A
Kn
L
1
1V
RS
VGS
R2
15V
| R2 600k
1.33M 1.5M
6.75V
6.75V
R1
RR
15V | 6.75V 1 2
R1 R2
R1 R2
6.75V
R1
15V R1 1.23M 1.2M
R1 1.5M
W 10
L
1
4.107
6 x10 4
2
8.1V
4.109
VGS 4 2
5V
2.5k 2.4k and VR S will be 4.8 V | 2mA =
2mA
2mA
1.50V | VG VS VGS 4.8 1.5 6.3V
0.125mA
VGS 2.5
6.3 = 15
R1
R1 = 620 k and R2 = 910 k is one convenient possibilit y.
R 1 R2
15 5 4.8V
2mA
2.60k 2.70 k.
4.111
100 x10 6 20 A
2
VGS 12 10 I D and I D
2 VGS 0.75V
2
1 V
100VGS2 149VGS 44.25 0 VGS 1.08V , 0.409V VGS 1.08 V since VGS must
5
100 x10 6 20 A
2
2 1.08 0.75V
2
1 V
12 1.08
I D 109 A | Checking : I D
109 A | Q - Point : 109 A,1.08 V
10 5
(b) Using KVL, VDS = 107 IG +VGS. But, since IG = 0, VGS = VDS. Also VTN = 0.75 V > 0, so the transistor is
saturated by connection.
+12 V
W = 10
L
1
10 M
330 k
IDS
+
VDS
+
V GS
K n' W
ID
VGS VTN 2 100 A2 20 VGS 0.75 2
2 L
2 V 1
VGS 12 330k I D I G 10M I G but I G = 0
VGS 12 330k I D
2
VGS 12 3.30 x10 5 10 3 2 VGS 0.75
V
2
330VGS 494VGS 173.6 0 yields VGS 0.933V , 0.564V
100 A 20
0.933 0.75 2 33.5 A
2
2 V 1
ID
4.125
(a) Both transistors are saturated by connection and the two drain currents must be equal.
I D1
K n1
K
VGS1 VTN 1 2 and I D 2 n 2 VGS 2 VTN 2 2
2
2
But since the transistors are identical, ID1 = ID2 requires VGS1 = VGS2 = VDD/2 = 2.5V.
I D1 I D 2
100 x10 6 20
2
2.5 1 = 2.25 mA
2
1
(b) For this case, the same arguments hold, and VGS1 = VGS2 = VDD/2 = 5V.
I D1 I D 2
100 x10 6
2
20
2
5 1 = 16.0 mA
1
(c) For this case, the threshold voltages will be different due to the body-effect in the upper transistor. The drain currents
must be the same, but the gate-source voltages will be different:
VGS1 VTN 1
VTN 1 = 1V
2I D
2I D
; VGS 2 VTN 2
; VGS1 VGS 2 5V .
Kn
Kn
5 - 2VGS1 0.5 VGS1 0.6 0.6 0 VGS1 2.27V ; VGS 2 5 VGS1 2.73V
I D 2 = I D1
100 x10 6 20
2
I D2 =
100 x10 20
2
4.130
For VGS = 5 V and VDS = 0.5 V, the transistor will be in the triode region.
ID
5 0.5V
68k
5 0.75
0.5
W 0.331
1
0.5 |
2
L
1
3.02
4.132
(a) The transistor is saturated by connection. For this circuit,
VGS V DD I D R 15 75000 I D
4 x10 5 1
2
15 75000 I D 0.75 153 A
2 1
15 75000 I D 3.525V
ID
VGS
(b) Here the transistor has VGS = -15 V, a large value, so the transistor is most likely operating in the triode region.
V DS 15
V
15 0.347
Checking : I D
V 195A
Q - point : 195 A,-0.347 V
785k
ID
(a) I DP I DN , and both trans istors are saturated by connection . 10 = -VGSP VGSN
1 40 A
2 V2
1 100A
20
2
10 VGSN 0.75
2 V2
1
9.25 VGSN
20
2
VGSN 0.75
1
However, VSGP 10 V, so the PMOS transisto r will probably be in the triode region.
VDSP = -10 + VGSN . Equating the drain currents,
40A
2
V
20
10 0.75
10 VGSN
2
1 100A
10 VGSN
2 V2
20
2
VGSN 0.75
1
2
Rearanging yields a quadratic equation : 3.5VGSN
4.25VGSN 83.6 0
1 100A 20
2
VGSN 5.70 V , VDSP 4.30 V , I DN
4.137
4V
2mA. For I D 0, VDS 4V . VSD 4V
2k
300k
4V
3V VSG 3V
300k 100k
For VDS 0, I D
VGS VEQ
From the graph, the transistor is operating below pinchoff in the linear region.
VGS = -4 V
2000
VGS = - 3 V
VGS = -2 V
Load Line
Q-Point
1500
1000
500
0
1
-1
-2
-3
-4
-5
-6
-500
Drain-Source Voltage (V)
4.138
(a ) VGG
5
20
15V
5
5 4 x10
4.139
Setting W=20U, L=1U, LEVEL=1, KP=40U, VTO=-0.75 yields results identical to the previous problem.
4.147
2 I D
VGS VTP
2 500A
W 25
.
1
L
1
R1
9 R1 R2
9
4.75 9
R1
2 M
R1 2.01M 2M | V EQ 9
4.74V
R1 R2
1.8M 2M
4.74V 1.75V
933
5.97k 6.2k | R D
6.0k 6.2k
0.5mA
0.5mA
Note that R 1 is connected between th e gate and + 9 V, and R 2 is connected between
RS
4.154
Region. Therefore
2 I DSS
V DS
2 5 x10 4
V
GS P
DS
2
V P2
3 2
V
8200 I DS
VP
3
4.158
Assume J1 is in the triode region and J2 is saturated.
(a) I D1
I D2
2 I DSS
V
V
V
2 0.2mA
V
I DSS 1 GS 2
VP
0.5mA 1 GS 2
4
0.5mA 1 DS1
4
V
V
4.163
(a) Use V = 6V . For R = 0, VGS 0, and I D I DSS 500 A | Q - point : 500 A, 6.00 V
VGS
10 4 I D
500A 1
(b) Assume saturation : I D I DSS 1
VP
3
I D 140.8A
VGS
10 5 I D
500 A 1
(c) Assume saturation : I D I DSS 1
V
3
P
I D 23.49 A