2009 International Conference on Emerging Technologies

FPGA Implementation of a Low power, Processorindependent and Reusable System-on-Chip Platform

Ehsan ul haq, Muhammad Kazim Hafeez, Muhammad Salman Khan, Shoaib Sial, Arshad Riazuddin
ASIC and Chip Design Department
PalmChip Private Limited
Islamabad, Pakistan
{ehsanulhaq, kazim, salman, shoaib, arshad }@palmchip.com
Abstract In order to achieve low cost and reduced time to
market goals ASIC and Embedded system designers have always
struggled to come up with a basic platform, which once built and
verified can easily be reconfigured and reused. Moreover they
are also been challenged with compatibility issues of their designs
with different processors. In this paper, we have presented a
System-on-Chip (SoC) platform architecture, which once built
can be modified for different processors with minimal effort.
Using a bus architecture that allows easy addition and removal of
various modules, our proposed SoC can be reconfigured and
reused as a platform for various projects. Moreover, we have
also included those modules in our chip which are the building
blocks of almost all ASIC and embedded applications. Finally,
implementation parameters of this SoC on Xilinx FPGA are
reported.
Keywords-FPGA;
Low
power;
reusable; System-on-Chip (key words)

I.

processor-independent;

INTRODUCTION

In recent years, the advancements in silicon industry have

seriously challenged Moores Law with its ever increasing
number of transistors on a chip. Today an easy access to
multi-million gates has made FPGAs an indispensable part of
embedded and ASIC applications. With this the complexity
of designs has increased while time to market window has
never been shorter. To meet these constraints the concept of
IP reuse and reconfigurability is becoming more and more
inevitable, especially for academia and starters. Owing to the
low budget, starters have to keep the non recurring
engineering (NRE) cost as low as possible. Similarly,
university students have to cope with the pressure of
submitting a completely verified design in very short time.
In this paper, we have explained the research and results of
designing a fully integrated, verified and working open core
SoC platform. A purpose of this project was also to help
academia by providing them a basic platform, so that they can
study it and build up their own modules by using it as a base.
To meet the above mentioned goals, we designed an
industry standard processor independent SoC platform
architecture. The processor independence allows designers to
easily modify it for their own processor without worrying
about the rest of the system. Moreover, the architecture is
built around PalmBus [6], which is a silicon-industry proven,
high performance, widely-used, on-chip point-to-point bus
designed specifically for multi-million gate SoC designs. It
allows designers to easily add or remove modules from this

978-1-4244-5632-1/09/$26.00 2009 IEEE

base platform without developing complex wrappers around

their modules. We have also integrated a number of basic
building blocks of embedded system application, like Timers,
interrupt controller, general purpose input outputs (GPIO),
UART, Real time clock (RTC) etc into this SoC, to make it
more reliable platform for all embedded and ASIC
applications.
Once built and verified, Professional designers and
engineering students can easily reuse it to integrate their
modules in it, allowing them to focus, debug and verify only
their own modules. Hence, NRE cost and production time are
significantly reduced.
In next section we have described the over all chip
architecture. Section III explains what makes this architecture
processor independent. After that section IV reveals the logic
behind reusability of this SoC platform. In section V we have
described a block from our chip as an example to show how
each block is implemented and interfaced in our chip. In
section VI we have included the block diagrams of all
modules that we implemented for reference proposes. Section
VII contains results of implementation on Xilinx FPGA. After
that Section VIII concludes this paper.
II.

SOC ARCHITECTURE

This paper focuses only on that logic which is implemented

in FPGA. At the system level FPGA will interface to a
processor through the external bus interface of the processor.
In our system we used an ARM based processor. Fig. 1 below
gives a high level architecture of how various blocks are
implemented and interfaced inside the FPGA.
Whole architecture is centered on PalmBus, which is a
point-to-point on-chip bus protocol. In Fig. 1, The General
Purpose Input Output (GPIO) block implements
general purpose input-output ports of the SoC. The GPIO pins
are very helpful in implementing general purpose low speed
interfaces without wasting specific pins for these interfaces, as
all users might not be interested in this feature. The Real
Time Clock (RTC) provides the user with real time data in
units from centuries down to seconds. Alarm features are
available to give either a one time interrupt or recurring
interrupts to the processor for real time processing
applications. A real time clock is used to keep the system
time. The Organic LED (OLED) displays can provide a
graphical user interface to various applications. Timer block
implements timers, which can be used for code profiling,

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clock generation, monitoring healthy state of chip and for

generating periodic interrupts based on user functionality.

Figure 2: Block diagram of CPU interface controller

IV.
Figure 1: Block diagram of proposed SoC architecture

The interrupt controller block will prioritize and forward the

interrupts from all the blocks inside the chip as well as from
outside the chip to the processor. The Universal Asynchronous
Receiver-Transmitters (UART) provides a mechanism for
serial communication and implements 16550-compatibile
UART. Likewise for communication with various SPI [10]
and I2C [8] compatible devices, SPI and I2C blocks implement
their specifications respectively. The CPU interface controller
decodes the processor requests and generates a PalmBus
request to one of the peripherals. The System controller
module contains registers which control the clock and reset
inputs to all the on-chip modules. To make our design power
efficient we included a power management unit (PMU)
module. PMU enables and disables the clock to various onchip peripherals, so that idle blocks can be put to sleep mode
and power can be conserved.
Each module has a register sub-module and a PalmBus
interface sub-module. The registers sub-module contains all
the registers of a module which can be programmed to achieve
various modes of operation for that particular block. The CPU
gains access to these register through the PalmBus interface so
that these devices can be programmed as per requirement.
III.

CPU INTERFACE

One of the major features of our architecture is its processor

independence. It is achieved by adding a CPU interface block
between processor and PalmBus controller. To add any 8, 16
or 32 bit processor the designer simply has to develop a CPU
interface block which provides the translation of CPU requests
to the PalmBus requests and inserts required number of wait
states. Moreover, it handles the address decoding for memory
accesses from the CPU, including the reporting of access
errors.
In our design we have used an ARM9 based processor.
Fig. 2 shows a block level diagram of CPU interface controller
module. The CPU interface controller basically decodes 64MB
address space with processor requests to generate PalmBus
request.

PALMBUS CONTROLLER

To meet our design targets of reusability, performance,

reduced design time and ease of use PalmBus is at the heart of
our SoC architecture. PalmBus is Palmchip Corporations bus
which is extensively being used in many chips in ASIC
industry. Using it as a part of university projects will bring
students a step closer to the silicon industry.
PalmBus is a master-slave interface with a single master
which is usually a CPU core that controls the bus through its
PalmBus interface controller. Unlike other on chip buses
connecting a module to PalmBus requires simple address
decoding. Configuring (writing to registers) and checking
status (reading registers) of the attached module through CPU
requires simple straight forward logic and little verification
time. PalmBus controller is used for communication between
CPU interface and multiple peripheral blocks. Timings of
PalmBus controller are synchronous to the system clock.
CPU interface controller generates the PalmBus request on
the basis of interpretation of CPU request. There are two types
of request available; either it could be writing data request or
reading data request. Direction pin will be used by the CPU
interface to differentiate the request. There are separate 32-bit
wide buses available for data read/write and byte selection bits
are used to select the appropriate bytes of data. PalmBus
controller is responsible for decoding the address provided to it
by CPU interface controller to generate the appropriate
peripheral blocks read/write request. It also generates the
ready signal on completion of transfer. Next a brief description
of each block of PalmBus controller is given.
A. Decoder
It decodes the address provided from the CPU interface and
generates the appropriate selection signal of a peripheral.
B. Request Generator
It generates the read or write request of the selected
peripheral on the basis of direction signal from CPU interface.
C. Data Path
It controls the data that is to be read from or written to the
selected peripheral. It also generates the ready signals of the
selected peripheral.

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Figure 4: Block diagram of I2C module

VI.

BLOCK DIAGRAMS OF REMAINING MODULES IN SOC

Figure 3: Block diagram of proposed SoC architecture

V.

I2C BLOCK STUDY AS AN EXAMPLE

The Serial Inter Integrated Circuits (I2C) Controller Block is

designed to communicate with various I2C devices. In our
design I2C module is configurable and can be configured to
operate either as master or slave. It is controlled by firmware
to perform different functions. A block level diagram of I2C
module showing different sub-modules in it is shown in Fig. 4.
In I2Cs block diagram, the Register module contains all the
registers of I2C. These registers consist of configuration
register, which defines devices mode of operation as well as
data, address and status registers. PalmBus Controller block
interfaces the I2C module to the PalmBus. It contains simple
logic that does address decoding, generates registers write and
read strobes as well as other PalmBus tasks. The clock
generator module divides down the system clock coming in to
the module by divider value programmed in a configuration
register in Registers module. The shift register converts
parallel data to serial data for transmission on serial data pin of
the I2C block, and convert serial data to parallel data from
serial data pin of I2C block for saving in the registers. Only
one byte is loaded into the shift register as I2C needs to
receive/transmit an acknowledgement after every byte. The
loading and unloading of the shift register block with parallel
data is controlled by state machines. The master state machine
module controls generation of I2C clock and the loading and
shifting of data when device is operated in master mode. It
also checks for transmission and reception of
acknowledgement signals from attached slave device. In slave
mode, slave state machine module controls the data
transmission, reception and proper acknowledgment to and
from the attached master device.

Figure 5: Block diagram of timer module

Figure 6: Block diagram of RTC module

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Figure 7: Block diagram of GPIO module

Figure 11: Block diagram of OLED interface controller module

Figure 8: Block diagram interrupt controller module

Figure 12: Block diagram of UART module

VII. FPGA IMPLEMENTATION PARAMETERS

After complete verification and debug this design was
implemented on Xilinx Spartan3 XC3S2000-5FG676 [11]
FPGA. It runs at clock speed of 33.3MHz and with 30ns
period. Total gate count was 0.4084 Million gates, moreover,
design only occupied 19% FPGA slices.
Figure 9: Block diagram of SPI module

Figure 10: Block diagram of PMU module

VIII. CONCLUSION
This paper presents the idea behind the architecture of a
low-power, processor-independent and reusable SoC platform.
It describes the overall structure of this SoC, describes how
processor independence and reusability is achieved and
presents the block level diagrams of each module in the chip.
Each module of the chip is designed keeping reusability in
mind so any module can be easily removed from this SoC or
additional modules can be added with minimum effort. The
modules which are implemented in the platform support
different modes of operation, and these various modes are
configurable through programmable registers, thus providing
another level of reusability at the module level.
Implementation of this whole SoC platform on FPGA took
only 0.4084 Million gates. Hence a lot of resources are
available for building future projects using it as a base.

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[4]

ACKNOWLEDGMENT
This research was supported by National ICT R&D. This
particular platform will be licensable under the National ICT
R&D open source policy.
REFERENCES
[1]

[2]

[3]

Tony Givargis and Frank Vahid, Platune: A Tuning Framework for

System-on-a-Chip Platforms, IEEE transactions on computer-aided
design of integrated circuits and systems, vol. 21, no. 11, November
2002.
Andrea Lodi, Andrea Cappelli, Massimo Bocchi, Claudio Mucci,
Massimilano Innocenti, Claudia De Bartolomeis, Luca Ciccarelli,
Roberto Giansante, Antonio Deledda, Fabio Campi, Mario Toma, and
Roberto Guerrieri, XiSystem: A XiRisc-Based SoC With
Reconfigurable IO Module, IEEE journal of solid-state circuits, vol. 41,
no. 1, January 2006.
Soo Ho Chang and Soo Dong Kim, Reuse-based Methodology in
Developing System-on-Chip (SoC), Proceedings of the Fourth
International Conference on Software Engineering Research,
Management and Applications (SERA06).

341

Kwanghyun Cho, Jaebeom Kim, Euibong Jung, Sik Kim, Zhenmin Li,
Young-Rae Cho, Byeong Min, Kyu-Myung Choi, Reusable Platform
Design Methodology For SoC Integration And Verification, 2008
International SoC Design Conference.
[5] Bill Cordan, An Efficient Bus Architecture for System-On-Chip
Design, IEEE 1999 Custom Integrated Circuits Conference
[6] Palmchip Corp. CoreFrame II Bus Specification
[7] Atmel
Corporation. AT91 ARM
Thumb Microcontrollers
AT91SAM9XE128 AT91SAM9XE256 AT91SAM9XE512 Datasheet.
[Online]
Available:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=605
[8] NXP Semiconductors. I2C bus specification and user manual. [Online]
Available: http://www.nxp.com/acrobat/usermanuals/UM10204_3.pdf
[9] Texas Instruments. Asynchronous Communications Element with
Autoflow
Control
(Rev.
E).
[Online]
Available:
http://focus.ti.com/docs/prod/folders/print/tl16c550d.html
[10] Freescale Semiconductor. Serial Peripheral Interface (SPIV3) Block
Description.
[Online]
Available:
http://www.freescale.com/files/microcontrollers/doc/ref_manual/S12SPI
V3.pdf
[11] Xilinx Inc. Spartan 3 FPGA Family Datasheet. [Online] Available:
http://www.xilinx.com/support/documentation/data_sheets/ds099.pdf