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INTRODUCTION
Intodayshandheldandportableapplicationsmarket,powerpriceandspaceformthecruxof
thecompetition,especiallywithFPGAsandCPLDsplayinganincreasinglyimportantrolein
meetingmarketdemandsofconvergence,innovation,andtimetomarket.Thisapplication
notediscussesacreativetechnologythatreducesstaticpowerconsumptiontoevenlower
levelsthatwerepreviouslythoughtunreachable.
StaticpowerisbasedonthecurrentthatisdrawnbytheFPGAwhenitispoweredup,
configured,anddoingnowork.DeepwithintheFPGA,transistorsleakcurrentevenwhenthey
arenotswitching.Leakagevariesfromoneprocesstoanother,dependingontheoxidelayer
thickness.ThisformofstaticcurrentiswhatmostFPGAvendorsdeclareintheirtechnical
documentation.Practicallyhowever,truestaticpowerisseldomreachableinadesignwhere
I/OsaretogglingandinputsareswitchingevenwhentheFPGAisinstandbymodeorsimply
doingnowork.WhatmostFPGAvendorsdeclareastheirstatic/standbylowpoweris
unrealisticandcannotbereachedinanydesignexample,wheretypically,inputsareswitching
andI/Osaretoggling.WhatSiliconBlueoffersisacreativemethodologytoovercomethis
problembyblockingunwantedinputsandthusreducingpowerconsumptiontothedefinitive
staticpowerwhereonlythefabricispoweredonbutnoI/Oiscontributingtofinalpower
consumption.iCEGATEisaprogrammableON/OFFswitchthateliminatesunnecessarytoggling
ofinputswhenthesearenotinuse.
iCEGATE
InatypicalCPLD/FPGAdesign,externallogicisneededtoblockswitchinginputs,thusraising
systempowerandcost.Truestaticpowercannotbepracticallyachievedunlessinputsare
beingblockedbyacertainmechanism.Nodesigncanoperatewithzeroinputstoggling.
iCEGATEallowstruestaticpowertohappenwithoutusinganyexternalresources.
iCEGATEisimplementedintwostages.ThefirststageconsistsofaBankLatchEnablecontrol
signal(iCEGATEHOLD)thatpropagatesthroughoutallpreIOcellspertainingtoonebank.The
controlsignaloptionallyenablesasynchronousinputswithinabankandsavespowerby
selectivelyinhibitingswitchingofinputsignalsduringlowpoweroperation.Asecondstage
consistingofconfigurationbitsthatcontroleachindividualpinsparticipationiniCEGATE.
1
IndividualpinswithintheI/ObankcanbypasstheInputEnablecontrolandfeeddirectlyinto
theProgrammableInterconnect,remainingactiveduringlowpoweroperation.
iCEGATEcircuitryisimplementedinaninterfacecellbetweenthelogiccoreandtheI/Ocell
thatiscalledthePREIOcell.ThefigurebelowshowsPREIOCellarchitectureandiCEGATE
implementation.
PRE-IO CELL
Input Clock
iCEGATE
HOLD
cbit[1]
LOGIC CORE
cbit[0]
Figure1:PreIOCellArchitecture
Thefollowingtableshowstheinputs,outputs,andcontrolspertainingtotheiCEGATEdesignin
thePREIOcell:
Table1:PreIOCellSignalDescription
Signal
Description
InputClock
iCEGATEHOLD
cbit[1:0]
EnablesthetworegistersD0andD1
Bankenablesignal
Configurationbitsforindividualpincontrol
iCEGATE_HOLDsignalissharedamongallI/Osplacedinthesamebank.Sucharchitecturegives
iCEGATEaninherentadvantageoverotherarchitecturesbycompetitorswhereinputblockingis
implementedviaarailthataffectsallbanksandallI/Osatonce.
hieveUlttraLowPower
UsingiCEGATEtoAch
Wedesiggnasampleapplicationwherethecchipisfilledw
with88load
dablecounteers.Weruntthe
codefrom
mtwodifferrentclockso
ources:32M
MHzoscillator,and32kH
Hzoscillator.Bothinputssare
sourcedtthroughglob
balbufferinputs.Theou
utputoftheglobalbuffeerconnectsttotheCLKin
nput
oftheProgrammable
eLogicBlockkinuse.TheeCLKsignaliissharedam
mongallflipfflopsina
wingpowerb
bypropagatiing
programmablelogicblock.Thus,,aclocksourcecanbeaactivelydraw
througho
outtheFPGA
Afabriceven
nwhennotb
beingused.Thefollowin
ngfiguresho
owstheMUX
X
implemeentationinan
niCE04FPGA.
Figure2:ClockMUX
XarchitecturreinaniCE0
04FPGA
TablebelowdescribesthesettingsrequiredforenablingiCEGATE:
Table2:TwoiCEGATEconfigurationsfor32MHzinput
CLK_SELECT
0
0
1
LATCH_32MHz
1
0
0
iCEGATE
ENABLED
DISABLED
DISABLED
WemeasuretheinternalpowerconsumptionontheiCE04devicebeforeweenableiCEGATE
onthe32MHzinputandthecurrentdrawis1.092mAat1.2Vwhichisequivalentto1.31mW.
WhenwedoenableiCEGATE,thecurrentdrawis51uAat1.2Vwhichisequivalentto61uW:
thatis95%powerreduction!
ThetablebelowshowsthevariouspowerconsumptionnumbersdependingoniCEGATE.
Table3:StaticPowerConsumptionwithiCEGATE
SystemMode
Description
iCEGATEEnabled
LowSpeedOperation Yes
(32kHz)
LowSpeedOperation No
(32kHz)
PowerConsumption
61uW
1.31mW
Figure1belowshowstheevaluationboardsetupwithammetermeasuring1.092mA.
Figure3:Ammeterreadingof1.092mAbeforeenablingiCEGATE
Figure2showsthecurrentdroppingto51uAafterenablingiCEGATE.
Figure4:Ammeterreadingof51uAafterenablingiCEGATE
ConfiguringiCEGATE
EverypincanbeindividuallyconfiguredwhethertouseiCEGATElatchenableornot.The
followingisaninputpinfunctiontruthtablethatshowsthefunctionaldescriptionbasedonthe
pintypebitassignment.ThedesignermustthensetthepintypeinHDLcodetoparticipatein
iCEGATEandtheinputtobeblockedappropriately.Thefollowingtableshowsthetwo
configurationbitsPIN_TYPEassociatedwitheachindividualpin.
Table4:InputPinFunctionTruthTable
ParameterNameMnemonic
PIN_TYPE[1:0]
FunctionalDescriptionofPackage
PinInputOperation
1 PIN_INPUT
Simpleinputpin
2 PIN_INPUT_LATCH
Disablesinternaldatachangesonthe
physicalinputpinbylatchingthe
value.
3 PIN_INPUT_REGISTERED
Inputdataisregisteredininputcell
Disablesinternaldatachangesonthe
physicalinputpinbylatchingthe
valueontheinputregister
4 PIN_INPUT_REGISTERED_LATCH
DesignersmustfollowthethreesimpleguidelinesinimplementingiCEGATE:
1. IfIOcelldoesnotusetheLatchfunction:leaveLATCH_INPUT_VALUE(iCEGATEenable)
unconnectedandsetPIN_TYPE[1]=0;
2. IfIOcellusestheLatchfunction:connectLATCH_INPUT_VALUE(iCEGATEenable)tothe
controlsignalandsetPIN_TYPE[1]=1;
3. ItisalegalplacementifallIOsassignedtothesamebankwhereallIOswith
PIN_TYPE[1]=1havethesameLATCH_INPUT_VALUE,andtherestoftheIOswith
PIN_TYPE[1]=0.
ThedesignerimplementsiCEGATEinHDLcode.Thefollowingcodesnippetsdemonstratehow
weimplementediCEGATEfunctionalityonthe32MHzoscillatorinput.
First,thebanklatchenableisdefinedasindicatedinredinthefollowingcode:
Component SB_IO is
GENERIC (
PIN_TYPE: STD_LOGIC_VECTOR (5 downto 0));
Port (
PACKAGE_PIN: in_STD_LOGIC;
LATCH_IPUT_VALUE : in STD_LOGIC;
D_IN_0 : out STD_LOGIC
);
end component;
ThecodebelowshowstheIOcellconfigurationandthemappingoftheBankLatchEnable
signal(LATCH_INPUT_VALUE)tothe32MHzclockenableinputsignal.
CLK32MHz_Buffer: SB_IO
generic map (
PIN_TYPE => 000011)
Port map (
PACKAGE_PIN => CLK_32MHz,
LATCH_INPUT_VALUE => LATCH_32MHz,
D_I_0 => CLK_32MHz_GB
);
Consecutively,theBankLatchEnableisnegatedandconnectedtotheclockselectoftheclock
mux.Whentheselectsignaloftheclockmuxiszerothe32kHzinputisactive,whichmeans
thatthe32MHzinputmustbelatchedsoiCEGATEisenabled.
LATCH_32MHZ <= not (CLK_SELECT)
iCEGATEvs.LowPowerMode
Lowpowermodesorsleepmodesareprevalentintodayslowpowerintegratedcircuits.
Whilethesemodesdopresentnumerousbenefitsforthedesigner,theylacksignificantly
behindwhattheiCEGATEtechnologycanofferintermsofpowersavings.WhatmakesiCEGATE
sopowerfulandattractiveistheabilitytoselectindividualpinswhilekeepingthedevice
operationalandlogicavailablefortherestofthechip.Suchfeaturesarenotpermissibleinlow
powermodeschemes.
SUMMARY
PortableApplicationsareparticularlysensitivebecausetheydrawalotofbatterypower.Anew
methodologytoreducestaticordynamicpowerconsumptioncanbeveryeffectivein
improvingbatterylife.iCEGATEwasdesignedtostopunwantedinputswitchingfrom
continuouslydrainingpowerandthatcanleadtonearly95%decreaseinpowerconsumption.
WithpowersavingtechniquessuchasiCEGATE,iCEFPGAsallowdesignerstobuildfullcustom
designseasilymeetingtargetsforsystemcostandpower.