VLSI Wiring Capacitance Determination

N.P. van der Meijs, A.J. van Genderen

Delft University of Technology, The Netherlands
Introduction

Parallel Line Example

150

With the increase of device density, usually only the

horizontal dimensions are reduced. The vertical
dimensions are (approximately) kept constant.
Consequently,

a
a

(pF/m)

capacitances are not scaled linearly

coupling
capacitances
capacitances

dominate

substrate

a
a

Technology
The capacitances presented refer to a hypothetical
but realistic MOS process with perfect planarization
and the following layer thicknesses:

i iiiiiiiiiiiiiiiiiiiiiii

gate oxide
250A
inter wires oxides 0.75
poly
0.5
metal 1
0.75
metal
2
1.0
i iiiiiiiiiiiiiiiiiiiiiii

Cpp

space and width (microns)

Top right: characteristic capacitance components

per unit length for middle conductor. (Cs = short
circuit capacitance, total capacitance when other
conductors have a low impedance)
Bottom right: The same capacitances normalized
to the parallel plate capacitance to show the
relative magnitudes at small dimensions more
clearly.

30
Cs /Cpp
20

C 12 /Cpp

10

Cgnd /Cpp

Note:

a
a

Total capacitance Cs increases with smaller

dimensions.

space and width (microns)

Total coupling capacitance (2 C 12 ) dominates

Cgnd for width/spacing 2 .

Design Implications
2.5

width

(fF)

Using incorrect capacitance values in the design loop

can result in

C 3d

1.5

a
a
a

C 2d

lower then expected performance

higher then expected dissipation
unreliable or incorrect circuit behavior

Cpp

width

0.5

Above: crossing metal 1 and metal 2 lines

Top right: Parallel-plate (Cpp ), 2-dimensional (C 2d )

and 3-dimensional (C 3d ) computations of the
coupling capacitance.
Bottom right: The same capacitances normalized
to the parallel plate capacitance to show the
relative magnitudes at small dimensions more
clearly.

width (microns)

To obtain correct values, the program SPACE can be

used.
SPACE is a layout to circuit extractor that uses 3dimensional finite element methods to accurately
determine interconnect capacitances.

20
15

SPACE employs a new approximative matrix

inversion technique, which makes the program
capable of rigorous finite element modeling of
substantial circuits even on small workstations.

C 3d /Cpp

Note:

Above: three parallel metal 2 interconnects

Crossing Line Example

Cgnd

50

C 12

This poster analysis the scaling behavior of

interconnect
capacitances,
discusses
design
implications, and introduces a layout to circuit
extractor
that
accurately
determines
these
capacitances for state of the art technologies.

a
a

Cs

100

Parallel-plate and 2-dimensional approximations

are inaccurate for state of the art technologies.

10
C 2d /Cpp
5
0

width (microns)

SRAM Example

SPACE Features

a
coupling coupling

a
ground

ground

a
a

coupling coupling coupling

ground
gate

gate

1
2
25.5 fF 25.5 fF

ground

ground

gate

notbit
9.8 fF

bit
9.8 fF

word
8.7 fF

Fully automatic extraction from layout to circuit,

including devices and (parasitic) capacitances and
resistances, that can directly be simulated with
e.g. SPICE.
Trade off possible between accuracy and cpu
time.
Cpu time is linear in the size of the layout.
Memory requirements are nearly independent of
the size of the layout.

Finite element mesh of the ram cell.

A breakdown of capacitance values for a 6 transistor
sram cell, which was extracted with SPACE.

This mesh was automatically generated from the

layout description and a technology description.

See also:

Note:

a
a
a

The large ground capacitances for node 1 and 2

are diffusion capacitances.
The high bitline (coupling) capacitances cause
severe signal degradation at the sense amplifiers.
When this cell is embedded in a 2-dimensional
array, the ratio of coupling and substrate
capacitances will even be higher.

SRAM Extraction Results

iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
number of finite elements
1537
memory needed
9.2 Mbyte
cpu time (HP 9000/835, min:sec)
19:44
iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii

N.P. van der Meijs and A.J. van Genderen,

Space: An Accurate and Efficient Extractor for
Submicron Integrated Circuits, Delft Progr. Rep.
12Delft, pp. 260-279 (1988).
N.P. van der Meijs and A.J. van Genderen, An
Efficient Finite Element Method for Submicron IC
Capacitance Extraction, Proc. 26th Design
Automation Conference, Las Vegas, pp. 678-681
(June 1989).