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MOS Transistors
2.1
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IC design
Gate
Source
Drain
polysilicon
oxide
n+
channel length(L)
n+
gate
source
drain
substrate
Substrate
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IC design
Source
Drain
polysilicon
oxide
p+
channel length(L)
p+
gate
source
drain
substrate
Substrate
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IC design
2.2
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IC design
Step 1:
VGS <VT
GATE
VDS = 0V
oxide
SOURCE
(n+)
DEPLETION REGION
DRAIN
(n+)
SUBSTRATE: p-Si
Vsub= 0V
We start with case when the gate voltage, VGS is smaller than the
threshold voltage, VT . The drain voltage, VDS is in this situation
irrelevant and can be zero.
The electric field induced by the gate voltage points down from the
gate through the channel. This fields repels the majority carriers for the
p-type substrate, that is, positive holes, from the channel hence
forming a region depleted of carriers as shown in Figure 2.3.
As a result, due to the lack of free carriers, no current flows between
the source and the drain at this stage, that is, ID = 0.
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Step 2:
In this case (Figure 2.4), when the gate voltage VGS increases above
VS = 0V
VGS >VT
GATE
oxide
SOURCE inversion layer (source--drain channel)
DEPLETION REGION
(n+)
VDS = 0V
DRAIN
(n+)
SUBSTRATE: p-Si
Vsub= 0V
Figure 2.4: Formation of the conducting channel (inversion layer) in an enhancementmode nMOS.
the threshold voltage VT , then the electric field repels more holes from
the channel area leaving an excess of electrons.
The field also pulls out electrons from the source and drain area which,
by virtue of being the n+ regions, have excess of electrons.
As a result in the area between source and drain an inversion layer is
created in which there is an excess of the negative carriers, that is,
electrons. In other words a conducting channel has been formed
between the source and drain.
Due to the fact that in this case we assume that the drain-source
voltage VDS = 0, thermal equilibrium exists in the channel region and
the drain current, ID = 0.
The threshold voltage VT depends on a specific transistor
configuration, that is, on a specific technology of fabrication of MOS
transistors and usually is in a range of 0.5V.
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IC design
VS = 0V
GATE
VDS > 0V
oxide
SOURCE
(n+)
DRAIN
(n+)
CHANNEL
DEPLETION REGION
SUBSTRATE: p-Si
Vsub= 0V
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VS = 0V
GATE
VDS = Vsat
oxide
SOURCE CHANNEL
(n+)
PINCH-OFF POINT
DRAIN
(n+)
DEPLETION REGION
SUBSTRATE: p-Si
Vsub= 0V
When the source-drain voltage, VDS , reaches a certain value, Vsat , the
channel depth at the drain end is reduced to zero. This is called the
pinch-off point. In other words, at the pinch-off point, VDS = Vsat .
From now on, the further increase of the source-drain voltage does not
result in an increase of the source-drain current. The transistor now
operates in the saturation mode.
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IC design
VGS >VT
GATE
oxide
SOURCE CHANNEL
(n+)
PINCH-OFF POINT
DRAIN
(n+)
DEPLETION REGION
SUBSTRATE: p-Si
Vsub= 0V
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2.3
L
Polysilicon
Diffusion
Diffusion
Gate
Cross-Section
Poly
n+
Diffusion
tox
n+
Diffusion
SUBSTRATE, p - Si (WELL)
210
Diffusion areas (source and drain) are created inside a substrate (also
known in some technological context as the well) of the opposite type,
e.g. n+ diffusion inside the p substrate, where n+ indicates silicon
highly doped with donors.
From the top and cross-sectional views of the MOS transistor
presented in Figure 2.8 we note that three basic geometrical parameters
of the transistor are the following:
L and W the length and width of the conducting channel
between the source and drain,
tox thickness of the oxide layer between the gate and the
diffusion/substrate areas.
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ox
tox
(2.1)
where
ox = 0.351pF/cm
is the permittivity (a dielectric constant) of SiO2 . Note that the
capacitance is inversely proportional to the thickness of the silicon
dioxide layer.
Example
0.351 1012
= 0.7 107 F/cm2 = 70nF/cm2
5
0.5 10
Note that the oxide thickness and the resulting gate capacitance per
unit area are parameters specified by the technological process of
fabrication of MOS transistors.
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Values of the mobility in doped semiconductor are smaller, but the ratio
n
2.5
p
(2.3)
is preserved. The fact that holes are more sluggish than electron has
some influence on relative sizes of nMOS and pMOS transistors.
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pMOS
VDD
ID
d
sub
VGS
g
VDS
s
sub
VDS
d
ID
VGS
GND (VSS)
n-type Si substrate
p diff
drain
holes
p diff
source
gate
electrons
p-type Si substrate
n diff
source
gate
n diff
drain
VDD
GND
The nMOS transistor has its source and the p-type substrate connected
to the ground terminal GND (VSS ) = 0V, whereas the pMOS transistor
has its source and the n-type substrate connected to VDD = 25V.
The VGS and VDS voltages are positive for the nMOS transistor and
negative for the pMOS.
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2.4
(2.4)
(2.5)
2
L
It is also convenient to use a gate voltage relative to the threshold
voltage defined as follows:
gc =
V = VGS VT
(2.6)
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pMOS
Cut-off region:
|
VGS < VT n
VGS > VT p
ID = 0
Linear region:
VGS VT n , VDS < Vn
Saturation region:
VGS VT n , VDS Vn
VGS VT p , VDS Vp
ID = gc V2
Table 2.1: Fundamental DC relationships for MOS transistors
Note that the drain current ID is proportional to the ratio W/L of the
transistor channel size. For given process parameters and voltages,
the wider the transistor channel, W , the larger ID current, and
the longer the transistor channel, L, the smaller ID current.
Note also that the saturation occurs when
VDS = VGS VT = V
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At the saturation point the current expressions for the linear and
saturation regions are identical what can be seen from the following
derivation:
Isat = gc (2V V V2 ) = gc V2
(2.7)
Example
20
= 210 106 A/V2 = 0.21mA/V2
2
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ID (mA)
3
VGS = 4 V
I (mA)
VGS = 3 V
VDS (V)
|
VT 2
VGS (V)
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pMOS
nMOS
g
d
s
VGS
VDD
ON: if VGS > VT
SATURATION:
if VDS > VGS Vth
ID (VGS )
ID (VGS )
VGS
g s
GND
SATURATION:
if VDS < VGS VT
ON: if VGS < VT < 0
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2.5
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SCHEMATIC
STICK-DIAGRAM
CIRCUIT LAYOUT
G
sub
S
D
pMOS
nMOS
D
G
sub
S
GND
D
S
contact:
n substr to
metal
contact:
n diff to
metal
contact:
p substr to
metal
VDD
p diffusion
pMOS
polysilicon
polysilicon
n diffusion
nMOS
metal
VDD
contact:
p diff to
metal
metal
GND
Figure 2.12: Three representations of MOS circutry: schematics, stick diagrams and
circuit layouts.
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pMOS
L = 2
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